mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 09:08:05 -04:00
623 lines
20 KiB
C
623 lines
20 KiB
C
/****************************************************************************
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*
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* Copyright (c) 2014 - 2016 Samsung Electronics Co., Ltd. All rights reserved
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*
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****************************************************************************/
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/* Implements */
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#include "pcie_mif.h"
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/* Uses */
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/moduleparam.h>
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#include <scsc/scsc_logring.h>
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#include "pcie_mif_module.h"
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#include "peterson_mutex.h"
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#include "pcie_proc.h"
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static bool enable_pcie_mif_arm_reset = true;
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module_param(enable_pcie_mif_arm_reset, bool, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(enable_pcie_mif_arm_reset, "Enables ARM cores reset");
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struct pcie_mif {
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struct scsc_mif_abs interface;
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struct scsc_mbox_s *mbox;
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struct peterson_mutex *p_mutex_r4; /* AP will READ - CR4 will WRITE */
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struct peterson_mutex *p_mutex_ap; /* AP will WRITE - CR4 will READ */
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struct pci_dev *pdev;
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int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */
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__iomem void *registers;
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struct device *dev;
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void *mem;
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size_t mem_allocated;
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dma_addr_t dma_addr;
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/* Callback function and dev pointer mif_intr manager handler */
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void (*r4_handler)(int irq, void *data);
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void *irq_dev;
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#ifdef SUPPORTED_M4
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void (*m4_handler)(int irq, void *data);
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#endif
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};
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#define pcie_mif_from_mif_abs(MIF_ABS_PTR) container_of(MIF_ABS_PTR, struct pcie_mif, interface)
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static void pcie_mif_irq_default_handler(int irq, void *data)
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{
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/* Avoid unused parameter error */
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(void)irq;
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(void)data;
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}
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irqreturn_t pcie_mif_isr(int irq, void *data)
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{
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struct pcie_mif *pcie = (struct pcie_mif *)data;
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#ifdef SUPPORTED_M4
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/* TODO */
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#endif
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if (pcie->r4_handler != pcie_mif_irq_default_handler)
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pcie->r4_handler(irq, pcie->irq_dev);
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else
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SCSC_TAG_INFO(PCIE_MIF, "Any handler registered\n");
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return IRQ_HANDLED;
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}
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static void pcie_mif_destroy(struct scsc_mif_abs *interface)
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{
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/* Avoid unused parameter error */
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(void)interface;
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}
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static char *pcie_mif_get_uid(struct scsc_mif_abs *interface)
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{
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/* Avoid unused parameter error */
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(void)interface;
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/* TODO */
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/* return "0" for the time being */
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return "0";
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}
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static int pcie_mif_reset(struct scsc_mif_abs *interface, bool reset)
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{
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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int ret;
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if (enable_pcie_mif_arm_reset || !reset) {
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/* Sanity check */
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iowrite32(0xdeadbeef, pcie->registers + SCSC_PCIE_SIGNATURE);
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mmiowb();
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ret = ioread32(pcie->registers + SCSC_PCIE_SIGNATURE);
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if (ret != 0xdeadbeef) {
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SCSC_TAG_ERR_DEV(PCIE_MIF, pcie->dev, "Can't acces BAR0 magic number. Readed: 0x%x Expected: 0x%x\n",
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ret, 0xdeadbeef);
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return -ENODEV;
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}
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iowrite32(reset ? 1 : 0,
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pcie->registers + SCSC_PCIE_GRST_OFFSET);
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mmiowb();
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} else
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SCSC_TAG_INFO(PCIE_MIF, "Not resetting ARM Cores enable_pcie_mif_arm_reset: %d\n",
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enable_pcie_mif_arm_reset);
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return 0;
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}
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static void *pcie_mif_map(struct scsc_mif_abs *interface, size_t *allocated)
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{
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int ret;
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size_t map_len = PCIE_MIF_ALLOC_MEM;
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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if (allocated)
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*allocated = 0;
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if (map_len > (PCIE_MIF_PREALLOC_MEM - 1)) {
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SCSC_TAG_ERR(PCIE_MIF, "Error allocating DMA memory, requested %zu, maximum %d, consider different size\n", map_len, PCIE_MIF_PREALLOC_MEM);
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return NULL;
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}
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/* should return PAGE_ALIGN Memory */
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pcie->mem = dma_alloc_coherent(pcie->dev,
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PCIE_MIF_PREALLOC_MEM, &pcie->dma_addr, GFP_KERNEL);
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if (pcie->mem == NULL) {
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SCSC_TAG_ERR(PCIE_MIF, "Error allocating %d DMA memory\n", PCIE_MIF_PREALLOC_MEM);
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return NULL;
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}
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pcie->mem_allocated = map_len;
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SCSC_TAG_INFO_DEV(PCIE_MIF, pcie->dev, "Allocated dma coherent mem: %p addr %p\n", pcie->mem, (void *)pcie->dma_addr);
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iowrite32((unsigned int)pcie->dma_addr,
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pcie->registers + SCSC_PCIE_OFFSET);
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mmiowb();
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ret = ioread32(pcie->registers + SCSC_PCIE_OFFSET);
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SCSC_TAG_INFO(PCIE_MIF, "Read SHARED_BA 0x%0x\n", ret);
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if (ret != (unsigned int)pcie->dma_addr) {
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SCSC_TAG_ERR_DEV(PCIE_MIF, pcie->dev, "Can't acces BAR0 Shared BA. Readed: 0x%x Expected: 0x%x\n", ret, (unsigned int)pcie->dma_addr);
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return NULL;
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}
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#ifdef OLD_REG
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/* Allocate mbox struct at the end of the PCIE_MIF_PREALLOC_MEM */
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pcie->mbox = (void *)pcie->mem + PCIE_MIF_PREALLOC_MEM - sizeof(struct scsc_mbox_s);
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/* Allocate Peterson algo shared varialbles before mbox */
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pcie->p_mutex_r4 = (void *)pcie->mem + PCIE_MIF_PREALLOC_MEM - sizeof(struct scsc_mbox_s) - sizeof(struct peterson_mutex);
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pcie->p_mutex_ap = (void *)pcie->mem + PCIE_MIF_PREALLOC_MEM - sizeof(struct scsc_mbox_s) - 2 * (sizeof(struct peterson_mutex));
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#else
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/* Allocate mbox struct at the end of the PCIE_MIF_PREALLOC_MEM */
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pcie->mbox = (void *)pcie->mem + MBOX_OFFSET;
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memset(pcie->mbox, 0, sizeof(struct scsc_mbox_s));
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/* Allocate Peterson algo shared varialbles before mbox */
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pcie->p_mutex_r4 = (void *)pcie->mem + P_OFFSET_R4;
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pcie->p_mutex_ap = (void *)pcie->mem + P_OFFSET_AP;
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#endif
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SCSC_TAG_INFO_DEV(PCIE_MIF, pcie->dev, "pcie->mbox is pointing at %p pcie->mem %p map_len %zu sizeof %zu\n",
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pcie->mbox,
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pcie->mem,
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map_len,
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sizeof(struct scsc_mbox_s));
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#ifdef SUPPORTED_M4
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/* TODO */
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#endif
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peterson_mutex_init(pcie->p_mutex_ap);
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/* Return the max allocatable memory on this abs. implementation */
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if (allocated)
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*allocated = map_len;
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return pcie->mem;
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}
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/* HERE: Not sure why mem is passed in - its stored in pcie - as it should be */
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static void pcie_mif_unmap(struct scsc_mif_abs *interface, void *mem)
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{
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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/* Avoid unused parameter error */
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(void)mem;
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dma_free_coherent(pcie->dev, PCIE_MIF_PREALLOC_MEM, pcie->mem, pcie->dma_addr);
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SCSC_TAG_INFO_DEV(PCIE_MIF, pcie->dev, "Freed dma coherent mem: %p addr %p\n", pcie->mem, (void *)pcie->dma_addr);
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}
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#ifdef MAILBOX_SETGET
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static void pcie_mif_mailbox_set(struct scsc_mif_abs *interface, u32 mbox_num, u32 value)
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{
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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if (mbox_num >= NUM_MBOX) {
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SCSC_TAG_ERR(PCIE_MIF, "MBOX not mapped\n");
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return;
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}
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pcie->mbox->issr[mbox_num] = value;
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}
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static u32 pcie_mif_mailbox_get(struct scsc_mif_abs *interface, u32 mbox_num)
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{
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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u32 val;
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if (mbox_num >= NUM_MBOX) {
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SCSC_TAG_ERR(PCIE_MIF, "MBOX not mapped\n");
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return -1;
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}
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val = pcie->mbox->issr[mbox_num];
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return val;
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}
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#endif
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static u32 pcie_mif_irq_bit_mask_status_get(struct scsc_mif_abs *interface)
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{
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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u32 val;
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val = (pcie->mbox->intmr0) >> 16;
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return val;
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}
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static u32 pcie_mif_irq_get(struct scsc_mif_abs *interface)
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{
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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u32 val;
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val = pcie->mbox->intsr1 >> 16;
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return val;
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}
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static void pcie_mif_irq_bit_set(struct scsc_mif_abs *interface, int bit_num, enum scsc_mif_abs_target target)
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{
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volatile u32 *set_reg;
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volatile u32 *mask_reg;
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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if (bit_num >= 16) {
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SCSC_TAG_ERR(PCIE_MIF, "Incorrect INT\n");
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return;
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}
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peterson_mutex_lock(pcie->p_mutex_r4, AP_PROCESS);
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/* Set Status Register */
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if (target == SCSC_MIF_ABS_TARGET_R4) {
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set_reg = &pcie->mbox->intsr0;
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mask_reg = &pcie->mbox->intmr0;
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} else if (target == SCSC_MIF_ABS_TARGET_M4) {
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set_reg = &pcie->mbox->intsr2;
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mask_reg = &pcie->mbox->intmr2;
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} else {
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SCSC_TAG_ERR(PCIE_MIF, "Incorrect Target %d\n", target);
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return;
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}
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*set_reg |= (1 << bit_num) << 16;
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/* Check whether int is masked */
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if (*mask_reg & ((1 << bit_num) << 16)) {
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SCSC_TAG_ERR(PCIE_MIF, "Interrupt is masked - do not generate interrupt\n");
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peterson_mutex_unlock(pcie->p_mutex_r4, AP_PROCESS);
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return;
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}
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iowrite32(0xffffff, pcie->registers + SCSC_PCIE_NEWMSG);
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mmiowb();
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peterson_mutex_unlock(pcie->p_mutex_r4, AP_PROCESS);
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}
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static void pcie_mif_irq_bit_clear(struct scsc_mif_abs *interface, int bit_num)
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{
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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if (bit_num >= 16) {
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SCSC_TAG_ERR(PCIE_MIF, "Incorrect INT\n");
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return;
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}
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peterson_mutex_lock(pcie->p_mutex_ap, AP_PROCESS);
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pcie->mbox->intsr1 &= ~((1 << bit_num) << 16);
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peterson_mutex_unlock(pcie->p_mutex_ap, AP_PROCESS);
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}
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static void pcie_mif_irq_bit_mask(struct scsc_mif_abs *interface, int bit_num)
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{
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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if (bit_num >= 16) {
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SCSC_TAG_ERR(PCIE_MIF, "Incorrect INT\n");
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return;
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}
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peterson_mutex_lock(pcie->p_mutex_ap, AP_PROCESS);
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pcie->mbox->intmr1 |= ((1 << bit_num) << 16);
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peterson_mutex_unlock(pcie->p_mutex_ap, AP_PROCESS);
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}
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static void pcie_mif_irq_bit_unmask(struct scsc_mif_abs *interface, int bit_num)
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{
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int irq_unmasked;
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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if (bit_num >= 16) {
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SCSC_TAG_ERR(PCIE_MIF, "Incorrect INT\n");
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return;
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}
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peterson_mutex_lock(pcie->p_mutex_ap, AP_PROCESS);
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pcie->mbox->intmr1 &= ~((1 << bit_num) << 16);
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irq_unmasked = pcie_mif_irq_get(interface) & (1 << bit_num);
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peterson_mutex_unlock(pcie->p_mutex_ap, AP_PROCESS);
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/* Check whether the interrupt has been triggered */
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if (irq_unmasked)
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if (pcie->r4_handler != pcie_mif_irq_default_handler)
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pcie->r4_handler(bit_num, pcie->irq_dev);
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}
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static void pcie_mif_irq_reg_handler(struct scsc_mif_abs *interface, void (*handler)(int irq, void *data), void *dev)
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{
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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pcie->r4_handler = handler;
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pcie->irq_dev = dev;
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}
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static void pcie_mif_irq_unreg_handler(struct scsc_mif_abs *interface)
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{
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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pcie->r4_handler = pcie_mif_irq_default_handler;
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pcie->irq_dev = NULL;
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}
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static void pcie_mif_irq_reg_reset_request_handler(struct scsc_mif_abs *interface, void (*handler)(int irq, void *data), void *dev)
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{
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(void)interface;
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(void)handler;
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(void)dev;
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}
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static void pcie_mif_irq_unreg_reset_request_handler(struct scsc_mif_abs *interface)
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{
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(void)interface;
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}
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static u32 *pcie_mif_get_mbox_ptr(struct scsc_mif_abs *interface, u32 mbox_index)
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{
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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u32 *addr;
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addr = (u32 *)(&pcie->mbox->issr[mbox_index]);
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return addr;
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}
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static int pcie_mif_get_mifram_ref(struct scsc_mif_abs *interface, void *ptr, scsc_mifram_ref *ref)
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{
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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if (ptr > (pcie->mem + 4 * 1024 * 1024)) {
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SCSC_TAG_ERR(PCIE_MIF, "ooops limits reached\n");
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return -ENOMEM;
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}
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*ref = (scsc_mifram_ref)((uintptr_t)ptr - (uintptr_t)pcie->mem);
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return 0;
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}
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static void *pcie_mif_get_mifram_ptr(struct scsc_mif_abs *interface, scsc_mifram_ref ref)
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{
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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return (void *)((uintptr_t)pcie->mem + (uintptr_t)ref);
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}
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static uintptr_t pcie_mif_get_mif_pfn(struct scsc_mif_abs *interface)
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{
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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return virt_to_phys(pcie->mem) >> PAGE_SHIFT;
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}
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static struct device *pcie_mif_get_mif_device(struct scsc_mif_abs *interface)
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{
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struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
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return pcie->dev;
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}
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static void pcie_mif_irq_clear(void)
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{
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}
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static void pcie_mif_dump_register(struct scsc_mif_abs *interface)
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{
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}
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struct scsc_mif_abs *pcie_mif_create(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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int rc = 0;
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struct scsc_mif_abs *pcie_if;
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struct pcie_mif *pcie = (struct pcie_mif *)devm_kzalloc(&pdev->dev, sizeof(struct pcie_mif), GFP_KERNEL);
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u16 cmd;
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/* Avoid unused parameter error */
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(void)id;
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if (!pcie)
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return NULL;
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pcie_if = &pcie->interface;
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/* initialise interface structure */
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pcie_if->destroy = pcie_mif_destroy;
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pcie_if->get_uid = pcie_mif_get_uid;
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pcie_if->reset = pcie_mif_reset;
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pcie_if->map = pcie_mif_map;
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pcie_if->unmap = pcie_mif_unmap;
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#ifdef MAILBOX_SETGET
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pcie_if->mailbox_set = pcie_mif_mailbox_set;
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pcie_if->mailbox_get = pcie_mif_mailbox_get;
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#endif
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pcie_if->irq_bit_set = pcie_mif_irq_bit_set;
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pcie_if->irq_get = pcie_mif_irq_get;
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pcie_if->irq_bit_mask_status_get = pcie_mif_irq_bit_mask_status_get;
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pcie_if->irq_bit_clear = pcie_mif_irq_bit_clear;
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pcie_if->irq_bit_mask = pcie_mif_irq_bit_mask;
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pcie_if->irq_bit_unmask = pcie_mif_irq_bit_unmask;
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pcie_if->irq_reg_handler = pcie_mif_irq_reg_handler;
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pcie_if->irq_unreg_handler = pcie_mif_irq_unreg_handler;
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pcie_if->irq_reg_reset_request_handler = pcie_mif_irq_reg_reset_request_handler;
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pcie_if->irq_unreg_reset_request_handler = pcie_mif_irq_unreg_reset_request_handler;
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pcie_if->get_mbox_ptr = pcie_mif_get_mbox_ptr;
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pcie_if->get_mifram_ptr = pcie_mif_get_mifram_ptr;
|
|
pcie_if->get_mifram_ref = pcie_mif_get_mifram_ref;
|
|
pcie_if->get_mifram_pfn = pcie_mif_get_mif_pfn;
|
|
pcie_if->get_mif_device = pcie_mif_get_mif_device;
|
|
pcie_if->irq_clear = pcie_mif_irq_clear;
|
|
pcie_if->mif_dump_registers = pcie_mif_dump_register;
|
|
|
|
/* Suspend/resume not supported in PCIe MIF */
|
|
pcie_if->suspend_reg_handler = NULL;
|
|
pcie_if->suspend_unreg_handler = NULL;
|
|
|
|
/* Update state */
|
|
pcie->pdev = pdev;
|
|
|
|
pcie->dev = &pdev->dev;
|
|
|
|
pcie->r4_handler = pcie_mif_irq_default_handler;
|
|
pcie->irq_dev = NULL;
|
|
|
|
/* Just do whats is necessary to meet the pci probe
|
|
* -BAR0 stuff
|
|
* -Interrupt (will be able to handle interrupts?)
|
|
*/
|
|
|
|
/* My stuff */
|
|
pci_set_drvdata(pdev, pcie);
|
|
|
|
rc = pcim_enable_device(pdev);
|
|
if (rc) {
|
|
SCSC_TAG_ERR_DEV(PCIE_MIF, pcie->dev,
|
|
"Error enabling device.\n");
|
|
return NULL;
|
|
}
|
|
|
|
/* This function returns the flags associated with this resource.*/
|
|
/* esource flags are used to define some features of the individual resource.
|
|
* For PCI resources associated with PCI I/O regions, the information is extracted from the base address registers */
|
|
/* IORESOURCE_MEM = If the associated I/O region exists, one and only one of these flags is set */
|
|
if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
|
|
SCSC_TAG_ERR(PCIE_MIF, "Incorrect BAR configuration\n");
|
|
return NULL;
|
|
}
|
|
|
|
/* old --- rc = pci_request_regions(pdev, "foo"); */
|
|
/* Request and iomap regions specified by @mask (0x01 ---> BAR0)*/
|
|
rc = pcim_iomap_regions(pdev, BIT(0), DRV_NAME);
|
|
if (rc) {
|
|
SCSC_TAG_ERR_DEV(PCIE_MIF, pcie->dev,
|
|
"pcim_iomap_regions() failed. Aborting.\n");
|
|
return NULL;
|
|
}
|
|
|
|
|
|
pci_set_master(pdev);
|
|
|
|
/* Access iomap allocation table */
|
|
/* return __iomem * const * */
|
|
pcie->registers = pcim_iomap_table(pdev)[0];
|
|
|
|
/* Set up a single MSI interrupt */
|
|
if (pci_enable_msi(pdev)) {
|
|
SCSC_TAG_ERR_DEV(PCIE_MIF, pcie->dev,
|
|
"Failed to enable MSI interrupts. Aborting.\n");
|
|
return NULL;
|
|
}
|
|
rc = devm_request_irq(&pdev->dev, pdev->irq, pcie_mif_isr, 0,
|
|
DRV_NAME, pcie);
|
|
if (rc) {
|
|
SCSC_TAG_ERR_DEV(PCIE_MIF, pcie->dev,
|
|
"Failed to register MSI handler. Aborting.\n");
|
|
return NULL;
|
|
}
|
|
|
|
/* if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
|
|
* SCSC_TAG_INFO_DEV(PCIE_MIF, pcie->dev, "DMA mask 64bits.\n");
|
|
* pcie->dma_using_dac = 1; */
|
|
if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
|
|
SCSC_TAG_INFO_DEV(PCIE_MIF, pcie->dev, "DMA mask 32bits.\n");
|
|
pcie->dma_using_dac = 0;
|
|
} else {
|
|
SCSC_TAG_ERR_DEV(PCIE_MIF, pcie->dev, "Failed to set DMA mask. Aborting.\n");
|
|
return NULL;
|
|
}
|
|
|
|
pci_read_config_word(pdev, PCI_COMMAND, &cmd);
|
|
|
|
/* Make sure Mx is in the reset state */
|
|
pcie_mif_reset(pcie_if, true);
|
|
|
|
/* Create debug proc entry */
|
|
pcie_create_proc_dir(pcie);
|
|
|
|
return pcie_if;
|
|
}
|
|
|
|
void pcie_mif_destroy_pcie(struct pci_dev *pdev, struct scsc_mif_abs *interface)
|
|
{
|
|
/* Create debug proc entry */
|
|
pcie_remove_proc_dir();
|
|
|
|
pci_disable_device(pdev);
|
|
}
|
|
|
|
struct pci_dev *pcie_mif_get_pci_dev(struct scsc_mif_abs *interface)
|
|
{
|
|
struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
|
|
|
|
BUG_ON(!interface || !pcie);
|
|
|
|
return pcie->pdev;
|
|
}
|
|
|
|
struct device *pcie_mif_get_dev(struct scsc_mif_abs *interface)
|
|
{
|
|
struct pcie_mif *pcie = pcie_mif_from_mif_abs(interface);
|
|
|
|
BUG_ON(!interface || !pcie);
|
|
|
|
return pcie->dev;
|
|
}
|
|
|
|
|
|
|
|
/* Funtions for proc entry */
|
|
int pcie_mif_set_bar0_register(struct pcie_mif *pcie, unsigned int value, unsigned int offset)
|
|
{
|
|
iowrite32(value, pcie->registers + offset);
|
|
mmiowb();
|
|
|
|
return 0;
|
|
}
|
|
|
|
void pcie_mif_get_bar0(struct pcie_mif *pcie, struct scsc_bar0_reg *bar0)
|
|
{
|
|
bar0->NEWMSG = ioread32(pcie->registers + SCSC_PCIE_NEWMSG);
|
|
bar0->SIGNATURE = ioread32(pcie->registers + SCSC_PCIE_SIGNATURE);
|
|
bar0->OFFSET = ioread32(pcie->registers + SCSC_PCIE_OFFSET);
|
|
bar0->RUNEN = ioread32(pcie->registers + SCSC_PCIE_RUNEN);
|
|
bar0->DEBUG = ioread32(pcie->registers + SCSC_PCIE_DEBUG);
|
|
bar0->AXIWCNT = ioread32(pcie->registers + SCSC_PCIE_AXIWCNT);
|
|
bar0->AXIRCNT = ioread32(pcie->registers + SCSC_PCIE_AXIRCNT);
|
|
bar0->AXIWADDR = ioread32(pcie->registers + SCSC_PCIE_AXIWADDR);
|
|
bar0->AXIRADDR = ioread32(pcie->registers + SCSC_PCIE_AXIRADDR);
|
|
bar0->TBD = ioread32(pcie->registers + SCSC_PCIE_TBD);
|
|
bar0->AXICTRL = ioread32(pcie->registers + SCSC_PCIE_AXICTRL);
|
|
bar0->AXIDATA = ioread32(pcie->registers + SCSC_PCIE_AXIDATA);
|
|
bar0->AXIRDBP = ioread32(pcie->registers + SCSC_PCIE_AXIRDBP);
|
|
bar0->IFAXIWCNT = ioread32(pcie->registers + SCSC_PCIE_IFAXIWCNT);
|
|
bar0->IFAXIRCNT = ioread32(pcie->registers + SCSC_PCIE_IFAXIRCNT);
|
|
bar0->IFAXIWADDR = ioread32(pcie->registers + SCSC_PCIE_IFAXIWADDR);
|
|
bar0->IFAXIRADDR = ioread32(pcie->registers + SCSC_PCIE_IFAXIRADDR);
|
|
bar0->IFAXICTRL = ioread32(pcie->registers + SCSC_PCIE_IFAXICTRL);
|
|
bar0->GRST = ioread32(pcie->registers + SCSC_PCIE_GRST);
|
|
bar0->AMBA2TRANSAXIWCNT = ioread32(pcie->registers + SCSC_PCIE_AMBA2TRANSAXIWCNT);
|
|
bar0->AMBA2TRANSAXIRCNT = ioread32(pcie->registers + SCSC_PCIE_AMBA2TRANSAXIRCNT);
|
|
bar0->AMBA2TRANSAXIWADDR = ioread32(pcie->registers + SCSC_PCIE_AMBA2TRANSAXIWADDR);
|
|
bar0->AMBA2TRANSAXIRADDR = ioread32(pcie->registers + SCSC_PCIE_AMBA2TRANSAXIRADDR);
|
|
bar0->AMBA2TRANSAXICTR = ioread32(pcie->registers + SCSC_PCIE_AMBA2TRANSAXICTR);
|
|
bar0->TRANS2PCIEREADALIGNAXIWCNT = ioread32(pcie->registers + SCSC_PCIE_TRANS2PCIEREADALIGNAXIWCNT);
|
|
bar0->TRANS2PCIEREADALIGNAXIRCNT = ioread32(pcie->registers + SCSC_PCIE_TRANS2PCIEREADALIGNAXIRCNT);
|
|
bar0->TRANS2PCIEREADALIGNAXIWADDR = ioread32(pcie->registers + SCSC_PCIE_TRANS2PCIEREADALIGNAXIWADDR);
|
|
bar0->TRANS2PCIEREADALIGNAXIRADDR = ioread32(pcie->registers + SCSC_PCIE_TRANS2PCIEREADALIGNAXIRADDR);
|
|
bar0->TRANS2PCIEREADALIGNAXICTRL = ioread32(pcie->registers + SCSC_PCIE_TRANS2PCIEREADALIGNAXICTRL);
|
|
bar0->READROUNDTRIPMIN = ioread32(pcie->registers + SCSC_PCIE_READROUNDTRIPMIN);
|
|
bar0->READROUNDTRIPMAX = ioread32(pcie->registers + SCSC_PCIE_READROUNDTRIPMAX);
|
|
bar0->READROUNDTRIPLAST = ioread32(pcie->registers + SCSC_PCIE_READROUNDTRIPLAST);
|
|
bar0->CPTAW0 = ioread32(pcie->registers + SCSC_PCIE_CPTAW0);
|
|
bar0->CPTAW1 = ioread32(pcie->registers + SCSC_PCIE_CPTAW1);
|
|
bar0->CPTAR0 = ioread32(pcie->registers + SCSC_PCIE_CPTAR0);
|
|
bar0->CPTAR1 = ioread32(pcie->registers + SCSC_PCIE_CPTAR1);
|
|
bar0->CPTB0 = ioread32(pcie->registers + SCSC_PCIE_CPTB0);
|
|
bar0->CPTW0 = ioread32(pcie->registers + SCSC_PCIE_CPTW0);
|
|
bar0->CPTW1 = ioread32(pcie->registers + SCSC_PCIE_CPTW1);
|
|
bar0->CPTW2 = ioread32(pcie->registers + SCSC_PCIE_CPTW2);
|
|
bar0->CPTR0 = ioread32(pcie->registers + SCSC_PCIE_CPTR0);
|
|
bar0->CPTR1 = ioread32(pcie->registers + SCSC_PCIE_CPTR1);
|
|
bar0->CPTR2 = ioread32(pcie->registers + SCSC_PCIE_CPTR2);
|
|
bar0->CPTRES = ioread32(pcie->registers + SCSC_PCIE_CPTRES);
|
|
bar0->CPTAWDELAY = ioread32(pcie->registers + SCSC_PCIE_CPTAWDELAY);
|
|
bar0->CPTARDELAY = ioread32(pcie->registers + SCSC_PCIE_CPTARDELAY);
|
|
bar0->CPTSRTADDR = ioread32(pcie->registers + SCSC_PCIE_CPTSRTADDR);
|
|
bar0->CPTENDADDR = ioread32(pcie->registers + SCSC_PCIE_CPTENDADDR);
|
|
bar0->CPTSZLTHID = ioread32(pcie->registers + SCSC_PCIE_CPTSZLTHID);
|
|
bar0->CPTPHSEL = ioread32(pcie->registers + SCSC_PCIE_CPTPHSEL);
|
|
bar0->CPTRUN = ioread32(pcie->registers + SCSC_PCIE_CPTRUN);
|
|
bar0->FPGAVER = ioread32(pcie->registers + SCSC_PCIE_FPGAVER);
|
|
}
|