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			325 lines
		
	
	
	
		
			8.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			325 lines
		
	
	
	
		
			8.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright (c) 2008-2011 Atheros Communications Inc.
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|  *
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|  * Permission to use, copy, modify, and/or distribute this software for any
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|  * purpose with or without fee is hereby granted, provided that the above
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|  * copyright notice and this permission notice appear in all copies.
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|  *
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|  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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|  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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|  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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|  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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|  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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|  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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|  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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|  */
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| 
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| #ifndef DEBUG_H
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| #define DEBUG_H
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| 
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| #include "hw.h"
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| #include "dfs_debug.h"
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| 
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| struct ath_txq;
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| struct ath_buf;
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| struct fft_sample_tlv;
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| 
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| #ifdef CONFIG_ATH9K_DEBUGFS
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| #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
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| #define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
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| #define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
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| #define ANT_STAT_INC(i, c) sc->debug.stats.ant_stats[i].c++
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| #define ANT_LNA_INC(i, c) sc->debug.stats.ant_stats[i].lna_recv_cnt[c]++;
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| #else
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| #define TX_STAT_INC(q, c) do { } while (0)
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| #define RX_STAT_INC(c)
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| #define RESET_STAT_INC(sc, type) do { } while (0)
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| #define ANT_STAT_INC(i, c) do { } while (0)
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| #define ANT_LNA_INC(i, c) do { } while (0)
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| #endif
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| 
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| enum ath_reset_type {
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| 	RESET_TYPE_BB_HANG,
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| 	RESET_TYPE_BB_WATCHDOG,
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| 	RESET_TYPE_FATAL_INT,
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| 	RESET_TYPE_TX_ERROR,
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| 	RESET_TYPE_TX_GTT,
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| 	RESET_TYPE_TX_HANG,
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| 	RESET_TYPE_PLL_HANG,
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| 	RESET_TYPE_MAC_HANG,
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| 	RESET_TYPE_BEACON_STUCK,
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| 	RESET_TYPE_MCI,
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| 	__RESET_TYPE_MAX
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| };
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| 
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| #ifdef CONFIG_ATH9K_DEBUGFS
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| 
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| /**
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|  * struct ath_interrupt_stats - Contains statistics about interrupts
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|  * @total: Total no. of interrupts generated so far
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|  * @rxok: RX with no errors
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|  * @rxlp: RX with low priority RX
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|  * @rxhp: RX with high priority, uapsd only
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|  * @rxeol: RX with no more RXDESC available
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|  * @rxorn: RX FIFO overrun
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|  * @txok: TX completed at the requested rate
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|  * @txurn: TX FIFO underrun
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|  * @mib: MIB regs reaching its threshold
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|  * @rxphyerr: RX with phy errors
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|  * @rx_keycache_miss: RX with key cache misses
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|  * @swba: Software Beacon Alert
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|  * @bmiss: Beacon Miss
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|  * @bnr: Beacon Not Ready
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|  * @cst: Carrier Sense TImeout
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|  * @gtt: Global TX Timeout
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|  * @tim: RX beacon TIM occurrence
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|  * @cabend: RX End of CAB traffic
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|  * @dtimsync: DTIM sync lossage
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|  * @dtim: RX Beacon with DTIM
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|  * @bb_watchdog: Baseband watchdog
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|  * @tsfoor: TSF out of range, indicates that the corrected TSF received
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|  * from a beacon differs from the PCU's internal TSF by more than a
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|  * (programmable) threshold
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|  * @local_timeout: Internal bus timeout.
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|  * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
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|  * @gen_timer: Generic hardware timer interrupt
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|  */
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| struct ath_interrupt_stats {
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| 	u32 total;
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| 	u32 rxok;
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| 	u32 rxlp;
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| 	u32 rxhp;
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| 	u32 rxeol;
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| 	u32 rxorn;
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| 	u32 txok;
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| 	u32 txeol;
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| 	u32 txurn;
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| 	u32 mib;
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| 	u32 rxphyerr;
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| 	u32 rx_keycache_miss;
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| 	u32 swba;
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| 	u32 bmiss;
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| 	u32 bnr;
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| 	u32 cst;
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| 	u32 gtt;
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| 	u32 tim;
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| 	u32 cabend;
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| 	u32 dtimsync;
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| 	u32 dtim;
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| 	u32 bb_watchdog;
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| 	u32 tsfoor;
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| 	u32 mci;
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| 	u32 gen_timer;
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| 
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| 	/* Sync-cause stats */
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| 	u32 sync_cause_all;
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| 	u32 sync_rtc_irq;
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| 	u32 sync_mac_irq;
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| 	u32 eeprom_illegal_access;
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| 	u32 apb_timeout;
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| 	u32 pci_mode_conflict;
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| 	u32 host1_fatal;
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| 	u32 host1_perr;
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| 	u32 trcv_fifo_perr;
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| 	u32 radm_cpl_ep;
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| 	u32 radm_cpl_dllp_abort;
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| 	u32 radm_cpl_tlp_abort;
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| 	u32 radm_cpl_ecrc_err;
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| 	u32 radm_cpl_timeout;
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| 	u32 local_timeout;
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| 	u32 pm_access;
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| 	u32 mac_awake;
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| 	u32 mac_asleep;
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| 	u32 mac_sleep_access;
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| };
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| 
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| 
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| /**
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|  * struct ath_tx_stats - Statistics about TX
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|  * @tx_pkts_all:  No. of total frames transmitted, including ones that
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| 	may have had errors.
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|  * @tx_bytes_all:  No. of total bytes transmitted, including ones that
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| 	may have had errors.
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|  * @queued: Total MPDUs (non-aggr) queued
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|  * @completed: Total MPDUs (non-aggr) completed
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|  * @a_aggr: Total no. of aggregates queued
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|  * @a_queued_hw: Total AMPDUs queued to hardware
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|  * @a_queued_sw: Total AMPDUs queued to software queues
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|  * @a_completed: Total AMPDUs completed
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|  * @a_retries: No. of AMPDUs retried (SW)
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|  * @a_xretries: No. of AMPDUs dropped due to xretries
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|  * @txerr_filtered: No. of frames with TXERR_FILT flag set.
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|  * @fifo_underrun: FIFO underrun occurrences
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| 	Valid only for:
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| 		- non-aggregate condition.
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| 		- first packet of aggregate.
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|  * @xtxop: No. of frames filtered because of TXOP limit
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|  * @timer_exp: Transmit timer expiry
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|  * @desc_cfg_err: Descriptor configuration errors
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|  * @data_urn: TX data underrun errors
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|  * @delim_urn: TX delimiter underrun errors
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|  * @puttxbuf: Number of times hardware was given txbuf to write.
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|  * @txstart:  Number of times hardware was told to start tx.
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|  * @txprocdesc:  Number of times tx descriptor was processed
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|  * @txfailed:  Out-of-memory or other errors in xmit path.
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|  */
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| struct ath_tx_stats {
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| 	u32 tx_pkts_all;
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| 	u32 tx_bytes_all;
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| 	u32 queued;
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| 	u32 completed;
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| 	u32 xretries;
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| 	u32 a_aggr;
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| 	u32 a_queued_hw;
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| 	u32 a_queued_sw;
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| 	u32 a_completed;
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| 	u32 a_retries;
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| 	u32 a_xretries;
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| 	u32 txerr_filtered;
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| 	u32 fifo_underrun;
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| 	u32 xtxop;
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| 	u32 timer_exp;
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| 	u32 desc_cfg_err;
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| 	u32 data_underrun;
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| 	u32 delim_underrun;
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| 	u32 puttxbuf;
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| 	u32 txstart;
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| 	u32 txprocdesc;
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| 	u32 txfailed;
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| };
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| 
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| /*
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|  * Various utility macros to print TX/Queue counters.
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|  */
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| #define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
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| #define TXSTATS sc->debug.stats.txstats
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| #define PR(str, elem)							\
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| 	do {								\
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| 		len += scnprintf(buf + len, size - len,			\
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| 				 "%s%13u%11u%10u%10u\n", str,		\
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| 				 TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem,\
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| 				 TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem,\
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| 				 TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem,\
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| 				 TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \
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| 	} while(0)
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| 
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| struct ath_rx_rate_stats {
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| 	struct {
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| 		u32 ht20_cnt;
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| 		u32 ht40_cnt;
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| 		u32 sgi_cnt;
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| 		u32 lgi_cnt;
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| 	} ht_stats[24];
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| 
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| 	struct {
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| 		u32 ofdm_cnt;
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| 	} ofdm_stats[8];
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| 
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| 	struct {
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| 		u32 cck_lp_cnt;
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| 		u32 cck_sp_cnt;
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| 	} cck_stats[4];
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| };
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| 
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| #define ANT_MAIN 0
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| #define ANT_ALT  1
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| 
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| struct ath_antenna_stats {
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| 	u32 recv_cnt;
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| 	u32 rssi_avg;
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| 	u32 lna_recv_cnt[4];
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| 	u32 lna_attempt_cnt[4];
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| };
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| 
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| struct ath_stats {
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| 	struct ath_interrupt_stats istats;
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| 	struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
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| 	struct ath_rx_stats rxstats;
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| 	struct ath_dfs_stats dfs_stats;
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| 	struct ath_antenna_stats ant_stats[2];
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| 	u32 reset[__RESET_TYPE_MAX];
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| };
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| 
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| struct ath9k_debug {
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| 	struct dentry *debugfs_phy;
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| 	u32 regidx;
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| 	struct ath_stats stats;
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| };
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| 
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| int ath9k_init_debug(struct ath_hw *ah);
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| void ath9k_deinit_debug(struct ath_softc *sc);
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| 
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| void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
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| void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
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| 		       struct ath_tx_status *ts, struct ath_txq *txq,
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| 		       unsigned int flags);
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| void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
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| int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
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| 			    struct ieee80211_vif *vif, int sset);
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| void ath9k_get_et_stats(struct ieee80211_hw *hw,
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| 			struct ieee80211_vif *vif,
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| 			struct ethtool_stats *stats, u64 *data);
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| void ath9k_get_et_strings(struct ieee80211_hw *hw,
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| 			  struct ieee80211_vif *vif,
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| 			  u32 sset, u8 *data);
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| void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,
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| 			   struct ieee80211_vif *vif,
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| 			   struct ieee80211_sta *sta,
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| 			   struct dentry *dir);
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| void ath9k_debug_stat_ant(struct ath_softc *sc,
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| 			  struct ath_hw_antcomb_conf *div_ant_conf,
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| 			  int main_rssi_avg, int alt_rssi_avg);
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| void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause);
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| 
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| #else
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| 
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| static inline int ath9k_init_debug(struct ath_hw *ah)
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| {
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| 	return 0;
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| }
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| 
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| static inline void ath9k_deinit_debug(struct ath_softc *sc)
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| {
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| }
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| static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
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| 					    enum ath9k_int status)
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| {
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| }
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| static inline void ath_debug_stat_tx(struct ath_softc *sc,
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| 				     struct ath_buf *bf,
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| 				     struct ath_tx_status *ts,
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| 				     struct ath_txq *txq,
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| 				     unsigned int flags)
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| {
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| }
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| static inline void ath_debug_stat_rx(struct ath_softc *sc,
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| 				     struct ath_rx_status *rs)
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| {
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| }
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| static inline void ath9k_debug_stat_ant(struct ath_softc *sc,
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| 					struct ath_hw_antcomb_conf *div_ant_conf,
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| 					int main_rssi_avg, int alt_rssi_avg)
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| {
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| 
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| }
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| 
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| static inline void
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| ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
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| {
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| }
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| 
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| #endif /* CONFIG_ATH9K_DEBUGFS */
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| 
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| #ifdef CONFIG_ATH9K_STATION_STATISTICS
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| void ath_debug_rate_stats(struct ath_softc *sc,
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| 			  struct ath_rx_status *rs,
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| 			  struct sk_buff *skb);
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| #else
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| static inline void ath_debug_rate_stats(struct ath_softc *sc,
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| 					struct ath_rx_status *rs,
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| 					struct sk_buff *skb)
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| {
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| }
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| #endif /* CONFIG_ATH9K_STATION_STATISTICS */
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| 
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| #endif /* DEBUG_H */
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