mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
296 lines
8.1 KiB
C
296 lines
8.1 KiB
C
/*
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* Copyright (c) 2010 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _SBCHIPC_H
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#define _SBCHIPC_H
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#include "defs.h" /* for PAD macro */
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#define CHIPCREGOFFS(field) offsetof(struct chipcregs, field)
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struct chipcregs {
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u32 chipid; /* 0x0 */
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u32 capabilities;
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u32 corecontrol; /* corerev >= 1 */
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u32 bist;
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/* OTP */
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u32 otpstatus; /* 0x10, corerev >= 10 */
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u32 otpcontrol;
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u32 otpprog;
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u32 otplayout; /* corerev >= 23 */
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/* Interrupt control */
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u32 intstatus; /* 0x20 */
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u32 intmask;
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/* Chip specific regs */
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u32 chipcontrol; /* 0x28, rev >= 11 */
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u32 chipstatus; /* 0x2c, rev >= 11 */
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/* Jtag Master */
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u32 jtagcmd; /* 0x30, rev >= 10 */
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u32 jtagir;
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u32 jtagdr;
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u32 jtagctrl;
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/* serial flash interface registers */
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u32 flashcontrol; /* 0x40 */
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u32 flashaddress;
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u32 flashdata;
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u32 PAD[1];
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/* Silicon backplane configuration broadcast control */
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u32 broadcastaddress; /* 0x50 */
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u32 broadcastdata;
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/* gpio - cleared only by power-on-reset */
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u32 gpiopullup; /* 0x58, corerev >= 20 */
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u32 gpiopulldown; /* 0x5c, corerev >= 20 */
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u32 gpioin; /* 0x60 */
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u32 gpioout; /* 0x64 */
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u32 gpioouten; /* 0x68 */
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u32 gpiocontrol; /* 0x6C */
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u32 gpiointpolarity; /* 0x70 */
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u32 gpiointmask; /* 0x74 */
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/* GPIO events corerev >= 11 */
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u32 gpioevent;
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u32 gpioeventintmask;
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/* Watchdog timer */
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u32 watchdog; /* 0x80 */
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/* GPIO events corerev >= 11 */
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u32 gpioeventintpolarity;
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/* GPIO based LED powersave registers corerev >= 16 */
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u32 gpiotimerval; /* 0x88 */
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u32 gpiotimeroutmask;
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/* clock control */
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u32 clockcontrol_n; /* 0x90 */
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u32 clockcontrol_sb; /* aka m0 */
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u32 clockcontrol_pci; /* aka m1 */
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u32 clockcontrol_m2; /* mii/uart/mipsref */
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u32 clockcontrol_m3; /* cpu */
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u32 clkdiv; /* corerev >= 3 */
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u32 gpiodebugsel; /* corerev >= 28 */
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u32 capabilities_ext; /* 0xac */
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/* pll delay registers (corerev >= 4) */
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u32 pll_on_delay; /* 0xb0 */
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u32 fref_sel_delay;
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u32 slow_clk_ctl; /* 5 < corerev < 10 */
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u32 PAD;
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/* Instaclock registers (corerev >= 10) */
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u32 system_clk_ctl; /* 0xc0 */
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u32 clkstatestretch;
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u32 PAD[2];
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/* Indirect backplane access (corerev >= 22) */
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u32 bp_addrlow; /* 0xd0 */
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u32 bp_addrhigh;
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u32 bp_data;
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u32 PAD;
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u32 bp_indaccess;
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u32 PAD[3];
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/* More clock dividers (corerev >= 32) */
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u32 clkdiv2;
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u32 PAD[2];
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/* In AI chips, pointer to erom */
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u32 eromptr; /* 0xfc */
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/* ExtBus control registers (corerev >= 3) */
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u32 pcmcia_config; /* 0x100 */
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u32 pcmcia_memwait;
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u32 pcmcia_attrwait;
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u32 pcmcia_iowait;
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u32 ide_config;
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u32 ide_memwait;
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u32 ide_attrwait;
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u32 ide_iowait;
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u32 prog_config;
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u32 prog_waitcount;
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u32 flash_config;
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u32 flash_waitcount;
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u32 SECI_config; /* 0x130 SECI configuration */
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u32 PAD[3];
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/* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */
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u32 eci_output; /* 0x140 */
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u32 eci_control;
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u32 eci_inputlo;
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u32 eci_inputmi;
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u32 eci_inputhi;
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u32 eci_inputintpolaritylo;
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u32 eci_inputintpolaritymi;
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u32 eci_inputintpolarityhi;
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u32 eci_intmasklo;
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u32 eci_intmaskmi;
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u32 eci_intmaskhi;
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u32 eci_eventlo;
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u32 eci_eventmi;
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u32 eci_eventhi;
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u32 eci_eventmasklo;
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u32 eci_eventmaskmi;
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u32 eci_eventmaskhi;
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u32 PAD[3];
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/* SROM interface (corerev >= 32) */
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u32 sromcontrol; /* 0x190 */
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u32 sromaddress;
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u32 sromdata;
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u32 PAD[17];
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/* Clock control and hardware workarounds (corerev >= 20) */
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u32 clk_ctl_st; /* 0x1e0 */
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u32 hw_war;
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u32 PAD[70];
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/* UARTs */
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u8 uart0data; /* 0x300 */
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u8 uart0imr;
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u8 uart0fcr;
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u8 uart0lcr;
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u8 uart0mcr;
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u8 uart0lsr;
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u8 uart0msr;
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u8 uart0scratch;
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u8 PAD[248]; /* corerev >= 1 */
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u8 uart1data; /* 0x400 */
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u8 uart1imr;
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u8 uart1fcr;
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u8 uart1lcr;
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u8 uart1mcr;
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u8 uart1lsr;
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u8 uart1msr;
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u8 uart1scratch;
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u32 PAD[126];
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/* PMU registers (corerev >= 20) */
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u32 pmucontrol; /* 0x600 */
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u32 pmucapabilities;
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u32 pmustatus;
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u32 res_state;
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u32 res_pending;
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u32 pmutimer;
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u32 min_res_mask;
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u32 max_res_mask;
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u32 res_table_sel;
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u32 res_dep_mask;
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u32 res_updn_timer;
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u32 res_timer;
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u32 clkstretch;
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u32 pmuwatchdog;
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u32 gpiosel; /* 0x638, rev >= 1 */
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u32 gpioenable; /* 0x63c, rev >= 1 */
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u32 res_req_timer_sel;
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u32 res_req_timer;
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u32 res_req_mask;
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u32 pmucapabilities_ext; /* 0x64c, pmurev >=15 */
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u32 chipcontrol_addr; /* 0x650 */
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u32 chipcontrol_data; /* 0x654 */
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u32 regcontrol_addr;
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u32 regcontrol_data;
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u32 pllcontrol_addr;
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u32 pllcontrol_data;
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u32 pmustrapopt; /* 0x668, corerev >= 28 */
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u32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
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u32 retention_ctl; /* 0x670, pmurev >= 15 */
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u32 PAD[3];
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u32 retention_grpidx; /* 0x680 */
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u32 retention_grpctl; /* 0x684 */
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u32 PAD[94];
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u16 sromotp[768];
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};
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/* chipid */
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#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
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#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
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#define CID_REV_SHIFT 16 /* Chip Revision shift */
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#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
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#define CID_PKG_SHIFT 20 /* Package Option shift */
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#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
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#define CID_CC_SHIFT 24
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#define CID_TYPE_MASK 0xf0000000 /* Chip Type */
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#define CID_TYPE_SHIFT 28
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/* capabilities */
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#define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */
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#define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
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#define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
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/* UARTs are driven by internal divided clock */
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#define CC_CAP_UINTCLK 0x00000008
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#define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
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#define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
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#define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
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#define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
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#define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
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#define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */
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#define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */
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#define CC_CAP_PWR_CTL 0x00040000 /* Power control */
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#define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
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#define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
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#define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */
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#define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */
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#define CC_CAP_ROM 0x00800000 /* Internal boot rom active */
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#define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
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#define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
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#define CC_CAP_SROM 0x40000000 /* Srom Present, rev >= 32 */
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/* Nand flash present, rev >= 35 */
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#define CC_CAP_NFLASH 0x80000000
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#define CC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */
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/* GSIO (spi/i2c) present, rev >= 37 */
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#define CC_CAP2_GSIO 0x00000002
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/* pmucapabilities */
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#define PCAP_REV_MASK 0x000000ff
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#define PCAP_RC_MASK 0x00001f00
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#define PCAP_RC_SHIFT 8
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#define PCAP_TC_MASK 0x0001e000
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#define PCAP_TC_SHIFT 13
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#define PCAP_PC_MASK 0x001e0000
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#define PCAP_PC_SHIFT 17
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#define PCAP_VC_MASK 0x01e00000
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#define PCAP_VC_SHIFT 21
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#define PCAP_CC_MASK 0x1e000000
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#define PCAP_CC_SHIFT 25
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#define PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */
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#define PCAP5_PC_SHIFT 17
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#define PCAP5_VC_MASK 0x07c00000
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#define PCAP5_VC_SHIFT 22
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#define PCAP5_CC_MASK 0xf8000000
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#define PCAP5_CC_SHIFT 27
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/* pmucapabilites_ext PMU rev >= 15 */
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#define PCAPEXT_SR_SUPPORTED_MASK (1 << 1)
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/* retention_ctl PMU rev >= 15 */
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#define PMU_RCTL_MACPHY_DISABLE_MASK (1 << 26)
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#define PMU_RCTL_LOGIC_DISABLE_MASK (1 << 27)
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/*
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* Maximum delay for the PMU state transition in us.
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* This is an upper bound intended for spinwaits etc.
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*/
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#define PMU_MAX_TRANSITION_DLY 15000
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#endif /* _SBCHIPC_H */
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