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20 lines
683 B
C
20 lines
683 B
C
/*
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* Device Tree binding constants for Exynos8890 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_8890_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_8890_H
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#define CLK_SYSMMU_BASE 1100
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#define CLK_VCLK_SYSMMU_MFC (CLK_SYSMMU_BASE + 0)
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#define CLK_VCLK_SYSMMU_MSCL (CLK_SYSMMU_BASE + 1)
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#define CLK_VCLK_SYSMMU_ISP0 (CLK_SYSMMU_BASE + 2)
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#define CLK_VCLK_SYSMMU_CAM0 (CLK_SYSMMU_BASE + 3)
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#define CLK_VCLK_SYSMMU_CAM1 (CLK_SYSMMU_BASE + 4)
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#define CLK_VCLK_SYSMMU_AUD (CLK_SYSMMU_BASE + 5)
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#define CLK_VCLK_SYSMMU_DISP0 (CLK_SYSMMU_BASE + 6)
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#define CLK_VCLK_SYSMMU_DISP1 (CLK_SYSMMU_BASE + 7)
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#define CLK_GATE_SMFC 51
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_8890_H */
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