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			52 lines
		
	
	
	
		
			1.4 KiB
		
	
	
	
		
			Text
		
	
	
	
	
	
			
		
		
	
	
			52 lines
		
	
	
	
		
			1.4 KiB
		
	
	
	
		
			Text
		
	
	
	
	
	
| Qualcomm adreno/snapdragon GPU
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| 
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| Required properties:
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| - compatible: "qcom,adreno-3xx"
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| - reg: Physical base address and length of the controller's registers.
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| - interrupts: The interrupt signal from the gpu.
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| - clocks: device clocks
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|   See ../clocks/clock-bindings.txt for details.
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| - clock-names: the following clocks are required:
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|   * "core_clk"
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|   * "iface_clk"
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|   * "mem_iface_clk"
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| - qcom,chipid: gpu chip-id.  Note this may become optional for future
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|   devices if we can reliably read the chipid from hw
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| - qcom,gpu-pwrlevels: list of operating points
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|   - compatible: "qcom,gpu-pwrlevels"
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|   - for each qcom,gpu-pwrlevel:
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|     - qcom,gpu-freq: requested gpu clock speed
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|     - NOTE: downstream android driver defines additional parameters to
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|       configure memory bandwidth scaling per OPP.
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| 
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| Example:
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| 
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| / {
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| 	...
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| 
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| 	gpu: qcom,kgsl-3d0@4300000 {
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| 		compatible = "qcom,adreno-3xx";
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| 		reg = <0x04300000 0x20000>;
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| 		reg-names = "kgsl_3d0_reg_memory";
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| 		interrupts = <GIC_SPI 80 0>;
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| 		interrupt-names = "kgsl_3d0_irq";
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| 		clock-names =
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| 		    "core_clk",
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| 		    "iface_clk",
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| 		    "mem_iface_clk";
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| 		clocks =
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| 		    <&mmcc GFX3D_CLK>,
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| 		    <&mmcc GFX3D_AHB_CLK>,
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| 		    <&mmcc MMSS_IMEM_AHB_CLK>;
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| 		qcom,chipid = <0x03020100>;
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| 		qcom,gpu-pwrlevels {
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| 			compatible = "qcom,gpu-pwrlevels";
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| 			qcom,gpu-pwrlevel@0 {
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| 				qcom,gpu-freq = <450000000>;
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| 			};
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| 			qcom,gpu-pwrlevel@1 {
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| 				qcom,gpu-freq = <27000000>;
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| 			};
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| 		};
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| 	};
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| };
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