mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
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118 lines
3.1 KiB
C
118 lines
3.1 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Rajeshwar Ranga: Interrupt Distribution Unit API's
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*/
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#ifndef __PLAT_ARCFPGA_SMP_H
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#define __PLAT_ARCFPGA_SMP_H
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#ifdef CONFIG_SMP
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#include <linux/types.h>
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#include <asm/arcregs.h>
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#define ARC_AUX_IDU_REG_CMD 0x2000
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#define ARC_AUX_IDU_REG_PARAM 0x2001
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#define ARC_AUX_XTL_REG_CMD 0x2002
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#define ARC_AUX_XTL_REG_PARAM 0x2003
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#define ARC_REG_MP_BCR 0x2021
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#define ARC_XTL_CMD_WRITE_PC 0x04
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#define ARC_XTL_CMD_CLEAR_HALT 0x02
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/*
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* Build Configuration Register which identifies the sub-components
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*/
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struct bcr_mp {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int mp_arch:16, pad:5, sdu:1, idu:1, scu:1, ver:8;
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#else
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unsigned int ver:8, scu:1, idu:1, sdu:1, pad:5, mp_arch:16;
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#endif
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};
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/* IDU supports 256 common interrupts */
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#define NR_IDU_IRQS 256
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/*
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* The Aux Regs layout is same bit-by-bit in both BE/LE modes.
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* However when casted as a bitfield encoded "C" struct, gcc treats it as
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* memory, generating different code for BE/LE, requiring strcture adj (see
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* include/asm/arcregs.h)
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*
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* However when manually "carving" the value for a Aux, no special handling
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* of BE is needed because of the property discribed above
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*/
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#define IDU_SET_COMMAND(irq, cmd) \
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do { \
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uint32_t __val; \
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__val = (((irq & 0xFF) << 8) | (cmd & 0xFF)); \
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write_aux_reg(ARC_AUX_IDU_REG_CMD, __val); \
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} while (0)
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#define IDU_SET_PARAM(par) write_aux_reg(ARC_AUX_IDU_REG_PARAM, par)
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#define IDU_GET_PARAM() read_aux_reg(ARC_AUX_IDU_REG_PARAM)
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/* IDU Commands */
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#define IDU_DISABLE 0x00
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#define IDU_ENABLE 0x01
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#define IDU_IRQ_CLEAR 0x02
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#define IDU_IRQ_ASSERT 0x03
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#define IDU_IRQ_WMODE 0x04
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#define IDU_IRQ_STATUS 0x05
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#define IDU_IRQ_ACK 0x06
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#define IDU_IRQ_PEND 0x07
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#define IDU_IRQ_RMODE 0x08
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#define IDU_IRQ_WBITMASK 0x09
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#define IDU_IRQ_RBITMASK 0x0A
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#define idu_enable() IDU_SET_COMMAND(0, IDU_ENABLE)
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#define idu_disable() IDU_SET_COMMAND(0, IDU_DISABLE)
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#define idu_irq_assert(irq) IDU_SET_COMMAND((irq), IDU_IRQ_ASSERT)
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#define idu_irq_clear(irq) IDU_SET_COMMAND((irq), IDU_IRQ_CLEAR)
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/* IDU Interrupt Mode - Destination Encoding */
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#define IDU_IRQ_MOD_DISABLE 0x00
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#define IDU_IRQ_MOD_ROUND_RECP 0x01
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#define IDU_IRQ_MOD_TCPU_FIRSTRECP 0x02
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#define IDU_IRQ_MOD_TCPU_ALLRECP 0x03
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/* IDU Interrupt Mode - Triggering Mode */
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#define IDU_IRQ_MODE_LEVEL_TRIG 0x00
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#define IDU_IRQ_MODE_PULSE_TRIG 0x01
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#define IDU_IRQ_MODE_PARAM(dest_mode, trig_mode) \
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(((trig_mode & 0x01) << 15) | (dest_mode & 0xFF))
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struct idu_irq_config {
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uint8_t irq;
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uint8_t dest_mode;
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uint8_t trig_mode;
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};
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struct idu_irq_status {
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uint8_t irq;
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bool enabled;
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bool status;
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bool ack;
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bool pend;
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uint8_t next_rr;
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};
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extern void idu_irq_set_tgtcpu(uint8_t irq, uint32_t mask);
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extern void idu_irq_set_mode(uint8_t irq, uint8_t dest_mode, uint8_t trig_mode);
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extern void iss_model_init_smp(unsigned int cpu);
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extern void iss_model_init_early_smp(void);
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#endif /* CONFIG_SMP */
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#endif
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