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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
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133 lines
3.7 KiB
C
133 lines
3.7 KiB
C
#ifndef _ASM_IA64_PCI_H
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#define _ASM_IA64_PCI_H
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <asm/io.h>
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#include <asm/scatterlist.h>
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#include <asm/hw_irq.h>
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struct pci_vector_struct {
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__u16 segment; /* PCI Segment number */
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__u16 bus; /* PCI Bus number */
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__u32 pci_id; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
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__u8 pin; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
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__u32 irq; /* IRQ assigned */
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};
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/*
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* Can be used to override the logic in pci_scan_bus for skipping already-configured bus
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* numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
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* loader.
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*/
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#define pcibios_assign_all_busses() 0
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#define PCIBIOS_MIN_IO 0x1000
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#define PCIBIOS_MIN_MEM 0x10000000
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void pcibios_config_init(void);
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struct pci_dev;
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/*
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* PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct
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* correspondence between device bus addresses and CPU physical addresses.
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* Platforms with a hardware I/O MMU _must_ turn this off to suppress the
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* bounce buffer handling code in the block and network device layers.
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* Platforms with separate bus address spaces _must_ turn this off and provide
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* a device DMA mapping implementation that takes care of the necessary
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* address translation.
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*
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* For now, the ia64 platforms which may have separate/multiple bus address
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* spaces all have I/O MMUs which support the merging of physically
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* discontiguous buffers, so we can use that as the sole factor to determine
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* the setting of PCI_DMA_BUS_IS_PHYS.
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*/
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extern unsigned long ia64_max_iommu_merge_mask;
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#define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL)
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#include <asm-generic/pci-dma-compat.h>
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#ifdef CONFIG_PCI
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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{
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unsigned long cacheline_size;
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u8 byte;
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
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if (byte == 0)
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cacheline_size = 1024;
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else
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cacheline_size = (int) byte * 4;
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*strat = PCI_DMA_BURST_MULTIPLE;
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*strategy_parameter = cacheline_size;
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}
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#endif
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#define HAVE_PCI_MMAP
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extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine);
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#define HAVE_PCI_LEGACY
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extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
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struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state);
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#define pci_get_legacy_mem platform_pci_get_legacy_mem
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#define pci_legacy_read platform_pci_legacy_read
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#define pci_legacy_write platform_pci_legacy_write
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struct iospace_resource {
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struct list_head list;
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struct resource res;
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};
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struct pci_controller {
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struct acpi_device *companion;
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void *iommu;
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int segment;
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int node; /* nearest node with memory or NUMA_NO_NODE for global allocation */
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void *platform_data;
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};
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#define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
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#define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment)
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extern struct pci_ops pci_root_ops;
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static inline int pci_proc_domain(struct pci_bus *bus)
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{
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return (pci_domain_nr(bus) != 0);
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}
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static inline struct resource *
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pcibios_select_root(struct pci_dev *pdev, struct resource *res)
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{
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struct resource *root = NULL;
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if (res->flags & IORESOURCE_IO)
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root = &ioport_resource;
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if (res->flags & IORESOURCE_MEM)
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root = &iomem_resource;
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return root;
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}
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#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
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static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
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{
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return channel ? isa_irq_to_vector(15) : isa_irq_to_vector(14);
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}
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#ifdef CONFIG_INTEL_IOMMU
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extern void pci_iommu_alloc(void);
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#endif
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#endif /* _ASM_IA64_PCI_H */
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