mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-07 16:58:04 -04:00
139 lines
4 KiB
C
139 lines
4 KiB
C
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __PCIE_EXYNOS_H
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#define __PCIE_EXYNOS_H
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#define MAX_TIMEOUT 2000
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#define ID_MASK 0xffff
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#define MAX_RC_NUM 2
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#if defined(CONFIG_SOC_EXYNOS8890)
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#define PCI_DEVICE_ID_EXYNOS 0xa544
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#define GPIO_DEBUG_SFR 0x15601068
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#else
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#define PCI_DEVICE_ID_EXYNOS 0xecec
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#define GPIO_DEBUG_SFR 0x0
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#endif
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#define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp)
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#define PCIE_BUS_PRIV_DATA(pdev) \
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((struct pcie_port *)pdev->bus->sysdata)
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struct exynos_pcie_clks {
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struct clk *pcie_clks[10];
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struct clk *phy_clks[3];
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};
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enum exynos_pcie_state {
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STATE_LINK_DOWN = 0,
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STATE_LINK_UP_TRY,
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STATE_LINK_DOWN_TRY,
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STATE_LINK_UP,
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};
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struct exynos_pcie {
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void __iomem *elbi_base;
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void __iomem *phy_base;
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void __iomem *block_base;
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void __iomem *rc_dbi_base;
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void __iomem *phy_pcs_base;
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struct regmap *pmureg;
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int perst_gpio;
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int ch_num;
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int pcie_clk_num;
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int phy_clk_num;
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enum exynos_pcie_state state;
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int probe_ok;
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int l1ss_enable;
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int linkdown_cnt;
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int idle_ip_index;
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bool use_msi;
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bool pcie_changed;
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struct workqueue_struct *pcie_wq;
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struct exynos_pcie_clks clks;
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struct pcie_port pp;
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struct pci_dev *pci_dev;
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struct pci_saved_state *pci_saved_configs;
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struct notifier_block lpa_nb;
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struct delayed_work work;
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struct exynos_pcie_register_event *event_reg;
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#ifdef CONFIG_PCI_EXYNOS_TEST
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int wlan_gpio;
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int bt_gpio;
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#endif
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#ifdef CONFIG_PM_DEVFREQ
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unsigned int int_min_lock;
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#endif
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};
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/* PCIe ELBI registers */
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#define PCIE_IRQ_PULSE 0x000
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#define IRQ_INTA_ASSERT (0x1 << 0)
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#define IRQ_INTB_ASSERT (0x1 << 2)
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#define IRQ_INTC_ASSERT (0x1 << 4)
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#define IRQ_INTD_ASSERT (0x1 << 6)
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#define IRQ_RADM_PM_TO_ACK (0x1 << 18)
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#define IRQ_L1_EXIT (0x1 << 24)
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#define PCIE_IRQ_LEVEL 0x004
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#define IRQ_MSI_CTRL (0x1 << 1)
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#define PCIE_IRQ_SPECIAL 0x008
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#define PCIE_IRQ_EN_PULSE 0x00c
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#define PCIE_IRQ_EN_LEVEL 0x010
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#define IRQ_MSI_ENABLE (0x1 << 1)
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#define IRQ_LINK_DOWN (0x1 << 30)
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#define IRQ_LINKDOWN_ENABLE (0x1 << 30)
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#define PCIE_IRQ_EN_SPECIAL 0x014
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#define PCIE_SW_WAKE 0x018
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#define PCIE_IRQ_LEVEL_FOR_READ 0x020
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#define L1_2_IDLE_STATE (0x1 << 23)
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#define PCIE_APP_LTSSM_ENABLE 0x02c
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#define PCIE_L1_BUG_FIX_ENABLE 0x038
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#define PCIE_APP_REQ_EXIT_L1 0x040
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#define PCIE_CXPL_DEBUG_INFO_H 0x070
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#define PCIE_ELBI_RDLH_LINKUP 0x074
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#define PCIE_ELBI_LTSSM_DISABLE 0x0
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#define PCIE_ELBI_LTSSM_ENABLE 0x1
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#define PCIE_PM_DSTATE 0x88
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#define PCIE_D0_UNINIT_STATE 0x4
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#define PCIE_APP_REQ_EXIT_L1_MODE 0xF4
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#define APP_REQ_EXIT_L1_MODE 0x1
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#define L1_REQ_NAK_CONTROL (0x3 << 4)
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#define PCIE_HISTORY_REG(x) (0x138 + ((x) * 0x4))
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#define LTSSM_STATE(x) (((x) >> 16) & 0x3f)
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#define PM_DSTATE(x) (((x) >> 8) & 0x7)
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#define L1SUB_STATE(x) (((x) >> 0) & 0x7)
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#define PCIE_LINKDOWN_RST_CTRL_SEL 0x1B8
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#define PCIE_LINKDOWN_RST_MANUAL (0x1 << 1)
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#define PCIE_LINKDOWN_RST_FSM (0x1 << 0)
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#define PCIE_SOFT_AUXCLK_SEL_CTRL 0x1C4
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#define CORE_CLK_GATING (0x1 << 0)
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#define PCIE_SOFT_CORE_RESET 0x1D0
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#define PCIE_STATE_HISTORY_CHECK 0x274
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#define HISTORY_BUFFER_ENABLE (0x1 << 0)
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#define HISTORY_BUFFER_CLEAR (0x1 << 1)
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#define PCIE_QCH_SEL 0x2C8
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#define CLOCK_GATING_IN_L12 0x1
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#define CLOCK_NOT_GATING 0x3
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#define CLOCK_GATING_MASK 0x3
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#define PCIE_DMA_MONITOR1 0x2CC
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#define PCIE_DMA_MONITOR2 0x2D0
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#define PCIE_DMA_MONITOR3 0x2D4
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#define FSYS1_MON_SEL_MASK 0xf
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#define PCIE_MON_SEL_MASK 0xff
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/* PCIe PMU registers */
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#define PCIE_PHY_CONTROL 0x071C
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#define PCIE_PHY_CONTROL_MASK 0x1
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#endif
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