mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-01 08:38:52 +01:00
1086 lines
51 KiB
C
1086 lines
51 KiB
C
#ifndef __EXYNOS7870_CMU_H__
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#define __EXYNOS7870_CMU_H__
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#include "../pwrcal-clk.h"
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enum clk_id {
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OSCCLK = fixed_rate_type,
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OSCCLK_26M,
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CLKPHY_FSYS_USB20DRD_PHYCLOCK,
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CLKPHY_FSYS_UFS_TX0_SYMBOL,
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CLKPHY_FSYS_UFS_RX0_SYMBOL,
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CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS,
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CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0,
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CLKIO_DISPAUD_AUDIOCDCLK0,
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CLKIO_DISPAUD_MIXER_SCLK_AP,
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CLKIO_DISPAUD_MIXER_BCLK_BT,
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CLKIO_DISPAUD_MIXER_BCLK_CP,
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CLKIO_DISPAUD_MIXER_BCLK_FM,
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CLKPHY_ISP_S_RXBYTECLKHS0_S4,
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CLKPHY_ISP_S_RXBYTECLKHS0_S4S,
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FIN_TEMP,
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FR_END,
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NUM_OF_FIXED_RATE_TYPE = FR_END - fixed_rate_type,
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MIF_FF_MUX_MEM_PLL_DIV2 = fixed_factor_type,
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MIF_FF_MUX_MEDIA_PLL_DIV2,
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MIF_FF_MUX_BUS_PLL_DIV2,
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FF_END,
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NUM_OF_FIXED_FACTOR_TYPE = FF_END - fixed_factor_type,
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CPUCL0_PLL = pll_type,
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CPUCL1_PLL,
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MEM_PLL,
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BUS_PLL,
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MEDIA_PLL,
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G3D_PLL,
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USB_PLL,
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ISP_PLL,
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DISP_PLL,
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AUD_PLL,
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PLL_END,
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NUM_OF_PLL_TYPE = PLL_END - pll_type,
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CPUCL0_MUX_CPUCL0_PLL = mux_type,
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CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
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CPUCL0_MUX_CLK_CPUCL0,
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CPUCL1_MUX_CPUCL1_PLL,
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CPUCL1_MUX_CLKCMU_CPUCL1_SWITCH_USER,
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CPUCL1_MUX_CLK_CPUCL1,
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DISPAUD_MUX_DISP_PLL,
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DISPAUD_MUX_AUD_PLL,
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DISPAUD_MUX_CLK_DISPAUD_DECON_INT_VCLK,
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DISPAUD_MUX_CLK_DISPAUD_DECON_INT_ECLK,
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DISPAUD_MUX_CLK_DISPAUD_MI2S,
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FSYS_MUX_USB_PLL,
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G3D_MUX_G3D_PLL,
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G3D_MUX_CLKCMU_G3D_SWITCH_USER,
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G3D_MUX_CLK_G3D,
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ISP_MUX_ISP_PLL,
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ISP_MUX_CLKCMU_ISP_VRA_USER,
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ISP_MUX_CLKCMU_ISP_CAM_USER,
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ISP_MUX_CLKCMU_ISP_ISP_USER,
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ISP_MUX_CLK_ISP_VRA,
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ISP_MUX_CLK_ISP_CAM,
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ISP_MUX_CLK_ISP_ISP,
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ISP_MUX_CLK_ISP_ISPD,
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MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER,
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MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER,
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MIF_MUX_MEM_PLL,
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MIF_MUX_MEDIA_PLL,
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MIF_MUX_BUS_PLL,
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MIF_MUX_CLK_MIF_PHY_CLK2X,
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MIF_MUX_CLK_MIF_PHY_SWITCH,
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MIF_MUX_CLK_MIF_BUSD,
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MIF_MUX_CLK_MIF_CCI,
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MIF_MUX_CLKCMU_ISP_VRA,
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MIF_MUX_CLKCMU_ISP_CAM,
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MIF_MUX_CLKCMU_ISP_ISP,
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MIF_MUX_CLKCMU_DISPAUD_BUS,
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MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK,
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MIF_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK,
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MIF_MUX_CLKCMU_MFCMSCL_MSCL,
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MIF_MUX_CLKCMU_MFCMSCL_MFC,
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MIF_MUX_CLKCMU_FSYS_BUS,
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MIF_MUX_CLKCMU_FSYS_MMC0,
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MIF_MUX_CLKCMU_FSYS_MMC1,
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MIF_MUX_CLKCMU_FSYS_MMC2,
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MIF_MUX_CLKCMU_FSYS_UFSUNIPRO,
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MIF_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG,
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MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK,
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MIF_MUX_CLKCMU_PERI_BUS,
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MIF_MUX_CLKCMU_PERI_UART_BTWIFIFM,
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MIF_MUX_CLKCMU_PERI_UART_DEBUG,
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MIF_MUX_CLKCMU_PERI_UART_SENSOR,
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MIF_MUX_CLKCMU_PERI_SPI_FRONTFROM,
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MIF_MUX_CLKCMU_PERI_SPI_REARFROM,
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MIF_MUX_CLKCMU_PERI_SPI_ESE,
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MIF_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR,
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MIF_MUX_CLKCMU_PERI_SPI_SENSORHUB,
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MIF_MUX_CLKCMU_ISP_SENSOR0,
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MIF_MUX_CLKCMU_ISP_SENSOR1,
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MIF_MUX_CLKCMU_ISP_SENSOR2,
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/* user_mux_type */
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DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER = MIF_MUX_CLKCMU_ISP_SENSOR2 + 0x1001,
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DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER,
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DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER,
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DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER,
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DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER,
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FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER,
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FSYS_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER,
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FSYS_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER,
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ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER,
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ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER,
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MUX_END,
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NUM_OF_MUX_TYPE = MUX_END - 0x1000 - mux_type,
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CPUCL0_DIV_CLK_CPUCL0_1 = div_type,
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CPUCL0_DIV_CLK_CPUCL0_2,
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CPUCL0_DIV_CLK_CPUCL0_ACLK,
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CPUCL0_DIV_CLK_CPUCL0_PCLK,
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CPUCL0_DIV_CLK_CPUCL0_ATCLK,
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CPUCL0_DIV_CLK_CPUCL0_PCLKDBG,
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CPUCL0_DIV_CLK_CPUCL0_CNTCLK,
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CPUCL0_DIV_CLK_CPUCL0_RUN_MONITOR,
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CPUCL0_DIV_CLK_CPUCL0_HPM,
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CPUCL0_DIV_CLK_CPUCL0_PLL,
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CPUCL1_DIV_CLK_CPUCL1_1,
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CPUCL1_DIV_CLK_CPUCL1_2,
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CPUCL1_DIV_CLK_CPUCL1_ACLK,
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CPUCL1_DIV_CLK_CPUCL1_PCLK,
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CPUCL1_DIV_CLK_CPUCL1_ATCLK,
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CPUCL1_DIV_CLK_CPUCL1_PCLKDBG,
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CPUCL1_DIV_CLK_CPUCL1_CNTCLK,
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CPUCL1_DIV_CLK_CPUCL1_RUN_MONITOR,
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CPUCL1_DIV_CLK_CPUCL1_HPM,
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CPUCL1_DIV_CLK_CPUCL1_PLL,
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DISPAUD_DIV_CLK_DISPAUD_APB,
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DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK,
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DISPAUD_DIV_CLK_DISPAUD_DECON_INT_ECLK,
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DISPAUD_DIV_CLK_DISPAUD_MI2S,
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DISPAUD_DIV_CLK_DISPAUD_MIXER,
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G3D_DIV_CLK_G3D_BUS,
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G3D_DIV_CLK_G3D_APB,
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ISP_DIV_CLK_ISP_APB,
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ISP_DIV_CLK_ISP_CAM_HALF,
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MFCMSCL_DIV_CLK_MFCMSCL_APB,
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MIF_DIV_CLK_MIF_PHY_CLKM,
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MIF_DIV_CLK_MIF_BUSD,
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MIF_DIV_CLK_MIF_APB,
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MIF_DIV_CLK_MIF_CCI,
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MIF_DIV_CLK_MIF_BUSP,
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MIF_DIV_CLK_MIF_HSI2C,
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MIF_DIV_CLKCMU_CP_MEDIA_PLL,
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MIF_DIV_CLKCMU_CPUCL0_SWITCH,
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MIF_DIV_CLKCMU_CPUCL1_SWITCH,
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MIF_DIV_CLKCMU_G3D_SWITCH,
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MIF_DIV_CLKCMU_ISP_VRA,
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MIF_DIV_CLKCMU_ISP_CAM,
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MIF_DIV_CLKCMU_ISP_ISP,
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MIF_DIV_CLKCMU_DISPAUD_BUS,
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MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK,
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MIF_DIV_CLKCMU_DISPAUD_DECON_INT_ECLK,
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MIF_DIV_CLKCMU_MFCMSCL_MSCL,
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MIF_DIV_CLKCMU_MFCMSCL_MFC,
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MIF_DIV_CLKCMU_FSYS_BUS,
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MIF_DIV_CLKCMU_FSYS_MMC0,
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MIF_DIV_CLKCMU_FSYS_MMC1,
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MIF_DIV_CLKCMU_FSYS_MMC2,
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MIF_DIV_CLKCMU_FSYS_UFSUNIPRO,
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MIF_DIV_CLKCMU_FSYS_UFSUNIPRO_CFG,
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MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK,
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MIF_DIV_CLKCMU_PERI_BUS,
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MIF_DIV_CLKCMU_PERI_UART_BTWIFIFM,
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MIF_DIV_CLKCMU_PERI_UART_DEBUG,
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MIF_DIV_CLKCMU_PERI_UART_SENSOR,
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MIF_DIV_CLKCMU_PERI_SPI_FRONTFROM,
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MIF_DIV_CLKCMU_PERI_SPI_REARFROM,
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MIF_DIV_CLKCMU_PERI_SPI_ESE,
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MIF_DIV_CLKCMU_PERI_SPI_VOICEPROCESSOR,
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MIF_DIV_CLKCMU_PERI_SPI_SENSORHUB,
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MIF_DIV_CLKCMU_ISP_SENSOR0,
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MIF_DIV_CLKCMU_ISP_SENSOR1,
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MIF_DIV_CLKCMU_ISP_SENSOR2,
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DIV_END,
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NUM_OF_DIV_TYPE = DIV_END - div_type,
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CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_CLK = gate_type,
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CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_CLK__PMU_CPUCL0,
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CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_D_CPUCL0_IPCLKPORT_I_CLK,
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CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK,
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CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_PCLK,
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CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_PCLK,
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CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK,
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CPUCL0_GATE_CLK_CPUCL0_UID_BUSP1_CPUCL0_IPCLKPORT_ACLK,
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CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CPUCL0_IPCLKPORT_I_CLK,
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CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_ATCLK,
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CPUCL0_GATE_CLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk,
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CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLKDBG,
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CPUCL0_GATE_CLK_CPUCL0_UID_DBG_MUX_CPUCL0_IPCLKPORT_I_CLK,
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CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG,
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CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_CSSYS_DBG_IPCLKPORT_PCLKS,
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CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_T_CSSYS_DBG_IPCLKPORT_ACLK,
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CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CSSYS_DBG_IPCLKPORT_PCLKM,
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CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_I_HPM_TARGETCLK_C,
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CPUCL1_GATE_CLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_CLK,
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CPUCL1_GATE_CLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_I_CLK__PMU_CPUCL1,
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CPUCL1_GATE_CLK_CPUCL1_UID_ASYNCS_D_CPUCL1_IPCLKPORT_I_CLK,
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CPUCL1_GATE_CLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK,
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CPUCL1_GATE_CLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_PCLK,
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CPUCL1_GATE_CLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_I_PCLK,
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CPUCL1_GATE_CLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK,
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CPUCL1_GATE_CLK_CPUCL1_UID_BUSP1_CPUCL1_IPCLKPORT_ACLK,
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CPUCL1_GATE_CLK_CPUCL1_UID_ASYNCM_P_CPUCL1_IPCLKPORT_I_CLK,
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CPUCL1_GATE_CLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLKDBG,
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CPUCL1_GATE_CLK_CPUCL1_UID_DBG_MUX_CPUCL1_IPCLKPORT_I_CLK,
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CPUCL1_GATE_CLK_CPUCL1_UID_ASYNCM_CSSYS_DBG_IPCLKPORT_PCLKM,
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CPUCL1_GATE_CLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_I_HPM_TARGETCLK_C,
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DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK,
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DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU,
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DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP,
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DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_VPP,
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DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS,
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DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP,
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DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD,
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DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP,
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DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB,
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DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_CFW,
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DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK,
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DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_ECLK,
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DISPAUD_GATE_CLK_DISPAUD_UID_DSIM1_IPCLKPORT_I_TXBYTECLKHS,
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DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_TXBYTECLKHS,
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DISPAUD_GATE_CLK_DISPAUD_UID_DSIM1_IPCLKPORT_I_RXCLKESC0,
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DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_RXCLKESC0,
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DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI,
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DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI,
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DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK,
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DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_EXT2AUD_BCK_gpio_I2S,
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DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_BT_IN,
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DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK,
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DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_FM_IN,
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FSYS_GATE_CLK_FSYS_UID_MMC2_IPCLKPORT_I_OSCCLK,
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FSYS_GATE_CLK_FSYS_UID_MMC1_IPCLKPORT_I_OSCCLK,
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FSYS_GATE_CLK_FSYS_UID_MMC0_IPCLKPORT_I_OSCCLK,
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FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_CLK,
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FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_CLK__PMU_FSYS,
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FSYS_GATE_CLK_FSYS_UID_BUSD1_FSYS_IPCLKPORT_ACLK,
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FSYS_GATE_CLK_FSYS_UID_BUSD0_FSYS_IPCLKPORT_ACLK,
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FSYS_GATE_CLK_FSYS_UID_BUSP0_FSYS_IPCLKPORT_ACLK,
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FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HCLK_USB20_CTRL,
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FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_HSDRD,
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FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK,
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FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK,
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FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK,
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FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_PCLK,
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FSYS_GATE_CLK_FSYS_UID_ASYNCS_D_FSYS_IPCLKPORT_I_CLK,
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FSYS_GATE_CLK_FSYS_UID_ASYNCM_P_FSYS_IPCLKPORT_I_CLK,
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FSYS_GATE_CLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK,
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FSYS_GATE_CLK_FSYS_UID_UPSIZER_BUS1_FSYS_IPCLKPORT_aclk,
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FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_ACLK,
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FSYS_GATE_CLK_FSYS_UID_MMC2_IPCLKPORT_I_ACLK,
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FSYS_GATE_CLK_FSYS_UID_MMC1_IPCLKPORT_I_ACLK,
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FSYS_GATE_CLK_FSYS_UID_MMC0_IPCLKPORT_I_ACLK,
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FSYS_GATE_CLK_FSYS_UID_PDMA0_IPCLKPORT_ACLK_PDMA0,
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FSYS_GATE_CLK_FSYS_UID_SROMC_IPCLKPORT_HCLK,
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FSYS_GATE_CLK_FSYS_UID_BR_BUSP1_FSYS_IPCLKPORT_aclk,
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FSYS_GATE_CLK_FSYS_UID_BR_BUSP0_FSYS_IPCLKPORT_aclk,
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FSYS_GATE_CLK_FSYS_UID_BUSP5_FSYS_IPCLKPORT_HCLK,
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FSYS_GATE_CLK_FSYS_UID_BUSP3_FSYS_IPCLKPORT_HCLK,
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FSYS_GATE_CLK_FSYS_UID_BUSP2_FSYS_IPCLKPORT_HCLK,
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FSYS_GATE_CLK_FSYS_UID_BUSP1_FSYS_IPCLKPORT_HCLK,
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FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_PCLK,
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FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_ACLK,
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FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_PCLK,
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FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_ACLK,
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FSYS_GATE_CLK_FSYS_UID_PDMA1_IPCLKPORT_ACLK_PDMA1,
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FSYS_GATE_CLK_FSYS_UID_MMC0_IPCLKPORT_SDCLKIN,
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FSYS_GATE_CLK_FSYS_UID_MMC1_IPCLKPORT_SDCLKIN,
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FSYS_GATE_CLK_FSYS_UID_MMC2_IPCLKPORT_SDCLKIN,
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FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_CLK_UNIPRO,
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FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_CLK_UNIPRO_CFG,
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FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_ref_clk,
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FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_PHYCLOCK,
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FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_TXCLK_CH0,
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FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_RXCLK_CH0,
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G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_CLK,
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G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_CLK__PMU_G3D,
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G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_ACLK,
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G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK,
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G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK,
|
|
G3D_GATE_CLK_G3D_UID_REGSLICE_D1_G3D_IPCLKPORT_aclk,
|
|
G3D_GATE_CLK_G3D_UID_REGSLICE_D0_G3D_IPCLKPORT_aclk,
|
|
G3D_GATE_CLK_G3D_UID_IXIU_D_G3D_IPCLKPORT_ACLK,
|
|
G3D_GATE_CLK_G3D_UID_ASYNCS_D1_G3D_IPCLKPORT_I_CLK,
|
|
G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK,
|
|
G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM,
|
|
G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK,
|
|
G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_PCLK,
|
|
G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK,
|
|
G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_PCLK,
|
|
G3D_GATE_CLK_G3D_UID_BUSP_G3D_IPCLKPORT_ACLK,
|
|
G3D_GATE_CLK_G3D_UID_ASYNCM_P_G3D_IPCLKPORT_I_CLK,
|
|
G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKS,
|
|
G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_ACLK,
|
|
G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_PCLK,
|
|
ISP_GATE_CLK_ISP_UID_CLK_ISP_OSCCLK,
|
|
ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA,
|
|
ISP_GATE_CLK_ISP_UID_CLK_ISP_APB,
|
|
ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD_PPMU,
|
|
ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD,
|
|
ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM,
|
|
ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM_HALF,
|
|
ISP_GATE_CLK_ISP_UID_CLK_ISP_ISP,
|
|
ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4,
|
|
ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4S,
|
|
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_OSCCLK,
|
|
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_PPMU,
|
|
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI,
|
|
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_POLY,
|
|
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_JPEG,
|
|
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_D,
|
|
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL,
|
|
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC,
|
|
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_APB,
|
|
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_CFW,
|
|
MIF_GATE_CLK_MIF_UID_NOC_REFCLK_GEN_IPCLKPORT_I_OSC_CLK,
|
|
MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_I_OSC_SYS,
|
|
MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_CLK,
|
|
MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_CLK__PMU_MIF,
|
|
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_RCLK,
|
|
MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clk,
|
|
MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clkm,
|
|
MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_GNSS_IPCLKPORT_ACLK_Cleany,
|
|
MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_ACLK_Cleany,
|
|
MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_CPNP,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCM_LH_GNSS_MIF_D_CP_IPCLKPORT_I_CLK,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCM_LH_CP_MIF_D_CP_IPCLKPORT_I_CLK,
|
|
MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_MODEM_CPND,
|
|
MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_MIF_CPND_MIFNP,
|
|
MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_MIF_CPND,
|
|
MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_GNSS_CPND,
|
|
MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_CP_IPCLKPORT_ACLKS,
|
|
MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_RT_IPCLKPORT_ACLKS,
|
|
MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_NRT_IPCLKPORT_ACLKS,
|
|
MIF_GATE_CLK_MIF_UID_PPMU_GNSS_IPCLKPORT_ACLK,
|
|
MIF_GATE_CLK_MIF_UID_PPMU_CP_IPCLKPORT_ACLK,
|
|
MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_PERINP,
|
|
MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNRTNP,
|
|
MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNP_MIFP,
|
|
MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MFCMSCLNP,
|
|
MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_ISPNP,
|
|
MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_G3DNP,
|
|
MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_FSYSNP,
|
|
MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_DISPAUDNP,
|
|
MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_CPUNP,
|
|
MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_APLNP,
|
|
MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_PCLK_MIF_CPND_SRV,
|
|
MIF_GATE_CLK_MIF_UID_MIF_D_RT_IPCLKPORT_PCLK_MIF_RTND_SRV,
|
|
MIF_GATE_CLK_MIF_UID_MIF_D_NRT_IPCLKPORT_PCLK_MIF_NRTND_SRV,
|
|
MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_PCLK,
|
|
MIF_GATE_CLK_MIF_UID_PPMU_GNSS_IPCLKPORT_PCLK,
|
|
MIF_GATE_CLK_MIF_UID_PPMU_CP_IPCLKPORT_PCLK,
|
|
MIF_GATE_CLK_MIF_UID_PPMU_DMC0_RT_IPCLKPORT_PCLK,
|
|
MIF_GATE_CLK_MIF_UID_PPMU_DMC0_NRT_IPCLKPORT_PCLK,
|
|
MIF_GATE_CLK_MIF_UID_PPMU_DMC0_CPU_IPCLKPORT_PCLK,
|
|
MIF_GATE_CLK_MIF_UID_DDRDMC0_APB_IPCLKPORT_PCLK,
|
|
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF,
|
|
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK,
|
|
MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_PCLK,
|
|
MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_GNSS_IPCLKPORT_PCLK_Mailbox,
|
|
MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_Mailbox,
|
|
MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1,
|
|
MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0,
|
|
MIF_GATE_CLK_MIF_UID_GPIO_MIF_IPCLKPORT_PCLK,
|
|
MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK,
|
|
MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_PCLK,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCAPB_MIF_CSSYS_IPCLKPORT_PCLKS,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_CP_IPCLKPORT_PCLKS,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_AP_IPCLKPORT_PCLKS,
|
|
MIF_GATE_CLK_MIF_UID_SFRIF_PMU_ALIVE_IPCLKPORT_PCLK,
|
|
MIF_GATE_CLK_MIF_UID_AHB2APB_BUS_IPCLKPORT_HCLK,
|
|
MIF_GATE_CLK_MIF_UID_AHB2APB_MIF2_IPCLKPORT_HCLK,
|
|
MIF_GATE_CLK_MIF_UID_AHB2APB_MIF1_IPCLKPORT_HCLK,
|
|
MIF_GATE_CLK_MIF_UID_AHB2APB_MIF0_IPCLKPORT_HCLK,
|
|
MIF_GATE_CLK_MIF_UID_AHB_BRIDGE_MIF_IPCLKPORT_HCLK,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_PERI_IPCLKPORT_I_CLK,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_FSYS_IPCLKPORT_I_CLK,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_G3D_IPCLKPORT_I_CLK,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_MFCMSCL_IPCLKPORT_I_CLK,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_DISPAUD_IPCLKPORT_I_CLK,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_ISP_IPCLKPORT_I_CLK,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_CPUCL1_IPCLKPORT_I_CLK,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_CPUCL0_IPCLKPORT_I_CLK,
|
|
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF_SECURE,
|
|
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_SECURE,
|
|
MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_Mailbox_S,
|
|
MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNP_CORE,
|
|
MIF_GATE_CLK_MIF_UID_CPU1_MO_MON_IPCLKPORT_I_ACLK,
|
|
MIF_GATE_CLK_MIF_UID_CPU0_MO_MON_IPCLKPORT_I_ACLK,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCM_DBG_IPCLKPORT_ACLK,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCM_CPUCL1_IPCLKPORT_I_CLK,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCM_CPUCL0_IPCLKPORT_I_CLK,
|
|
MIF_GATE_CLK_MIF_UID_UPSIZER_DBG_MIF_D_CCI_IPCLKPORT_aclk,
|
|
MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_CPU_IPCLKPORT_ACLKS,
|
|
MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_ACLK,
|
|
MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNP_CORE_DIV,
|
|
MIF_GATE_CLK_MIF_UID_SYNC_INTC_SOC_IPCLKPORT_CLK,
|
|
MIF_GATE_CLK_MIF_UID_INTC_SOC_IPCLKPORT_CLK,
|
|
MIF_GATE_CLK_MIF_UID_INTMEM_IPCLKPORT_ACLK,
|
|
MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C,
|
|
MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C_BAT_1,
|
|
MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C_BAT_0,
|
|
MIF_GATE_CLK_MIF_UID_HSI2C_MIF_IPCLKPORT_iTCLK,
|
|
MIF_GATE_CLK_MIF_UID_HSI2C_MIF_IPCLKPORT_iPCLK,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_CP_IPCLKPORT_PCLKM,
|
|
MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_AP_IPCLKPORT_PCLKM,
|
|
MIF_GATE_CLKCMU_CP_MEDIA_PLL,
|
|
MIF_GATE_CLKCMU_CPUCL0_SWITCH,
|
|
MIF_GATE_CLKCMU_CPUCL1_SWITCH,
|
|
MIF_GATE_CLKCMU_G3D_SWITCH,
|
|
MIF_GATE_CLKCMU_ISP_VRA,
|
|
MIF_GATE_CLKCMU_ISP_CAM,
|
|
MIF_GATE_CLKCMU_ISP_ISP,
|
|
MIF_GATE_CLKCMU_DISPAUD_BUS,
|
|
MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK,
|
|
MIF_GATE_CLKCMU_DISPAUD_DECON_INT_ECLK,
|
|
MIF_GATE_CLKCMU_MFCMSCL_MSCL,
|
|
MIF_GATE_CLKCMU_MFCMSCL_MFC,
|
|
MIF_GATE_CLKCMU_FSYS_BUS,
|
|
MIF_GATE_CLKCMU_FSYS_MMC0,
|
|
MIF_GATE_CLKCMU_FSYS_MMC1,
|
|
MIF_GATE_CLKCMU_FSYS_MMC2,
|
|
MIF_GATE_CLKCMU_FSYS_UFSUNIPRO,
|
|
MIF_GATE_CLKCMU_FSYS_UFSUNIPRO_CFG,
|
|
MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK,
|
|
MIF_GATE_CLKCMU_PERI_BUS,
|
|
MIF_GATE_CLKCMU_PERI_UART_BTWIFIFM,
|
|
MIF_GATE_CLKCMU_PERI_UART_DEBUG,
|
|
MIF_GATE_CLKCMU_PERI_UART_SENSOR,
|
|
MIF_GATE_CLKCMU_PERI_SPI_FRONTFROM,
|
|
MIF_GATE_CLKCMU_PERI_SPI_REARFROM,
|
|
MIF_GATE_CLKCMU_PERI_SPI_ESE,
|
|
MIF_GATE_CLKCMU_PERI_SPI_VOICEPROCESSOR,
|
|
MIF_GATE_CLKCMU_PERI_SPI_SENSORHUB,
|
|
MIF_GATE_CLKCMU_ISP_SENSOR0,
|
|
MIF_GATE_CLKCMU_ISP_SENSOR1,
|
|
MIF_GATE_CLKCMU_ISP_SENSOR2,
|
|
PERI_GATE_CLK_PERI_UID_TMU_G3D_IPCLKPORT_I_CLK,
|
|
PERI_GATE_CLK_PERI_UID_TMU_CPUCL1_IPCLKPORT_I_CLK,
|
|
PERI_GATE_CLK_PERI_UID_TMU_CPUCL0_IPCLKPORT_I_CLK,
|
|
PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_CLK,
|
|
PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_OSCCLK,
|
|
PERI_GATE_CLK_PERI_UID_PWM_LCD_IPCLKPORT_i_OSCCLK,
|
|
PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_CLK__PMU_PERI,
|
|
PERI_GATE_CLK_PERI_UID_CHIPID_IPCLKPORT_CLK,
|
|
PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0,
|
|
PERI_GATE_CLK_PERI_UID_PWM_LCD_IPCLKPORT_i_PCLK_S0,
|
|
PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_MCT_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_I2C_SENSOR2_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_I2C_SENSOR1_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_I2C_TSP_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_I2C_TOUCHKEY_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_I2C_FUELGAUGE_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_I2C_SPKAMP_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_I2C_NFC_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_I2C_MUIC_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_I2C_IFPMIC_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_HSI2C_FRONTCAM_IPCLKPORT_iPCLK,
|
|
PERI_GATE_CLK_PERI_UID_HSI2C_MAINCAM_IPCLKPORT_iPCLK,
|
|
PERI_GATE_CLK_PERI_UID_HSI2C_DEPTHCAM_IPCLKPORT_iPCLK,
|
|
PERI_GATE_CLK_PERI_UID_HSI2C_FRONTSENSOR_IPCLKPORT_iPCLK,
|
|
PERI_GATE_CLK_PERI_UID_HSI2C_REARAF_IPCLKPORT_iPCLK,
|
|
PERI_GATE_CLK_PERI_UID_HSI2C_REARSENSOR_IPCLKPORT_iPCLK,
|
|
PERI_GATE_CLK_PERI_UID_GPIO_TOUCH_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_GPIO_TOP_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_GPIO_NFC_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_GPIO_ESE_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_BUSP1_PERIS1_IPCLKPORT_HCLK,
|
|
PERI_GATE_CLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK,
|
|
PERI_GATE_CLK_PERI_UID_BUSP1_PERIC1_IPCLKPORT_HCLK,
|
|
PERI_GATE_CLK_PERI_UID_BUSP1_PERIC0_IPCLKPORT_HCLK,
|
|
PERI_GATE_CLK_PERI_UID_BUSP_BR_PERIC_IPCLKPORT_HCLK,
|
|
PERI_GATE_CLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_aclk,
|
|
PERI_GATE_CLK_PERI_UID_ASYNCM_PERI_IPCLKPORT_I_CLK,
|
|
PERI_GATE_CLK_PERI_UID_WDT_CPUCL1_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_WDT_CPUCL0_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_UART_BTWIFIFM_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_SPI_SENSORHUB_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_SPI_VOICEPROCESSOR_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_SPI_FRONTFROM_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_SFRIF_TMU_G3D_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL1_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL0_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_SFRIF_GPIO_ALIVE_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_TZPC10_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_TZPC9_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_TZPC8_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_TZPC7_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_TZPC6_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_TZPC5_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_TZPC4_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_TZPC3_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_TZPC2_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_TZPC1_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_TZPC0_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_SFRIF_CHIPID_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_SFRIF_RTC_ALIVE_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_SFRIF_RTC_TOP_IPCLKPORT_PCLK,
|
|
PERI_GATE_CLK_PERI_UID_UART_BTWIFIFM_IPCLKPORT_EXT_UCLK,
|
|
PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK,
|
|
PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_EXT_UCLK,
|
|
PERI_GATE_CLK_PERI_UID_SPI_FRONTFROM_IPCLKPORT_SPI_EXT_CLK,
|
|
PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_SPI_EXT_CLK,
|
|
PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_SPI_EXT_CLK,
|
|
PERI_GATE_CLK_PERI_UID_SPI_VOICEPROCESSOR_IPCLKPORT_SPI_EXT_CLK,
|
|
PERI_GATE_CLK_PERI_UID_SPI_SENSORHUB_IPCLKPORT_SPI_EXT_CLK,
|
|
MIF_MUXGATE_CLKCMU_ISP_VRA,
|
|
MIF_MUXGATE_CLKCMU_ISP_CAM,
|
|
MIF_MUXGATE_CLKCMU_ISP_ISP,
|
|
MIF_MUXGATE_CLKCMU_DISPAUD_BUS,
|
|
MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_VCLK,
|
|
MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_ECLK,
|
|
MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL,
|
|
MIF_MUXGATE_CLKCMU_MFCMSCL_MFC,
|
|
MIF_MUXGATE_CLKCMU_FSYS_MMC0,
|
|
MIF_MUXGATE_CLKCMU_FSYS_MMC1,
|
|
MIF_MUXGATE_CLKCMU_FSYS_MMC2,
|
|
MIF_MUXGATE_CLKCMU_FSYS_UFSUNIPRO,
|
|
MIF_MUXGATE_CLKCMU_FSYS_UFSUNIPRO_CFG,
|
|
MIF_MUXGATE_CLKCMU_FSYS_USB20DRD_REFCLK,
|
|
MIF_MUXGATE_CLKCMU_PERI_UART_BTWIFIFM,
|
|
MIF_MUXGATE_CLKCMU_PERI_UART_DEBUG,
|
|
MIF_MUXGATE_CLKCMU_PERI_UART_SENSOR,
|
|
MIF_MUXGATE_CLKCMU_PERI_SPI_FRONTFROM,
|
|
MIF_MUXGATE_CLKCMU_PERI_SPI_REARFROM,
|
|
MIF_MUXGATE_CLKCMU_PERI_SPI_ESE,
|
|
MIF_MUXGATE_CLKCMU_PERI_SPI_VOICEPROCESSOR,
|
|
MIF_MUXGATE_CLKCMU_PERI_SPI_SENSORHUB,
|
|
MIF_MUXGATE_CLKCMU_ISP_SENSOR0,
|
|
MIF_MUXGATE_CLKCMU_ISP_SENSOR1,
|
|
MIF_MUXGATE_CLKCMU_ISP_SENSOR2,
|
|
GATE_END,
|
|
NUM_OF_GATE_TYPE = GATE_END - gate_type,
|
|
|
|
};
|
|
|
|
|
|
PLL_EXTERN(CPUCL0_PLL)
|
|
PLL_EXTERN(CPUCL1_PLL)
|
|
PLL_EXTERN(MEM_PLL)
|
|
PLL_EXTERN(BUS_PLL)
|
|
PLL_EXTERN(MEDIA_PLL)
|
|
PLL_EXTERN(G3D_PLL)
|
|
PLL_EXTERN(USB_PLL)
|
|
PLL_EXTERN(ISP_PLL)
|
|
PLL_EXTERN(DISP_PLL)
|
|
PLL_EXTERN(AUD_PLL)
|
|
|
|
FIXEDRATE_EXTERN(OSCCLK)
|
|
FIXEDRATE_EXTERN(OSCCLK_26M)
|
|
FIXEDRATE_EXTERN(CLKPHY_FSYS_USB20DRD_PHYCLOCK)
|
|
FIXEDRATE_EXTERN(CLKPHY_FSYS_UFS_TX0_SYMBOL)
|
|
FIXEDRATE_EXTERN(CLKPHY_FSYS_UFS_RX0_SYMBOL)
|
|
FIXEDRATE_EXTERN(CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS)
|
|
FIXEDRATE_EXTERN(CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0)
|
|
FIXEDRATE_EXTERN(CLKIO_DISPAUD_AUDIOCDCLK0)
|
|
FIXEDRATE_EXTERN(CLKIO_DISPAUD_MIXER_SCLK_AP)
|
|
FIXEDRATE_EXTERN(CLKIO_DISPAUD_MIXER_BCLK_BT)
|
|
FIXEDRATE_EXTERN(CLKIO_DISPAUD_MIXER_BCLK_CP)
|
|
FIXEDRATE_EXTERN(CLKIO_DISPAUD_MIXER_BCLK_FM)
|
|
FIXEDRATE_EXTERN(CLKPHY_ISP_S_RXBYTECLKHS0_S4)
|
|
FIXEDRATE_EXTERN(CLKPHY_ISP_S_RXBYTECLKHS0_S4S)
|
|
FIXEDRATE_EXTERN(FIN_TEMP)
|
|
|
|
FIXEDFACTOR_EXTERN(MIF_FF_MUX_MEM_PLL_DIV2)
|
|
FIXEDFACTOR_EXTERN(MIF_FF_MUX_MEDIA_PLL_DIV2)
|
|
FIXEDFACTOR_EXTERN(MIF_FF_MUX_BUS_PLL_DIV2)
|
|
|
|
MUX_EXTERN(CPUCL0_MUX_CPUCL0_PLL)
|
|
MUX_EXTERN(CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER)
|
|
MUX_EXTERN(CPUCL0_MUX_CLK_CPUCL0)
|
|
MUX_EXTERN(CPUCL1_MUX_CPUCL1_PLL)
|
|
MUX_EXTERN(CPUCL1_MUX_CLKCMU_CPUCL1_SWITCH_USER)
|
|
MUX_EXTERN(CPUCL1_MUX_CLK_CPUCL1)
|
|
MUX_EXTERN(DISPAUD_MUX_DISP_PLL)
|
|
MUX_EXTERN(DISPAUD_MUX_AUD_PLL)
|
|
MUX_EXTERN(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER)
|
|
MUX_EXTERN(DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER)
|
|
MUX_EXTERN(DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER)
|
|
MUX_EXTERN(DISPAUD_MUX_CLK_DISPAUD_DECON_INT_VCLK)
|
|
MUX_EXTERN(DISPAUD_MUX_CLK_DISPAUD_DECON_INT_ECLK)
|
|
MUX_EXTERN(DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER)
|
|
MUX_EXTERN(DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER)
|
|
MUX_EXTERN(DISPAUD_MUX_CLK_DISPAUD_MI2S)
|
|
MUX_EXTERN(FSYS_MUX_USB_PLL)
|
|
MUX_EXTERN(FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER)
|
|
MUX_EXTERN(FSYS_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER)
|
|
MUX_EXTERN(FSYS_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER)
|
|
MUX_EXTERN(G3D_MUX_G3D_PLL)
|
|
MUX_EXTERN(G3D_MUX_CLKCMU_G3D_SWITCH_USER)
|
|
MUX_EXTERN(G3D_MUX_CLK_G3D)
|
|
MUX_EXTERN(ISP_MUX_ISP_PLL)
|
|
MUX_EXTERN(ISP_MUX_CLKCMU_ISP_VRA_USER)
|
|
MUX_EXTERN(ISP_MUX_CLKCMU_ISP_CAM_USER)
|
|
MUX_EXTERN(ISP_MUX_CLKCMU_ISP_ISP_USER)
|
|
MUX_EXTERN(ISP_MUX_CLK_ISP_VRA)
|
|
MUX_EXTERN(ISP_MUX_CLK_ISP_CAM)
|
|
MUX_EXTERN(ISP_MUX_CLK_ISP_ISP)
|
|
MUX_EXTERN(ISP_MUX_CLK_ISP_ISPD)
|
|
MUX_EXTERN(ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER)
|
|
MUX_EXTERN(ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER)
|
|
MUX_EXTERN(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER)
|
|
MUX_EXTERN(MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER)
|
|
MUX_EXTERN(MIF_MUX_MEM_PLL)
|
|
MUX_EXTERN(MIF_MUX_MEDIA_PLL)
|
|
MUX_EXTERN(MIF_MUX_BUS_PLL)
|
|
MUX_EXTERN(MIF_MUX_CLK_MIF_PHY_CLK2X)
|
|
MUX_EXTERN(MIF_MUX_CLK_MIF_PHY_SWITCH)
|
|
MUX_EXTERN(MIF_MUX_CLK_MIF_BUSD)
|
|
MUX_EXTERN(MIF_MUX_CLK_MIF_CCI)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_ISP_VRA)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_ISP_CAM)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_ISP_ISP)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_DISPAUD_BUS)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_MFCMSCL_MSCL)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_MFCMSCL_MFC)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_FSYS_BUS)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_FSYS_MMC0)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_FSYS_MMC1)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_FSYS_MMC2)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_FSYS_UFSUNIPRO)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_BUS)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_UART_BTWIFIFM)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_UART_DEBUG)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_UART_SENSOR)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_SPI_FRONTFROM)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_SPI_REARFROM)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_SPI_ESE)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_SPI_SENSORHUB)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_ISP_SENSOR0)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_ISP_SENSOR1)
|
|
MUX_EXTERN(MIF_MUX_CLKCMU_ISP_SENSOR2)
|
|
|
|
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_1)
|
|
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_2)
|
|
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_ACLK)
|
|
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_PCLK)
|
|
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_ATCLK)
|
|
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_PCLKDBG)
|
|
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_CNTCLK)
|
|
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_RUN_MONITOR)
|
|
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_HPM)
|
|
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_PLL)
|
|
DIV_EXTERN(CPUCL1_DIV_CLK_CPUCL1_1)
|
|
DIV_EXTERN(CPUCL1_DIV_CLK_CPUCL1_2)
|
|
DIV_EXTERN(CPUCL1_DIV_CLK_CPUCL1_ACLK)
|
|
DIV_EXTERN(CPUCL1_DIV_CLK_CPUCL1_PCLK)
|
|
DIV_EXTERN(CPUCL1_DIV_CLK_CPUCL1_ATCLK)
|
|
DIV_EXTERN(CPUCL1_DIV_CLK_CPUCL1_PCLKDBG)
|
|
DIV_EXTERN(CPUCL1_DIV_CLK_CPUCL1_CNTCLK)
|
|
DIV_EXTERN(CPUCL1_DIV_CLK_CPUCL1_RUN_MONITOR)
|
|
DIV_EXTERN(CPUCL1_DIV_CLK_CPUCL1_HPM)
|
|
DIV_EXTERN(CPUCL1_DIV_CLK_CPUCL1_PLL)
|
|
DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_APB)
|
|
DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK)
|
|
DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_DECON_INT_ECLK)
|
|
DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_MI2S)
|
|
DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_MIXER)
|
|
DIV_EXTERN(G3D_DIV_CLK_G3D_BUS)
|
|
DIV_EXTERN(G3D_DIV_CLK_G3D_APB)
|
|
DIV_EXTERN(ISP_DIV_CLK_ISP_APB)
|
|
DIV_EXTERN(ISP_DIV_CLK_ISP_CAM_HALF)
|
|
DIV_EXTERN(MFCMSCL_DIV_CLK_MFCMSCL_APB)
|
|
DIV_EXTERN(MIF_DIV_CLK_MIF_PHY_CLKM)
|
|
DIV_EXTERN(MIF_DIV_CLK_MIF_BUSD)
|
|
DIV_EXTERN(MIF_DIV_CLK_MIF_APB)
|
|
DIV_EXTERN(MIF_DIV_CLK_MIF_CCI)
|
|
DIV_EXTERN(MIF_DIV_CLK_MIF_BUSP)
|
|
DIV_EXTERN(MIF_DIV_CLK_MIF_HSI2C)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_CP_MEDIA_PLL)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_CPUCL0_SWITCH)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_CPUCL1_SWITCH)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_G3D_SWITCH)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_ISP_VRA)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_ISP_CAM)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_ISP_ISP)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_DISPAUD_BUS)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_DISPAUD_DECON_INT_ECLK)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_MFCMSCL_MSCL)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_MFCMSCL_MFC)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_FSYS_BUS)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_FSYS_MMC0)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_FSYS_MMC1)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_FSYS_MMC2)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_FSYS_UFSUNIPRO)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_FSYS_UFSUNIPRO_CFG)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_BUS)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_UART_BTWIFIFM)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_UART_DEBUG)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_UART_SENSOR)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_SPI_FRONTFROM)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_SPI_REARFROM)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_SPI_ESE)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_SPI_VOICEPROCESSOR)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_SPI_SENSORHUB)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_ISP_SENSOR0)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_ISP_SENSOR1)
|
|
DIV_EXTERN(MIF_DIV_CLKCMU_ISP_SENSOR2)
|
|
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_CLK)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_CLK__PMU_CPUCL0)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_D_CPUCL0_IPCLKPORT_I_CLK)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_PCLK)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_PCLK)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_BUSP1_CPUCL0_IPCLKPORT_ACLK)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CPUCL0_IPCLKPORT_I_CLK)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_ATCLK)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLKDBG)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_DBG_MUX_CPUCL0_IPCLKPORT_I_CLK)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_CSSYS_DBG_IPCLKPORT_PCLKS)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_T_CSSYS_DBG_IPCLKPORT_ACLK)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CSSYS_DBG_IPCLKPORT_PCLKM)
|
|
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_I_HPM_TARGETCLK_C)
|
|
GATE_EXTERN(CPUCL1_GATE_CLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_CLK)
|
|
GATE_EXTERN(CPUCL1_GATE_CLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_I_CLK__PMU_CPUCL1)
|
|
GATE_EXTERN(CPUCL1_GATE_CLK_CPUCL1_UID_ASYNCS_D_CPUCL1_IPCLKPORT_I_CLK)
|
|
GATE_EXTERN(CPUCL1_GATE_CLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK)
|
|
GATE_EXTERN(CPUCL1_GATE_CLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_PCLK)
|
|
GATE_EXTERN(CPUCL1_GATE_CLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_I_PCLK)
|
|
GATE_EXTERN(CPUCL1_GATE_CLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK)
|
|
GATE_EXTERN(CPUCL1_GATE_CLK_CPUCL1_UID_BUSP1_CPUCL1_IPCLKPORT_ACLK)
|
|
GATE_EXTERN(CPUCL1_GATE_CLK_CPUCL1_UID_ASYNCM_P_CPUCL1_IPCLKPORT_I_CLK)
|
|
GATE_EXTERN(CPUCL1_GATE_CLK_CPUCL1_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLKDBG)
|
|
GATE_EXTERN(CPUCL1_GATE_CLK_CPUCL1_UID_DBG_MUX_CPUCL1_IPCLKPORT_I_CLK)
|
|
GATE_EXTERN(CPUCL1_GATE_CLK_CPUCL1_UID_ASYNCM_CSSYS_DBG_IPCLKPORT_PCLKM)
|
|
GATE_EXTERN(CPUCL1_GATE_CLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_I_HPM_TARGETCLK_C)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_VPP)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_CFW)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_ECLK)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM1_IPCLKPORT_I_TXBYTECLKHS)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_TXBYTECLKHS)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM1_IPCLKPORT_I_RXCLKESC0)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_RXCLKESC0)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_EXT2AUD_BCK_gpio_I2S)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_BT_IN)
|
|
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK)
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GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_FM_IN)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC2_IPCLKPORT_I_OSCCLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC1_IPCLKPORT_I_OSCCLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC0_IPCLKPORT_I_OSCCLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_CLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_CLK__PMU_FSYS)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSD1_FSYS_IPCLKPORT_ACLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSD0_FSYS_IPCLKPORT_ACLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSP0_FSYS_IPCLKPORT_ACLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HCLK_USB20_CTRL)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_HSDRD)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_PCLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_ASYNCS_D_FSYS_IPCLKPORT_I_CLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_ASYNCM_P_FSYS_IPCLKPORT_I_CLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_UPSIZER_BUS1_FSYS_IPCLKPORT_aclk)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_ACLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC2_IPCLKPORT_I_ACLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC1_IPCLKPORT_I_ACLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC0_IPCLKPORT_I_ACLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_PDMA0_IPCLKPORT_ACLK_PDMA0)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_SROMC_IPCLKPORT_HCLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BR_BUSP1_FSYS_IPCLKPORT_aclk)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BR_BUSP0_FSYS_IPCLKPORT_aclk)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSP5_FSYS_IPCLKPORT_HCLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSP3_FSYS_IPCLKPORT_HCLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSP2_FSYS_IPCLKPORT_HCLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSP1_FSYS_IPCLKPORT_HCLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_PCLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_ACLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_PCLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_ACLK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_PDMA1_IPCLKPORT_ACLK_PDMA1)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC0_IPCLKPORT_SDCLKIN)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC1_IPCLKPORT_SDCLKIN)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC2_IPCLKPORT_SDCLKIN)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_CLK_UNIPRO)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_CLK_UNIPRO_CFG)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_ref_clk)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_PHYCLOCK)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_TXCLK_CH0)
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GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_UFS_TOP_IPCLKPORT_I_RXCLK_CH0)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_CLK)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_CLK__PMU_G3D)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_ACLK)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_REGSLICE_D1_G3D_IPCLKPORT_aclk)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_REGSLICE_D0_G3D_IPCLKPORT_aclk)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_IXIU_D_G3D_IPCLKPORT_ACLK)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_ASYNCS_D1_G3D_IPCLKPORT_I_CLK)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_PCLK)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_PCLK)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_BUSP_G3D_IPCLKPORT_ACLK)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_ASYNCM_P_G3D_IPCLKPORT_I_CLK)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKS)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_ACLK)
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GATE_EXTERN(G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_PCLK)
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GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLK_ISP_OSCCLK)
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GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA)
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GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLK_ISP_APB)
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GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD_PPMU)
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GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD)
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GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM)
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GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM_HALF)
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GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISP)
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|
GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4)
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GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4S)
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GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_OSCCLK)
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GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_PPMU)
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GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI)
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GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_POLY)
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GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_JPEG)
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GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_D)
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GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL)
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GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC)
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GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_APB)
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GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_CFW)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_NOC_REFCLK_GEN_IPCLKPORT_I_OSC_CLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_I_OSC_SYS)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_CLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_CLK__PMU_MIF)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_RCLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clk)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clkm)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_GNSS_IPCLKPORT_ACLK_Cleany)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_ACLK_Cleany)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_CPNP)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCM_LH_GNSS_MIF_D_CP_IPCLKPORT_I_CLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCM_LH_CP_MIF_D_CP_IPCLKPORT_I_CLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_MODEM_CPND)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_MIF_CPND_MIFNP)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_MIF_CPND)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_ACLK_GNSS_CPND)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_CP_IPCLKPORT_ACLKS)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_RT_IPCLKPORT_ACLKS)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_NRT_IPCLKPORT_ACLKS)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PPMU_GNSS_IPCLKPORT_ACLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PPMU_CP_IPCLKPORT_ACLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_PERINP)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNRTNP)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNP_MIFP)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MFCMSCLNP)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_ISPNP)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_G3DNP)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_FSYSNP)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_DISPAUDNP)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_CPUNP)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_APLNP)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MIF_D_CP_IPCLKPORT_PCLK_MIF_CPND_SRV)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MIF_D_RT_IPCLKPORT_PCLK_MIF_RTND_SRV)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MIF_D_NRT_IPCLKPORT_PCLK_MIF_NRTND_SRV)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_PCLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PPMU_GNSS_IPCLKPORT_PCLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PPMU_CP_IPCLKPORT_PCLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PPMU_DMC0_RT_IPCLKPORT_PCLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PPMU_DMC0_NRT_IPCLKPORT_PCLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PPMU_DMC0_CPU_IPCLKPORT_PCLK)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DDRDMC0_APB_IPCLKPORT_PCLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_PCLK)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_GNSS_IPCLKPORT_PCLK_Mailbox)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_Mailbox)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_GPIO_MIF_IPCLKPORT_PCLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_PCLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCAPB_MIF_CSSYS_IPCLKPORT_PCLKS)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_CP_IPCLKPORT_PCLKS)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_AP_IPCLKPORT_PCLKS)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SFRIF_PMU_ALIVE_IPCLKPORT_PCLK)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AHB2APB_BUS_IPCLKPORT_HCLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AHB2APB_MIF2_IPCLKPORT_HCLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AHB2APB_MIF1_IPCLKPORT_HCLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AHB2APB_MIF0_IPCLKPORT_HCLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AHB_BRIDGE_MIF_IPCLKPORT_HCLK)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_PERI_IPCLKPORT_I_CLK)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_FSYS_IPCLKPORT_I_CLK)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_G3D_IPCLKPORT_I_CLK)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_MFCMSCL_IPCLKPORT_I_CLK)
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GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_DISPAUD_IPCLKPORT_I_CLK)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_ISP_IPCLKPORT_I_CLK)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_CPUCL1_IPCLKPORT_I_CLK)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCS_LH_MIF_P_CPUCL0_IPCLKPORT_I_CLK)
|
|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF_SECURE)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_SECURE)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_Mailbox_S)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNP_CORE)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_CPU1_MO_MON_IPCLKPORT_I_ACLK)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_CPU0_MO_MON_IPCLKPORT_I_ACLK)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCM_DBG_IPCLKPORT_ACLK)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCM_CPUCL1_IPCLKPORT_I_CLK)
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|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCM_CPUCL0_IPCLKPORT_I_CLK)
|
|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_UPSIZER_DBG_MIF_D_CCI_IPCLKPORT_aclk)
|
|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNC_DMC0_CPU_IPCLKPORT_ACLKS)
|
|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_ACLK)
|
|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_NOC_MIF_P_IPCLKPORT_ACLK_MIFNP_CORE_DIV)
|
|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SYNC_INTC_SOC_IPCLKPORT_CLK)
|
|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_INTC_SOC_IPCLKPORT_CLK)
|
|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_INTMEM_IPCLKPORT_ACLK)
|
|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C)
|
|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C_BAT_1)
|
|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C_BAT_0)
|
|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_HSI2C_MIF_IPCLKPORT_iTCLK)
|
|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_HSI2C_MIF_IPCLKPORT_iPCLK)
|
|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_CP_IPCLKPORT_PCLKM)
|
|
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_AP_IPCLKPORT_PCLKM)
|
|
GATE_EXTERN(MIF_GATE_CLKCMU_CP_MEDIA_PLL)
|
|
GATE_EXTERN(MIF_GATE_CLKCMU_CPUCL0_SWITCH)
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GATE_EXTERN(MIF_GATE_CLKCMU_CPUCL1_SWITCH)
|
|
GATE_EXTERN(MIF_GATE_CLKCMU_G3D_SWITCH)
|
|
GATE_EXTERN(MIF_GATE_CLKCMU_ISP_VRA)
|
|
GATE_EXTERN(MIF_GATE_CLKCMU_ISP_CAM)
|
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GATE_EXTERN(MIF_GATE_CLKCMU_ISP_ISP)
|
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GATE_EXTERN(MIF_GATE_CLKCMU_DISPAUD_BUS)
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GATE_EXTERN(MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK)
|
|
GATE_EXTERN(MIF_GATE_CLKCMU_DISPAUD_DECON_INT_ECLK)
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|
GATE_EXTERN(MIF_GATE_CLKCMU_MFCMSCL_MSCL)
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GATE_EXTERN(MIF_GATE_CLKCMU_MFCMSCL_MFC)
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GATE_EXTERN(MIF_GATE_CLKCMU_FSYS_BUS)
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GATE_EXTERN(MIF_GATE_CLKCMU_FSYS_MMC0)
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GATE_EXTERN(MIF_GATE_CLKCMU_FSYS_MMC1)
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GATE_EXTERN(MIF_GATE_CLKCMU_FSYS_MMC2)
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GATE_EXTERN(MIF_GATE_CLKCMU_FSYS_UFSUNIPRO)
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GATE_EXTERN(MIF_GATE_CLKCMU_FSYS_UFSUNIPRO_CFG)
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GATE_EXTERN(MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK)
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GATE_EXTERN(MIF_GATE_CLKCMU_PERI_BUS)
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GATE_EXTERN(MIF_GATE_CLKCMU_PERI_UART_BTWIFIFM)
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GATE_EXTERN(MIF_GATE_CLKCMU_PERI_UART_DEBUG)
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GATE_EXTERN(MIF_GATE_CLKCMU_PERI_UART_SENSOR)
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GATE_EXTERN(MIF_GATE_CLKCMU_PERI_SPI_FRONTFROM)
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GATE_EXTERN(MIF_GATE_CLKCMU_PERI_SPI_REARFROM)
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GATE_EXTERN(MIF_GATE_CLKCMU_PERI_SPI_ESE)
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GATE_EXTERN(MIF_GATE_CLKCMU_PERI_SPI_VOICEPROCESSOR)
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GATE_EXTERN(MIF_GATE_CLKCMU_PERI_SPI_SENSORHUB)
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GATE_EXTERN(MIF_GATE_CLKCMU_ISP_SENSOR0)
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GATE_EXTERN(MIF_GATE_CLKCMU_ISP_SENSOR1)
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GATE_EXTERN(MIF_GATE_CLKCMU_ISP_SENSOR2)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TMU_G3D_IPCLKPORT_I_CLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TMU_CPUCL1_IPCLKPORT_I_CLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TMU_CPUCL0_IPCLKPORT_I_CLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_CLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_OSCCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_PWM_LCD_IPCLKPORT_i_OSCCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_CLK__PMU_PERI)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_CHIPID_IPCLKPORT_CLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_PWM_LCD_IPCLKPORT_i_PCLK_S0)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_MCT_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_SENSOR2_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_SENSOR1_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_TSP_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_TOUCHKEY_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_FUELGAUGE_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_SPKAMP_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_NFC_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_MUIC_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_IFPMIC_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTCAM_IPCLKPORT_iPCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_MAINCAM_IPCLKPORT_iPCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_DEPTHCAM_IPCLKPORT_iPCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTSENSOR_IPCLKPORT_iPCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_REARAF_IPCLKPORT_iPCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_REARSENSOR_IPCLKPORT_iPCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_GPIO_TOUCH_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_GPIO_TOP_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_GPIO_NFC_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_GPIO_ESE_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_BUSP1_PERIS1_IPCLKPORT_HCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC1_IPCLKPORT_HCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC0_IPCLKPORT_HCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_BUSP_BR_PERIC_IPCLKPORT_HCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_aclk)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_ASYNCM_PERI_IPCLKPORT_I_CLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_WDT_CPUCL1_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_WDT_CPUCL0_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_UART_BTWIFIFM_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_SENSORHUB_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_VOICEPROCESSOR_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_FRONTFROM_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_G3D_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL1_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL0_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_GPIO_ALIVE_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC10_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC9_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC8_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC7_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC6_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC5_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC4_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC3_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC2_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC1_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC0_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_CHIPID_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_RTC_ALIVE_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_RTC_TOP_IPCLKPORT_PCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_UART_BTWIFIFM_IPCLKPORT_EXT_UCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_EXT_UCLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_FRONTFROM_IPCLKPORT_SPI_EXT_CLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_SPI_EXT_CLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_SPI_EXT_CLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_VOICEPROCESSOR_IPCLKPORT_SPI_EXT_CLK)
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GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_SENSORHUB_IPCLKPORT_SPI_EXT_CLK)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_ISP_VRA)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_ISP_CAM)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_ISP_ISP)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_DISPAUD_BUS)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_VCLK)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_ECLK)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_MFCMSCL_MFC)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_FSYS_MMC0)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_FSYS_MMC1)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_FSYS_MMC2)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_FSYS_UFSUNIPRO)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_FSYS_UFSUNIPRO_CFG)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_FSYS_USB20DRD_REFCLK)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_UART_BTWIFIFM)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_UART_DEBUG)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_UART_SENSOR)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_SPI_FRONTFROM)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_SPI_REARFROM)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_SPI_ESE)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_SPI_VOICEPROCESSOR)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_SPI_SENSORHUB)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_ISP_SENSOR0)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_ISP_SENSOR1)
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GATE_EXTERN(MIF_MUXGATE_CLKCMU_ISP_SENSOR2)
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#endif
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