mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-01 08:38:52 +01:00
198 lines
7.7 KiB
C
198 lines
7.7 KiB
C
#include "../pwrcal.h"
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#include "../pwrcal-env.h"
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#include "../pwrcal-rae.h"
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#include "../pwrcal-pmu.h"
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#include "S5E7870-cmusfr.h"
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#include "S5E7870-pmusfr.h"
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#include "S5E7870-cmu.h"
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static void dispaud_prev(int enable)
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{
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if (enable == 0) {
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pwrcal_setf(CLK_ENABLE_CLK_DISPAUD_BUS, 0, 0x7, 0x7);
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pwrcal_setf(CLK_ENABLE_CLK_DISPAUD_APB, 0, 0x1, 0x1);
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pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 12, 0);
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pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 12, 0);
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pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 27, 1);
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pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 27, 1);
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}
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pwrcal_setf(PMU_CLKRUN_CMU_DISPAUD_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_CLKSTOP_CMU_DISPAUD_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_DISABLE_PLL_CMU_DISPAUD_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_RESET_LOGIC_DISPAUD_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_RESET_CMU_DISPAUD_SYS_PWR_REG, 0, 0x1, 0x0);
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}
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static void g3d_prev(int enable)
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{
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if (enable == 0) {
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pwrcal_setf(CLK_ENABLE_CLK_G3D_BUS, 1, 0x3, 0x3);
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pwrcal_setf(CLK_ENABLE_CLK_G3D_APB, 1, 0x1, 0x1);
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}
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pwrcal_setf(PMU_CLKRUN_CMU_G3D_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_CLKSTOP_CMU_G3D_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_DISABLE_PLL_CMU_G3D_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_RESET_LOGIC_G3D_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_RESET_CMU_G3D_SYS_PWR_REG, 0, 0x1, 0x0);
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}
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static void isp_prev(int enable)
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{
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if (enable == 0) {
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pwrcal_setf(CLK_ENABLE_CLK_ISP_VRA, 0, 0x1, 0x1);
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pwrcal_setf(CLK_ENABLE_CLK_ISP_APB, 0, 0x1, 0x1);
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pwrcal_setf(CLK_ENABLE_CLK_ISP_ISPD, 0, 0x1, 0x1);
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pwrcal_setf(CLK_ENABLE_CLK_ISP_CAM, 0, 0x1, 0x1);
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pwrcal_setf(CLK_ENABLE_CLK_ISP_ISP, 0, 0x1, 0x1);
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pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 12, 0);
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pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER, 12, 0);
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pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 27, 1);
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pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER, 27, 1);
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#if 0 // plz, check the sfr name first
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while (pwrcal_getf((void *)0x14403020, 0, 0x1) != 0x0);
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while (pwrcal_getf((void *)0x14443010, 0, 0x1) != 0x0);
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while (pwrcal_getf((void *)0x1444B010, 0, 0x1) != 0x0);
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#endif
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}
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pwrcal_setf(PMU_CLKRUN_CMU_ISP_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_CLKSTOP_CMU_ISP_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_DISABLE_PLL_CMU_ISP_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_RESET_LOGIC_ISP_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_RESET_CMU_ISP_SYS_PWR_REG, 0, 0x1, 0x0);
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}
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static void mfcmscl_prev(int enable)
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{
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if (enable == 0) {
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pwrcal_setf(CLK_ENABLE_CLK_MFCMSCL_MSCL, 0, 0x1D, 0x1D);
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pwrcal_setf(CLK_ENABLE_CLK_MFCMSCL_APB, 0, 0x1, 0x1);
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pwrcal_setf(CLK_ENABLE_CLK_MFCMSCL_MFC, 0, 0x1, 0x1);
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}
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pwrcal_setf(PMU_CLKRUN_CMU_MFCMSCL_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_CLKSTOP_CMU_MFCMSCL_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_DISABLE_PLL_CMU_MFCMSCL_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_RESET_LOGIC_MFCMSCL_SYS_PWR_REG, 0, 0x1, 0x0);
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pwrcal_setf(PMU_RESET_CMU_MFCMSCL_SYS_PWR_REG, 0, 0x1, 0x0);
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}
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static void dispaud_post(int enable)
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{
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if (enable == 1) {
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_EXT2AUD_BCK_gpio_I2S));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_BT_IN));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_FM_IN));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_ECLK));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI));
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/*non used disable*/
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_VPP));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM1_IPCLKPORT_I_TXBYTECLKHS));
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pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM1_IPCLKPORT_I_RXCLKESC0));
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}
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}
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static void g3d_post(int enable)
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{
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if (enable == 1) {
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pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK));
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pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK));
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pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_ACLK));
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pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK));
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pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK));
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pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM));
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pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK));
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pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_PCLK));
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}
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}
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static void isp_post(int enable)
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{
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if (enable == 1) {
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pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD_PPMU));
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pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD));
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pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM));
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pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM_HALF));
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pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA));
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/*non used disable*/
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pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISP));
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}
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}
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static void mfcmscl_post(int enable)
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{
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if (enable == 1) {
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pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_PPMU));
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pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_D));
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pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL));
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pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI));
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pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_POLY));
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pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_JPEG));
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pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC));
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}
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}
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static void dispaud_config(int enable)
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{
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pwrcal_setf(PMU_DISPAUD_OPTION, 0, 0x3, 0x2);
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pwrcal_setf(PMU_PAD_RETENTION_AUD_OPTION, 0, 0xFFFFFFFF, 0x10000000);
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}
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static void g3d_config(int enable)
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{
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pwrcal_setf(PMU_G3D_OPTION, 0, 0x1, 0x1);
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pwrcal_setf(PMU_G3D_DURATION0, 4, 0xFF, 0x0);
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}
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static void isp_config(int enable)
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{
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pwrcal_setf(PMU_ISP_OPTION, 0, 0x3, 0x2);
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}
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static void mfcmscl_config(int enable)
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{
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pwrcal_setf(PMU_MFCMSCL_OPTION, 0, 0x3, 0x2);
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}
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BLKPWR(blkpwr_dispaud, PMU_DISPAUD_CONFIGURATION, 0, 0xF, PMU_DISPAUD_STATUS, 0, 0xF, dispaud_config, dispaud_prev, dispaud_post);
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BLKPWR(blkpwr_g3d, PMU_G3D_CONFIGURATION, 0, 0xF, PMU_G3D_STATUS, 0, 0xF, g3d_config, g3d_prev, g3d_post);
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BLKPWR(blkpwr_isp, PMU_ISP_CONFIGURATION, 0, 0xF, PMU_ISP_STATUS, 0, 0xF, isp_config, isp_prev, isp_post);
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BLKPWR(blkpwr_mfcmscl, PMU_MFCMSCL_CONFIGURATION, 0, 0xF, PMU_MFCMSCL_STATUS, 0, 0xF, mfcmscl_config, mfcmscl_prev, mfcmscl_post);
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struct cal_pd *pwrcal_blkpwr_list[4];
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unsigned int pwrcal_blkpwr_size = 4;
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static int blkpwr_init(void)
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{
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pwrcal_blkpwr_list[0] = &blkpwr_blkpwr_dispaud;
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pwrcal_blkpwr_list[1] = &blkpwr_blkpwr_g3d;
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pwrcal_blkpwr_list[2] = &blkpwr_blkpwr_isp;
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pwrcal_blkpwr_list[3] = &blkpwr_blkpwr_mfcmscl;
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return 0;
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}
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struct cal_pd_ops cal_pd_ops = {
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.pd_control = blkpwr_control,
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.pd_status = blkpwr_status,
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.pd_init = blkpwr_init,
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};
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