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android_kernel_samsung_on5x.../drivers/soc/samsung/pwrcal/S5E7870/S5E7870-syspwr.c
awab228 f6dfaef42e Fixed MTP to work with TWRP
2018-06-19 23:16:04 +02:00

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/*
* Copyright (c) 2015 Samsung Electronics Co., Ltd. All rights reserved.
* http://www.samsung.com
*
* Chip Abstraction Layer for System power down support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "../pwrcal-env.h"
#include "../pwrcal.h"
#include "../pwrcal-pmu.h"
#include "../pwrcal-rae.h"
#include "S5E7870-cmusfr.h"
#include "S5E7870-pmusfr.h"
#include "S5E7870-cmu.h"
enum sys_powerdown {
SYS_SICD,
SYS_AFTR,
SYS_STOP,
SYS_LPD,
SYS_SLEEP,
NUM_SYS_POWERDOWN,
};
struct exynos_pmu_conf {
unsigned int *reg;
unsigned int val[NUM_SYS_POWERDOWN];
};
/* set_pmu_lpi_mask */
#define TIMEOUT_ENABLE (0x1 << 0)
/* init_pmu_l2_option */
#define MANUAL_ACINACTM_VALUE (0x1 << 3)
#define MANUAL_ACINACTM_CONTROL (0x1 << 2)
#define MANUAL_AINACTS_VALUE (0x1 << 1)
#define MANUAL_AINACTS_CONTROL (0x1 << 0)
#define USE_AUTOMATIC_L2FLUSHREQ (0x1 << 17)
#define USE_STANDBYWFIL2 (0x1 << 16)
#define USE_RETENTION (0x1 << 4)
/* CPU option */
#define USE_SMPEN (0x1 << 28)
#define USE_STANDBYWFE (0x1 << 24)
#define USE_STANDBYWFI (0x1 << 16)
#define USE_IRQCPU_FOR_PWR (0x3 << 4)
#define USE_MEMPWRDOWN_FEEDBACK (0x1 << 3)
#define USE_MEMPWRDOWN_COUNTER (0x1 << 2)
#define USE_SC_FEEDBACK (0x1 << 1)
#define USE_SC_COUNTER (0x1 << 0)
#define DUR_WAIT_RESET (0xF << 20)
#define DUR_SCALL (0xF << 4)
#define DUR_SCALL_VALUE (0x1 << 4)
/* init_pmu_up_scheduler */
#define ENABLE_CPUCL0_CPU (0x1 << 0)
#define ENABLE_CPUCL1_CPU (0x1 << 1)
#define PAD_INITIATE_WAKEUP (0x1 << 28)
struct cmu_backup {
void *sfr;
unsigned int mask;
void *power;
unsigned int backup;
int backup_valid;
};
#define SYS_PWR_BACK_REG(_reg, _reg_stat, _pwr_stat_reg) \
{ \
.reg = _reg, \
.backup = 0, \
.reg_stat = _reg_stat, \
.backup_stat = 0, \
.pwr_stat_reg = _pwr_stat_reg, \
.valid = 0, \
}
static unsigned int *pmu_cpuoption_sfrlist[] = {
PMU_CPUCL0_CPU0_OPTION,
PMU_CPUCL0_CPU1_OPTION,
PMU_CPUCL0_CPU2_OPTION,
PMU_CPUCL0_CPU3_OPTION,
PMU_CPUCL1_CPU0_OPTION,
PMU_CPUCL1_CPU1_OPTION,
PMU_CPUCL1_CPU2_OPTION,
PMU_CPUCL1_CPU3_OPTION,
};
static void init_pmu_cpu_option(void)
{
int cpu;
unsigned int tmp;
/* enable to wait for low SMP-bit at sys power down */
for (cpu = 0; cpu < sizeof(pmu_cpuoption_sfrlist) / sizeof(pmu_cpuoption_sfrlist[0]); cpu++) {
tmp = pwrcal_readl(pmu_cpuoption_sfrlist[cpu]);
tmp |= USE_SC_FEEDBACK;
tmp |= USE_SMPEN;
tmp |= USE_STANDBYWFI;
tmp |= USE_MEMPWRDOWN_FEEDBACK;
tmp &= ~USE_STANDBYWFE;
tmp &= ~USE_SC_COUNTER;
pwrcal_writel(pmu_cpuoption_sfrlist[cpu], tmp);
}
}
static void set_pmu_lpi_mask(void)
{
unsigned int tmp;
tmp = pwrcal_readl(PMU_RESET_LPI_TIMEOUT);
tmp |= TIMEOUT_ENABLE;
pwrcal_writel(PMU_RESET_LPI_TIMEOUT, tmp);
}
static void init_pmu_l2_option(void)
{
unsigned int tmp;
/* disable automatic L2 flush */
/* disable L2 retention */
tmp = pwrcal_readl(PMU_CPUCL0_L2_OPTION);
tmp &= ~(USE_AUTOMATIC_L2FLUSHREQ | USE_RETENTION);
tmp |= USE_STANDBYWFIL2;
pwrcal_writel(PMU_CPUCL0_L2_OPTION, tmp);
tmp = pwrcal_readl(PMU_CPUCL1_L2_OPTION);
tmp &= ~(USE_AUTOMATIC_L2FLUSHREQ | USE_RETENTION);
tmp |= USE_STANDBYWFIL2;
pwrcal_writel(PMU_CPUCL1_L2_OPTION, tmp);
}
static void init_pmu_up_scheduler(void)
{
unsigned int tmp;
/* limit in-rush current for CPUs local power up */
tmp = pwrcal_readl(PMU_UP_SCHEDULER);
tmp |= ENABLE_CPUCL0_CPU | ENABLE_CPUCL1_CPU;
pwrcal_writel(PMU_UP_SCHEDULER, tmp);
}
/* init_pmu_feedback */
static unsigned int *pmu_feedback_sfrlist[] = {
PMU_CPUCL0_NONCPU_OPTION,
PMU_CPUCL1_NONCPU_OPTION,
PMU_TOP_PWR_OPTION,
PMU_TOP_PWR_MIF_OPTION,
PMU_DISPAUD_OPTION,
PMU_MFCMSCL_OPTION,
PMU_ISP_OPTION,
PMU_G3D_OPTION,
PMU_MEMORY_G3D_OPTION
};
/* init_set_duration */
#define XXTI_DUR_STABLE 0x658 /* 1ms @ 26MHz */
#define TCXO_DUR_STABLE 0x658 /* 1ms @ 26MHz */
#define EXT_REGULATOR_DUR_STABLE 0xFDE /* 2.5ms @ 26MHz */
#define EXT_REGULATOR_MIF_DUR_STABLE 0xCB1 /* 2ms @ 26MHz */
static void init_set_duration(void)
{
pwrcal_writel(PMU_XXTI_DURATION3, XXTI_DUR_STABLE);
pwrcal_writel(PMU_TCXO_DURATION3, TCXO_DUR_STABLE);
pwrcal_writel(PMU_EXT_REGULATOR_DURATION3, EXT_REGULATOR_DUR_STABLE);
pwrcal_writel(PMU_EXT_REGULATOR_MIF_DURATION3, EXT_REGULATOR_MIF_DUR_STABLE);
pwrcal_setf(PMU_G3D_DURATION0, 4, 0xff, 0x00);
}
static void init_pmu_feedback(void)
{
int i;
for (i = 0; i < sizeof(pmu_feedback_sfrlist) / sizeof(pmu_feedback_sfrlist[0]); i++)
pwrcal_setf(pmu_feedback_sfrlist[i], 0, USE_SC_COUNTER | USE_SC_FEEDBACK, USE_SC_FEEDBACK);
}
#define ENABLE_HW_TRIP (0x1 << 31)
#define PS_HOLD_OUTPUT_HIGH (0x3 << 8)
static void init_ps_hold_setting(void)
{
unsigned int tmp;
tmp = pwrcal_readl(PMU_PS_HOLD_CONTROL);
tmp |= (ENABLE_HW_TRIP | PS_HOLD_OUTPUT_HIGH);
pwrcal_writel(PMU_PS_HOLD_CONTROL, tmp);
}
static void enable_armidleclockdown(void)
{
pwrcal_setbit(CPUCL0_PWR_CTRL3, 0, 1); /*PWR_CTRL3[0] USE_L2QACTIVE = 1*/
pwrcal_setbit(CPUCL1_PWR_CTRL3, 0, 1); /*PWR_CTRL3[0] USE_L2QACTIVE = 1*/
}
static void disable_armidleclockdown(void)
{
pwrcal_setbit(CPUCL0_PWR_CTRL3, 0, 0); /*PWR_CTRL3[0] USE_L2QACTIVE = 0*/
pwrcal_setbit(CPUCL1_PWR_CTRL3, 0, 0); /*PWR_CTRL3[0] USE_L2QACTIVE = 0*/
}
static void syspwr_init(void)
{
set_pmu_lpi_mask();
init_pmu_feedback();
init_pmu_l2_option();
init_pmu_cpu_option();
init_pmu_up_scheduler();
init_set_duration();
init_ps_hold_setting();
enable_armidleclockdown();
}
static struct exynos_pmu_conf exynos_syspwr_pmu_config[] = {
/* { .addr = address, .val = { SICD, AFTR, STOP, LPD, SLEEP } } */
{PMU_CPUCL0_CPU0_SYS_PWR_REG, {0x0, 0x0, 0x8, 0x0, 0x8} },
{PMU_DIS_IRQ_CPUCL0_CPU0_LOCAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL0_CPU0_CENTRAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL0_CPU0_CPUSEQUENCER_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CPUCL0_CPU1_SYS_PWR_REG, {0x0, 0x0, 0x8, 0x0, 0x8} },
{PMU_DIS_IRQ_CPUCL0_CPU1_LOCAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL0_CPU1_CENTRAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL0_CPU1_CPUSEQUENCER_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CPUCL0_CPU2_SYS_PWR_REG, {0x0, 0x0, 0x8, 0x0, 0x8} },
{PMU_DIS_IRQ_CPUCL0_CPU2_LOCAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL0_CPU2_CENTRAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL0_CPU2_CPUSEQUENCER_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CPUCL0_CPU3_SYS_PWR_REG, {0x0, 0x0, 0x8, 0x0, 0x8} },
{PMU_DIS_IRQ_CPUCL0_CPU3_LOCAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL0_CPU3_CENTRAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL0_CPU3_CPUSEQUENCER_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CPUCL1_CPU0_SYS_PWR_REG, {0x0, 0x0, 0x8, 0x0, 0x8} },
{PMU_DIS_IRQ_CPUCL1_CPU0_LOCAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL1_CPU0_CENTRAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL1_CPU0_CPUSEQUENCER_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CPUCL1_CPU1_SYS_PWR_REG, {0x0, 0x0, 0x8, 0x0, 0x8} },
{PMU_DIS_IRQ_CPUCL1_CPU1_LOCAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL1_CPU1_CENTRAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL1_CPU1_CPUSEQUENCER_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CPUCL1_CPU2_SYS_PWR_REG, {0x0, 0x0, 0x8, 0x0, 0x8} },
{PMU_DIS_IRQ_CPUCL1_CPU2_LOCAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL1_CPU2_CENTRAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL1_CPU2_CPUSEQUENCER_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CPUCL1_CPU3_SYS_PWR_REG, {0x0, 0x0, 0x8, 0x0, 0x8} },
{PMU_DIS_IRQ_CPUCL1_CPU3_LOCAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL1_CPU3_CENTRAL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DIS_IRQ_CPUCL1_CPU3_CPUSEQUENCER_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CPUCL0_NONCPU_SYS_PWR_REG, {0xF, 0x0, 0xF, 0x0, 0x8} },
{PMU_CPUCL1_NONCPU_SYS_PWR_REG, {0xF, 0x0, 0xF, 0x0, 0x8} },
{PMU_CPUCL0_L2_SYS_PWR_REG, {0x7, 0x0, 0x7, 0x0, 0x7} },
{PMU_CPUCL1_L2_SYS_PWR_REG, {0x7, 0x0, 0x7, 0x0, 0x7} },
{PMU_CLKSTOP_CMU_TOP_SYS_PWR_REG, {0x1, 0x1, 0x0, 0x0, 0x0} },
{PMU_CLKRUN_CMU_TOP_SYS_PWR_REG, {0x1, 0x1, 0x0, 0x0, 0x0} },
{PMU_RETENTION_CMU_TOP_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x0, 0x3} },
{PMU_RESET_CMU_TOP_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x0} },
{PMU_RESET_CPUCLKSTOP_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x0} },
{PMU_CLKSTOP_CMU_MIF_SYS_PWR_REG, {0x1, 0x1, 0x0, 0x1, 0x0} },
{PMU_CLKRUN_CMU_MIF_SYS_PWR_REG, {0x1, 0x1, 0x0, 0x1, 0x0} },
{PMU_RETENTION_CMU_MIF_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x3} },
{PMU_RESET_CMU_MIF_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x0} },
{PMU_DDRPHY_ISO_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x1, 0x1} },
{PMU_DDRPHY_DLL_CLK_SYS_PWR_REG, {0x0, 0x1, 0x0, 0x1, 0x0} },
{PMU_DISABLE_PLL_CMU_TOP_SYS_PWR_REG, {0x0, 0x1, 0x0, 0x0, 0x0} },
{PMU_DISABLE_PLL_CMU_MIF_SYS_PWR_REG, {0x0, 0x1, 0x0, 0x1, 0x0} },
{PMU_RESET_AHEAD_CP_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x3} },
{PMU_RESET_AHEAD_GNSS_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x3} },
{PMU_TOP_BUS_SYS_PWR_REG, {0x7, 0x7, 0x0, 0x0, 0x0} },
{PMU_TOP_RETENTION_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x0, 0x3} },
{PMU_TOP_PWR_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x0, 0x3} },
{PMU_TOP_BUS_MIF_SYS_PWR_REG, {0x0, 0x7, 0x0, 0x7, 0x0} },
{PMU_TOP_RETENTION_MIF_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x3} },
{PMU_TOP_PWR_MIF_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x3} },
{PMU_LOGIC_RESET_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x0, 0x0} },
{PMU_OSCCLK_GATE_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x0, 0x1} },
{PMU_SLEEP_RESET_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x0} },
{PMU_LOGIC_RESET_MIF_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x0} },
{PMU_OSCCLK_GATE_MIF_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x1, 0x1} },
{PMU_SLEEP_RESET_MIF_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x0} },
{PMU_RESET_ASB_MIF_GNSS_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x3} },
{PMU_MEMORY_TOP_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x0, 0x3} },
{PMU_TCXO_GATE_GNSS_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x1, 0x1} },
{PMU_RESET_ASB_GNSS_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x3} },
{PMU_CLEANY_BUS_CP_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x1, 0x1} },
{PMU_LOGIC_RESET_CP_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x3} },
{PMU_TCXO_GATE_CP_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x1, 0x1} },
{PMU_RESET_ASB_CP_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x3} },
{PMU_RESET_ASB_MIF_CP_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x3} },
{PMU_MEMORY_MIF_ALIVEIRAM_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x0} },
{PMU_MEMORY_MIF_TOP_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x3} },
{PMU_CLEANY_BUS_GNSS_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x1, 0x1} },
{PMU_LOGIC_RESET_GNSS_SYS_PWR_REG, {0x3, 0x3, 0x3, 0x3, 0x3} },
{PMU_PAD_RETENTION_LPDDR3_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x1, 0x0} },
{PMU_PAD_RETENTION_AUD_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x0, 0x0} },
{PMU_PAD_RETENTION_MMC2_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x0, 0x0} },
{PMU_PAD_RETENTION_TOP_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x0, 0x0} },
{PMU_PAD_RETENTION_UART_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x0, 0x0} },
{PMU_PAD_RETENTION_MMC0_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x0, 0x0} },
{PMU_PAD_RETENTION_MMC1_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x0, 0x0} },
{PMU_PAD_RETENTION_SPI_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x0, 0x0} },
{PMU_PAD_RETENTION_MIF_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x1, 0x0} },
{PMU_PAD_ISOLATION_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x0, 0x1} },
{PMU_PAD_RETENTION_BOOTLDO_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x0, 0x0} },
{PMU_PAD_ISOLATION_MIF_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x1, 0x1} },
{PMU_PAD_ALV_SEL_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x0, 0x0} },
{PMU_TCXO_SYS_PWR_REG, {0x1, 0x1, 0x0, 0x1, 0x0} },
{PMU_EXT_REGULATOR_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x1, 0x0} },
{PMU_EXT_REGULATOR_MIF_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x1, 0x0} },
{PMU_GPIO_MODE_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x0, 0x0} },
{PMU_GPIO_MODE_MIF_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x1, 0x0} },
{PMU_GPIO_MODE_DISPAUD_SYS_PWR_REG, {0x1, 0x1, 0x1, 0x1, 0x0} },
{PMU_CLKSTOP_OPEN_CMU_TOP_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CLKSTOP_OPEN_CMU_MIF_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CLKSTOP_OPEN_CMU_G3D_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CLKSTOP_OPEN_CMU_DISPAUD_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CLKSTOP_OPEN_CMU_ISP_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CLKSTOP_OPEN_CMU_MFCMSCL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_G3D_SYS_PWR_REG, {0xF, 0xF, 0x0, 0x0, 0x0} },
{PMU_DISPAUD_SYS_PWR_REG, {0xF, 0xF, 0xF, 0xF, 0x0} },
{PMU_ISP_SYS_PWR_REG, {0xF, 0xF, 0xF, 0x0, 0x0} },
{PMU_MFCMSCL_SYS_PWR_REG, {0xF, 0xF, 0xF, 0x0, 0x0} },
{PMU_CLKRUN_CMU_G3D_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CLKRUN_CMU_DISPAUD_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CLKRUN_CMU_ISP_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CLKRUN_CMU_MFCMSCL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CLKSTOP_CMU_G3D_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CLKSTOP_CMU_DISPAUD_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CLKSTOP_CMU_ISP_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_CLKSTOP_CMU_MFCMSCL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DISABLE_PLL_CMU_G3D_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DISABLE_PLL_CMU_DISPAUD_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DISABLE_PLL_CMU_ISP_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_DISABLE_PLL_CMU_MFCMSCL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_RESET_LOGIC_G3D_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_RESET_LOGIC_DISPAUD_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_RESET_LOGIC_ISP_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_RESET_LOGIC_MFCMSCL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_MEMORY_G3D_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_MEMORY_DISPAUD_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_MEMORY_ISP_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_MEMORY_MFCMSCL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_RESET_CMU_G3D_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_RESET_CMU_DISPAUD_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_RESET_CMU_ISP_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
{PMU_RESET_CMU_MFCMSCL_SYS_PWR_REG, {0x0, 0x0, 0x0, 0x0, 0x0} },
};
static struct exynos_pmu_conf exynos_syspwr_pmu_option[] = {
/* { .addr = address, .val = { SICD, AFTR, STOP, LPD, SLEEP } } */
{PMU_TOP_BUS_MIF_OPTION, {0x3, 0x0, 0x0, 0x0, 0x0} },
{PMU_CENTRAL_SEQ_OPTION, {0xFF0000, 0xFF0000, 0xFF0000, 0xFF0000, 0xFF0000} },
{PMU_CENTRAL_SEQ_OPTION1, {0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000} },
{PMU_CENTRAL_SEQ_MIF_OPTION, {0x10, 0x10, 0x10, 0x10, 0x10} },
};
static void set_pmu_sys_pwr_reg(enum sys_powerdown mode)
{
int i;
for (i = 0; i < ARRAY_SIZE(exynos_syspwr_pmu_config); i++)
pwrcal_writel(exynos_syspwr_pmu_config[i].reg, exynos_syspwr_pmu_config[i].val[mode]);
for (i = 0; i < ARRAY_SIZE(exynos_syspwr_pmu_option); i++)
pwrcal_writel(exynos_syspwr_pmu_option[i].reg, exynos_syspwr_pmu_option[i].val[mode]);
}
#define PWRCAL_CENTRALSEQ_PWR_CFG 0x10000
static void set_pmu_central_seq(bool enable)
{
/* central sequencer */
if (enable)
pwrcal_setf(PMU_CENTRAL_SEQ_CONFIGURATION, 0, PWRCAL_CENTRALSEQ_PWR_CFG, 0);
else
pwrcal_setf(PMU_CENTRAL_SEQ_CONFIGURATION, 0, PWRCAL_CENTRALSEQ_PWR_CFG, PWRCAL_CENTRALSEQ_PWR_CFG);
}
static void set_pmu_central_seq_mif(bool enable)
{
if (enable)
pwrcal_setf(PMU_CENTRAL_SEQ_MIF_CONFIGURATION, 0, PWRCAL_CENTRALSEQ_PWR_CFG, 0);
else
pwrcal_setf(PMU_CENTRAL_SEQ_MIF_CONFIGURATION, 0, PWRCAL_CENTRALSEQ_PWR_CFG, PWRCAL_CENTRALSEQ_PWR_CFG);
}
static struct cmu_backup cmu_backup_list[] = {
{MEM_PLL_LOCK, 0xFFFFFFFF, NULL, 0, 0},
{MEDIA_PLL_LOCK, 0xFFFFFFFF, NULL, 0, 0},
{BUS_PLL_LOCK, 0xFFFFFFFF, NULL, 0, 0},
{MEM_PLL_CON0, 0xFFFFFFFF, NULL, 0, 0},
{MEM_PLL_CON1, 0xFFFFFFFF, NULL, 0, 0},
{MEDIA_PLL_CON0, 0xFFFFFFFF, NULL, 0, 0},
{MEDIA_PLL_CON1, 0xFFFFFFFF, NULL, 0, 0},
{BUS_PLL_CON0, 0xFFFFFFFF, NULL, 0, 0},
{BUS_PLL_CON1, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_MUX_MEM_PLL, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_MEDIA_PLL, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_BUS_PLL, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLK_MIF_PHY_CLK2X, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLK_MIF_PHY_SWITCH, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLK_MIF_BUSD, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLK_MIF_CCI, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_ISP_VRA, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_ISP_CAM, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_ISP_ISP, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_DISPAUD_BUS, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_MFCMSCL_MFC, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_FSYS_BUS, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_FSYS_MMC0, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_FSYS_MMC1, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_FSYS_MMC2, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_FSYS_USB20DRD_REFCLK, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_BUS, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_UART_BTWIFIFM, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_UART_DEBUG, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_UART_SENSOR, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_SPI_FRONTFROM, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_SPI_REARFROM, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_SPI_ESE, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_SPI_SENSORHUB, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_ISP_SENSOR0, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_ISP_SENSOR1, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_ISP_SENSOR2, 0xFFDFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLK_MIF_PHY_CLKM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLK_MIF_BUSD, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLK_MIF_APB, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLK_MIF_CCI, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLK_MIF_BUSP, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLK_MIF_HSI2C, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_CP_MEDIA_PLL, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_ISP_VRA, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_ISP_CAM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_ISP_ISP, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_DISPAUD_BUS, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_ECLK, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_FSYS_BUS, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_FSYS_MMC0, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_FSYS_MMC1, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_FSYS_MMC2, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_FSYS_UFSUNIPRO, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_FSYS_UFSUNIPRO_CFG, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_FSYS_USB20DRD_REFCLK, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_PERI_BUS, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_PERI_UART_BTWIFIFM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_PERI_UART_DEBUG, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_PERI_UART_SENSOR, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_PERI_SPI_FRONTFROM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_PERI_SPI_REARFROM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_PERI_SPI_ESE, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_PERI_SPI_VOICEPROCESSOR, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_PERI_SPI_SENSORHUB, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_ISP_SENSOR0, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_ISP_SENSOR1, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_ISP_SENSOR2, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_MIF_OSCCLK, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_MIF_PHY_CLK2X, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_MIF_PHY_CLKM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_MIF_DDRPHY0, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_MIF_BUSD, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_MIF_APB0, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_MIF_APB1, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_MIF_APB_SECURE_DMC0, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_MIF_APB_SECURE_MODAPIF, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_MIF_CCI, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_MIF_BUSP, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_MIF_BUSP_SECURE_INTMEM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_MIF_HSI2C, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_CP_MEDIA_PLL, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_CPUCL0_SWITCH, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_CPUCL1_SWITCH, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_G3D_SWITCH, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_ISP_VRA, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_ISP_CAM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_ISP_ISP, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_DISPAUD_BUS, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_DISPAUD_DECON_INT_VCLK, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_DISPAUD_DECON_INT_ECLK, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_MFCMSCL_MSCL, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_MFCMSCL_MFC, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_FSYS_BUS, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_FSYS_MMC0, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_FSYS_MMC1, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_FSYS_MMC2, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_FSYS_UFSUNIPRO, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_FSYS_UFSUNIPRO_CFG, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_FSYS_USB20DRD_REFCLK, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_PERI_BUS, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_PERI_UART_BTWIFIFM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_PERI_UART_DEBUG, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_PERI_UART_SENSOR, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_PERI_SPI_FRONTFROM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_PERI_SPI_REARFROM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_PERI_SPI_ESE, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_PERI_SPI_VOICEPROCESSOR, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_PERI_SPI_SENSORHUB, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_ISP_SENSOR0, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_ISP_SENSOR1, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_ISP_SENSOR2, 0xFFFFFFFF, NULL, 0, 0},
{CLKOUT_CMU_MIF, 0xFFFFFFFF, NULL, 0, 0},
{CLKOUT_CMU_MIF_DIV_STAT, 0xFFFFFFFF, NULL, 0, 0},
{CP_CTRL_HSI2C_ENABLE, 0xFFFFFFFF, NULL, 0, 0},
{CP_CTRL_ADCIF_ENABLE, 0xFFFFFFFF, NULL, 0, 0},
{CG_CTRL_VAL_CLK_MIF_BUSD, 0xFFFFFFFF, NULL, 0, 0},
{CG_CTRL_VAL_CLK_MIF_APB, 0xFFFFFFFF, NULL, 0, 0},
{CG_CTRL_VAL_CLK_MIF_CCI, 0xFFFFFFFF, NULL, 0, 0},
{CG_CTRL_MAN_CLK_MIF_BUSD, 0xFFFFFFFF, NULL, 0, 0},
{CG_CTRL_MAN_CLK_MIF_APB, 0xFFFFFFFF, NULL, 0, 0},
{CG_CTRL_MAN_CLK_MIF_CCI, 0xFFFFFFFF, NULL, 0, 0},
{CG_CTRL_STAT_CLK_MIF_BUSD, 0xFFFFFFFF, NULL, 0, 0},
{CG_CTRL_STAT_CLK_MIF_APB, 0xFFFFFFFF, NULL, 0, 0},
{CG_CTRL_STAT_CLK_MIF_CCI, 0xFFFFFFFF, NULL, 0, 0},
{QCH_CTRL_UID_MIF_D_CCI, 0xFFFFFFFF, NULL, 0, 0},
{QCH_CTRL_UID_MIF_D_NRT, 0xFFFFFFFF, NULL, 0, 0},
{QCH_CTRL_UID_MIF_D_RT, 0xFFFFFFFF, NULL, 0, 0},
{QCH_CTRL_UID_ASYNCM_LH_G3D0_MIF_D_NRT, 0xFFFFFFFF, NULL, 0, 0},
{QCH_CTRL_UID_ASYNCM_LH_MFCMSCL0_MIF_D_NRT, 0xFFFFFFFF, NULL, 0, 0},
{QCH_CTRL_UID_ASYNCM_LH_FSYS_MIF_D_NRT, 0xFFFFFFFF, NULL, 0, 0},
{QCH_CTRL_UID_ASYNCM_LH_ISP_MIF_D_NRT, 0xFFFFFFFF, NULL, 0, 0},
{QCH_CTRL_UID_ASYNCM_LH_ISP_MIF_D_RT, 0xFFFFFFFF, NULL, 0, 0},
{QCH_CTRL_UID_ASYNCM_LH_DISPAUD_MIF_D_RT, 0xFFFFFFFF, NULL, 0, 0},
{G3D_PLL_LOCK, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{G3D_PLL_CON0, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{G3D_PLL_CON1, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLK_CON_MUX_G3D_PLL, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLK_CON_MUX_CLKCMU_G3D_SWITCH_USER, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLK_CON_MUX_CLK_G3D, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLK_CON_DIV_CLK_G3D_BUS, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLK_CON_DIV_CLK_G3D_APB, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLK_STAT_MUX_G3D_PLL, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLK_STAT_MUX_CLKCMU_G3D_SWITCH_USER, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLK_STAT_MUX_CLK_G3D, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLK_ENABLE_CLK_G3D_OSCCLK, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLK_ENABLE_CLK_G3D_BUS, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLK_ENABLE_CLK_G3D_APB, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLK_ENABLE_CLK_G3D_BUS_SECURE_CFW_G3D, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLK_ENABLE_CLK_G3D_APB_SECURE_CFW_G3D, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLKOUT_CMU_G3D, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLKOUT_CMU_G3D_DIV_STAT, 0xFFFFFFFF, PMU_G3D_STATUS, 0, 0},
{CLK_ENABLE_CLK_PERI_OSCCLK, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_OSCCLK_SECURE_CHIPID, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_BUS0, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_BUS1, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_BUS_SECURE_CHIPID, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_BUS_SECURE_OTP_CON_TOP, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_ALIVE, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_TOP, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_UART_BTWIFIFM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_UART_DEBUG, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_UART_SENSOR, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_SPI_FRONTFROM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_SPI_REARFROM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_SPI_ESE, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_SPI_VOICEPROCESSOR, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_PERI_SPI_SENSORHUB, 0xFFFFFFFF, NULL, 0, 0},
{CLKOUT_CMU_PERI, 0xFFFFFFFF, NULL, 0, 0},
{CLKOUT_CMU_PERI_DIV_STAT, 0xFFFFFFFF, NULL, 0, 0},
{USB_PLL_LOCK, 0xFFFFFFFF, NULL, 0, 0},
{USB_PLL_CON0, 0xFFFFFFFF, NULL, 0, 0},
{USB_PLL_CON1, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_MUX_USB_PLL, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER, 0xFFFFFFFF, NULL, 0, 0},
{CLK_STAT_MUX_USB_PLL, 0xFFFFFFFF, NULL, 0, 0},
{CLK_STAT_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, 0xFFFFFFFF, NULL, 0, 0},
{CLK_STAT_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER, 0xFFFFFFFF, NULL, 0, 0},
{CLK_STAT_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_FSYS_OSCCLK, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_FSYS_BUS, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_FSYS_SECURE_RTIC, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_FSYS_SECURE_SSS, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_FSYS_SECURE_PDMA1, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_FSYS_MMC0, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_FSYS_MMC1, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_FSYS_MMC2, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_FSYS_UFSUNIPRO, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_FSYS_UFSUNIPRO_CFG, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLK_FSYS_USB20DRD_REFCLK, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKPHY_FSYS_USB20DRD_PHYCLOCK, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKPHY_FSYS_UFS_TX0_SYMBOL, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKPHY_FSYS_UFS_RX0_SYMBOL, 0xFFFFFFFF, NULL, 0, 0},
{CLKOUT_CMU_FSYS, 0xFFFFFFFF, NULL, 0, 0},
{CLKOUT_CMU_FSYS_DIV_STAT, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL_USER, 0xFFFFFFFF, PMU_MFCMSCL_STATUS, 0, 0},
{CLK_CON_MUX_CLKCMU_MFCMSCL_MFC_USER, 0xFFFFFFFF, PMU_MFCMSCL_STATUS, 0, 0},
{CLK_CON_DIV_CLK_MFCMSCL_APB, 0xFFFFFFFF, PMU_MFCMSCL_STATUS, 0, 0},
{CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL_USER, 0xFFFFFFFF, PMU_MFCMSCL_STATUS, 0, 0},
{CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC_USER, 0xFFFFFFFF, PMU_MFCMSCL_STATUS, 0, 0},
{CLK_ENABLE_CLK_MFCMSCL_OSCCLK, 0xFFFFFFFF, PMU_MFCMSCL_STATUS, 0, 0},
{CLK_ENABLE_CLK_MFCMSCL_MSCL, 0xFFFFFFFF, PMU_MFCMSCL_STATUS, 0, 0},
{CLK_ENABLE_CLK_MFCMSCL_MFC, 0xFFFFFFFF, PMU_MFCMSCL_STATUS, 0, 0},
{CLK_ENABLE_CLK_MFCMSCL_APB, 0xFFFFFFFF, PMU_MFCMSCL_STATUS, 0, 0},
{CLK_ENABLE_CLK_MFCMSCL_SECURE_CFW_MSCL, 0xFFFFFFFF, PMU_MFCMSCL_STATUS, 0, 0},
{CLKOUT_CMU_MFCMSCL, 0xFFFFFFFF, PMU_MFCMSCL_STATUS, 0, 0},
{CLKOUT_CMU_MFCMSCL_DIV_STAT, 0xFFFFFFFF, PMU_MFCMSCL_STATUS, 0, 0},
{DISP_PLL_LOCK, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{AUD_PLL_LOCK, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{DISP_PLL_CON0, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{DISP_PLL_CON1, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{AUD_PLL_CON0, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{AUD_PLL_CON1, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{AUD_PLL_CON2, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_CON_MUX_DISP_PLL, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_CON_MUX_AUD_PLL, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_CON_MUX_CLKCMU_DISPAUD_BUS_USER, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_CON_MUX_CLK_DISPAUD_DECON_INT_VCLK, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_CON_MUX_CLK_DISPAUD_DECON_INT_ECLK, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_CON_MUX_CLK_DISPAUD_MI2S, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_CON_DIV_CLK_DISPAUD_APB, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_CON_DIV_CLK_DISPAUD_DECON_INT_VCLK, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_CON_DIV_CLK_DISPAUD_DECON_INT_ECLK, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_CON_DIV_CLK_DISPAUD_MI2S, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_CON_DIV_CLK_DISPAUD_MIXER, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_STAT_MUX_DISP_PLL, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_STAT_MUX_AUD_PLL, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_STAT_MUX_CLKCMU_DISPAUD_BUS_USER, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_STAT_MUX_CLK_DISPAUD_DECON_INT_VCLK, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_STAT_MUX_CLK_DISPAUD_DECON_INT_ECLK, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_ENABLE_CLK_DISPAUD_OSCCLK, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_ENABLE_CLK_DISPAUD_BUS, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_ENABLE_CLK_DISPAUD_APB, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_ENABLE_CLK_DISPAUD_SECURE_CFW_DISP, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_ENABLE_CLK_DISPAUD_DECON_INT_VCLK, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_ENABLE_CLK_DISPAUD_DECON_INT_ECLK, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_ENABLE_CLK_DISPAUD_MI2S, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_ENABLE_CLK_DISPAUD_MIXER, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_ENABLE_CLKIO_DISPAUD_MIXER_SCLK_AP, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_BT, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_CP, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_FM, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLKOUT_CMU_DISPAUD, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{CLKOUT_CMU_DISPAUD_DIV_STAT, 0xFFFFFFFF, PMU_DISPAUD_STATUS, 0, 0},
{ISP_PLL_LOCK, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{ISP_PLL_CON0, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{ISP_PLL_CON1, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_CON_MUX_ISP_PLL, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_CON_MUX_CLKCMU_ISP_VRA_USER, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_CON_MUX_CLKCMU_ISP_CAM_USER, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_CON_MUX_CLKCMU_ISP_ISP_USER, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_CON_MUX_CLK_ISP_VRA, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_CON_MUX_CLK_ISP_CAM, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_CON_MUX_CLK_ISP_ISP, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_CON_MUX_CLK_ISP_ISPD, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_CON_DIV_CLK_ISP_APB, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_CON_DIV_CLK_ISP_CAM_HALF, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_STAT_MUX_ISP_PLL, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_STAT_MUX_CLKCMU_ISP_VRA_USER, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_STAT_MUX_CLKCMU_ISP_CAM_USER, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_STAT_MUX_CLKCMU_ISP_ISP_USER, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_STAT_MUX_CLK_ISP_VRA, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_STAT_MUX_CLK_ISP_ISP, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_STAT_MUX_CLK_ISP_CAM, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_STAT_MUX_CLK_ISP_ISPD, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_STAT_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_STAT_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_ENABLE_CLK_ISP_OSCCLK, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_ENABLE_CLK_ISP_VRA, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_ENABLE_CLK_ISP_APB, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_ENABLE_CLK_ISP_ISPD, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_ENABLE_CLK_ISP_CAM, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_ENABLE_CLK_ISP_CAM_HALF, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_ENABLE_CLK_ISP_ISP, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_ENABLE_CLKPHY_ISP_S_RXBYTECLKHS0_S4, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLK_ENABLE_CLKPHY_ISP_S_RXBYTECLKHS0_S4S, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLKOUT_CMU_ISP, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
{CLKOUT_CMU_ISP_DIV_STAT, 0xFFFFFFFF, PMU_ISP_STATUS, 0, 0},
};
static struct cmu_backup cmu_backup_topmux_list[] = {
{CLK_CON_MUX_CLKCMU_ISP_VRA, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_ISP_CAM, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_ISP_ISP, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_DISPAUD_BUS, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_MFCMSCL_MFC, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_FSYS_BUS, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_FSYS_MMC0, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_FSYS_MMC1, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_FSYS_MMC2, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_FSYS_USB20DRD_REFCLK, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_BUS, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_UART_BTWIFIFM, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_UART_DEBUG, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_UART_SENSOR, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_SPI_FRONTFROM, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_SPI_REARFROM, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_SPI_ESE, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_PERI_SPI_SENSORHUB, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_ISP_SENSOR0, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_ISP_SENSOR1, 0x00200000, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_ISP_SENSOR2, 0x00200000, NULL, 0, 0},
};
static struct cmu_backup cmu_backup_lpd_list[] = {
{CLK_CON_DIV_CLKCMU_DISPAUD_BUS, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_ECLK, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_DISPAUD_BUS, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK, 0xFFFFFFFF, NULL, 0, 0},
{MEM_PLL_CON0, 0xFFFFFFFF, NULL, 0, 0},
{BUS_PLL_CON0, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_MUX_MEM_PLL, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_MUX_BUS_PLL, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLK_MIF_BUSD, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_DIV_CLK_MIF_CCI, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLK_MIF_BUSD, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLK_MIF_CCI, 0xFFFFFFFF, NULL, 0, 0},
{CLK_CON_MUX_CLK_MIF_PHY_CLK2X, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_PERI_SPI_FRONTFROM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_PERI_SPI_REARFROM, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_PERI_SPI_ESE, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_PERI_SPI_VOICEPROCESSOR, 0xFFFFFFFF, NULL, 0, 0},
{CLK_ENABLE_CLKCMU_PERI_SPI_SENSORHUB, 0xFFFFFFFF, NULL, 0, 0},
{MIF_ROOTCLKEN, 0xFFFFFFFF, NULL, 0, 0},
};
static void save_cmusfr(int mode)
{
int i;
if (mode == SYS_SICD || mode == SYS_AFTR)
return;
for (i = 0; i < ARRAY_SIZE(cmu_backup_list); i++) {
cmu_backup_list[i].backup_valid = 0;
if (cmu_backup_list[i].power) {
if (pwrcal_getf(cmu_backup_list[i].power, 0, 0xF) != 0xF)
continue;
} else if (mode != SYS_SLEEP) {
continue;
}
cmu_backup_list[i].backup = pwrcal_readl(cmu_backup_list[i].sfr);
cmu_backup_list[i].backup_valid = 1;
}
}
static void restore_cmusfr(int mode)
{
int i;
if (mode == SYS_SICD || mode == SYS_AFTR)
return;
for (i = 0; i < ARRAY_SIZE(cmu_backup_list); i++) {
if (cmu_backup_list[i].backup_valid == 0)
continue;
if (cmu_backup_list[i].power)
if (pwrcal_getf(cmu_backup_list[i].power, 0, 0xF) != 0xF)
continue;
pwrcal_setf(cmu_backup_list[i].sfr, 0, cmu_backup_list[i].mask, cmu_backup_list[i].backup);
}
}
static void save_topmuxgate(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(cmu_backup_topmux_list); i++) {
cmu_backup_topmux_list[i].backup_valid = 0;
if (cmu_backup_topmux_list[i].power)
if (pwrcal_getf(cmu_backup_topmux_list[i].power, 0, 0xF) != 0xF)
continue;
cmu_backup_topmux_list[i].backup = pwrcal_readl(cmu_backup_topmux_list[i].sfr);
cmu_backup_topmux_list[i].backup_valid = 1;
}
}
static void restore_topmuxgate(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(cmu_backup_topmux_list); i++) {
if (cmu_backup_topmux_list[i].backup_valid == 0)
continue;
if (cmu_backup_topmux_list[i].power)
if (pwrcal_getf(cmu_backup_topmux_list[i].power, 0, 0xF) != 0xF)
continue;
pwrcal_setf(cmu_backup_topmux_list[i].sfr, 0, cmu_backup_topmux_list[i].mask, cmu_backup_topmux_list[i].backup);
}
}
static void save_lpd(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(cmu_backup_lpd_list); i++) {
cmu_backup_lpd_list[i].backup = pwrcal_readl(cmu_backup_lpd_list[i].sfr);
cmu_backup_lpd_list[i].backup_valid = 1;
}
}
static void restore_lpd(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(cmu_backup_lpd_list); i++) {
if (cmu_backup_lpd_list[i].backup_valid == 0)
continue;
pwrcal_setf(cmu_backup_lpd_list[i].sfr, 0, cmu_backup_lpd_list[i].mask, cmu_backup_lpd_list[i].backup);
}
}
static void topmux_enable(int mode)
{
if (mode != SYS_AFTR) {
pwrcal_setbit(CLK_CON_MUX_CLKCMU_ISP_VRA, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_ISP_CAM, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_ISP_ISP, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_DISPAUD_BUS, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_MFCMSCL_MFC, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_FSYS_BUS, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_FSYS_MMC0, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_FSYS_MMC1, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_FSYS_MMC2, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_FSYS_USB20DRD_REFCLK, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_PERI_BUS, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_PERI_UART_BTWIFIFM, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_PERI_UART_DEBUG, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_PERI_UART_SENSOR, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_PERI_SPI_FRONTFROM, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_PERI_SPI_REARFROM, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_PERI_SPI_ESE, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_PERI_SPI_SENSORHUB, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_ISP_SENSOR0, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_ISP_SENSOR1, 21, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_ISP_SENSOR2, 21, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_ISP_VRA, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_ISP_CAM, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_ISP_ISP, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_DISPAUD_BUS, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_DISPAUD_DECON_INT_VCLK, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_DISPAUD_DECON_INT_ECLK, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_MFCMSCL_MSCL, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_MFCMSCL_MFC, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_FSYS_BUS, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_FSYS_MMC0, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_FSYS_MMC1, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_FSYS_MMC2, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_FSYS_UFSUNIPRO, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_FSYS_UFSUNIPRO_CFG, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_FSYS_USB20DRD_REFCLK, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_BUS, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_UART_BTWIFIFM, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_UART_DEBUG, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_UART_SENSOR, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_SPI_FRONTFROM, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_SPI_REARFROM, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_SPI_ESE, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_SPI_VOICEPROCESSOR, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_SPI_SENSORHUB, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_ISP_SENSOR0, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_ISP_SENSOR1, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_ISP_SENSOR2, 0, 1);
}
}
static void syspwr_clock_config(int mode)
{
pwrcal_setbit(CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, 12, 0);
pwrcal_setbit(CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, 27, 1);
if (pwrcal_getf(PMU_DISPAUD_STATUS, 0, 0xf) == 0xf) {
pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 12, 0);
pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 12, 0);
pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 27, 1);
pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 27, 1);
}
if (pwrcal_getf(PMU_ISP_STATUS, 0, 0xf) == 0xf) {
pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 12, 0);
pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER, 12, 0);
pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 27, 1);
pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER, 27, 1);
}
if (mode == SYS_LPD) {
save_lpd();
pwrcal_setf(CLK_CON_DIV_CLKCMU_DISPAUD_BUS, 0, 0xF, 0x3);
pwrcal_setf(CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK, 0, 0xF, 0x3);
pwrcal_setf(CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_ECLK, 0, 0xF, 0x3);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_DISPAUD_BUS, 12, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK, 12, 1);
pwrcal_setbit(CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK, 12, 1);
pwrcal_setf(CLK_CON_DIV_CLK_MIF_BUSD, 0, 0xF, 0x1);
pwrcal_setf(CLK_CON_DIV_CLK_MIF_CCI, 0, 0xF, 0x1);
pwrcal_setf(CLK_CON_MUX_CLK_MIF_BUSD, 12, 0x3, 0x1);
pwrcal_setf(CLK_CON_MUX_CLK_MIF_CCI, 12, 0x3, 0x1);
pwrcal_setf(CLK_CON_MUX_CLK_MIF_PHY_CLK2X, 12, 0x1, 0x1);
pwrcal_setbit(CLK_CON_MUX_MEM_PLL, 12, 0);
pwrcal_setbit(CLK_CON_MUX_BUS_PLL, 12, 0);
pwrcal_setbit(MEM_PLL_CON0, 31, 0);
pwrcal_setbit(BUS_PLL_CON0, 31, 0);
pwrcal_setbit(MIF_ROOTCLKEN, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_SPI_FRONTFROM, 0, 0);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_SPI_REARFROM, 0, 0);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_SPI_ESE, 0, 0);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_SPI_VOICEPROCESSOR, 0, 0);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_SPI_SENSORHUB, 0, 0);
}
pwrcal_setbit(CLK_ENABLE_CLKCMU_FSYS_BUS, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_FSYS_MMC0, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_FSYS_MMC1, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_FSYS_MMC2, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_FSYS_UFSUNIPRO, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_FSYS_UFSUNIPRO_CFG, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_FSYS_USB20DRD_REFCLK, 0, 1);
}
static int syspwr_clkpwr_optimize(unsigned int power_mode)
{
disable_armidleclockdown();
return 0;
}
static void syspwr_set_additional_config(const enum sys_powerdown eMode)
{
pwrcal_setbit(PMU_WAKEUP_MASK, 30, 1);
pwrcal_setbit(PMU_WAKEUP_MASK_MIF, 30, 1);
}
static void syspwr_prepare(int mode)
{
save_cmusfr(mode);
save_topmuxgate();
topmux_enable(mode);
syspwr_clock_config(mode);
syspwr_clkpwr_optimize(mode);
set_pmu_sys_pwr_reg(mode);
syspwr_set_additional_config(mode);
set_pmu_central_seq(true);
switch (mode) {
case SYS_SICD:
set_pmu_central_seq_mif(true);
if (is_sicd_factory())
pwrcal_setbit(MIF_SFR_IGNORE_REQ_SYSCLK, 2, 1);
else
pwrcal_setbit(MIF_SFR_IGNORE_REQ_SYSCLK, 2, 0);
break;
case SYS_AFTR:
set_pmu_central_seq_mif(false);
break;
case SYS_STOP:
set_pmu_central_seq_mif(true);
break;
case SYS_LPD:
set_pmu_central_seq_mif(false);
break;
case SYS_SLEEP:
set_pmu_central_seq_mif(true);
break;
default:
break;
}
}
static void set_pmu_pad_retention_release(void)
{
pwrcal_writel(PMU_PAD_RETENTION_AUD_OPTION, PAD_INITIATE_WAKEUP);
pwrcal_writel(PMU_PAD_RETENTION_TOP_OPTION, PAD_INITIATE_WAKEUP);
pwrcal_writel(PMU_PAD_RETENTION_UART_OPTION, PAD_INITIATE_WAKEUP);
pwrcal_writel(PMU_PAD_RETENTION_MMC0_OPTION, PAD_INITIATE_WAKEUP);
pwrcal_writel(PMU_PAD_RETENTION_MMC1_OPTION, PAD_INITIATE_WAKEUP);
pwrcal_writel(PMU_PAD_RETENTION_MMC2_OPTION, PAD_INITIATE_WAKEUP);
pwrcal_writel(PMU_PAD_RETENTION_SPI_OPTION, PAD_INITIATE_WAKEUP);
}
static void syspwr_post(int mode)
{
if (mode != SYS_SICD)
set_pmu_pad_retention_release();
set_pmu_central_seq(false);
set_pmu_central_seq_mif(false);
pwrcal_writel(PMU_TOP_BUS_MIF_OPTION, 0);
pwrcal_setbit(PMU_WAKEUP_MASK, 30, 0);
enable_armidleclockdown();
if (mode == SYS_LPD)
restore_lpd();
restore_cmusfr(mode);
restore_topmuxgate();
}
static void syspwr_earlywakeup(int mode)
{
set_pmu_central_seq(false);
set_pmu_central_seq_mif(false);
enable_armidleclockdown();
pwrcal_writel(PMU_TOP_BUS_MIF_OPTION, 0);
pwrcal_setbit(PMU_WAKEUP_MASK, 30, 0);
restore_cmusfr(mode);
restore_topmuxgate();
}
struct cal_pm_ops cal_pm_ops = {
.pm_enter = syspwr_prepare,
.pm_exit = syspwr_post,
.pm_earlywakeup = syspwr_earlywakeup,
.pm_init = syspwr_init,
};
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