mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-01 08:38:52 +01:00
3718 lines
322 KiB
C
3718 lines
322 KiB
C
#include "../pwrcal.h"
|
|
#include "../pwrcal-clk.h"
|
|
#include "../pwrcal-env.h"
|
|
#include "../pwrcal-rae.h"
|
|
#include "../pwrcal-pmu.h"
|
|
#include "S5E8890-cmusfr.h"
|
|
#include "S5E8890-pmusfr.h"
|
|
#include "S5E8890-cmu.h"
|
|
|
|
#ifdef PWRCAL_TARGET_LINUX
|
|
#include <soc/samsung/ect_parser.h>
|
|
#else
|
|
#include <mach/ect_parser.h>
|
|
#endif
|
|
|
|
extern struct pwrcal_pll_ops pll141xx_ops;
|
|
extern struct pwrcal_pll_ops pll1419x_ops;
|
|
extern struct pwrcal_pll_ops pll1431x_ops;
|
|
|
|
struct pwrcal_clk *fixed_rate_type_list[NUM_OF_FIXED_RATE_TYPE];
|
|
struct pwrcal_clk *fixed_factor_type_list[NUM_OF_FIXED_FACTOR_TYPE];
|
|
struct pwrcal_clk *pll_type_list[NUM_OF_PLL_TYPE];
|
|
struct pwrcal_clk *mux_type_list[NUM_OF_MUX_TYPE];
|
|
struct pwrcal_clk *div_type_list[NUM_OF_DIV_TYPE];
|
|
struct pwrcal_clk *gate_type_list[NUM_OF_GATE_TYPE];
|
|
|
|
#define ADD_CLK_TO_LIST(to, x) to[clk_##x.clk.id & 0xFFF] = &(clk_##x.clk)
|
|
|
|
CLK_PLL(14160, MNGS_PLL, 0, MNGS_PLL_LOCK, MNGS_PLL_CON0, NULL, MNGS_MUX_MNGS_PLL, &pll141xx_ops);
|
|
CLK_PLL(14170, APOLLO_PLL, 0, APOLLO_PLL_LOCK, APOLLO_PLL_CON0, NULL, APOLLO_MUX_APOLLO_PLL, &pll141xx_ops);
|
|
CLK_PLL(14180, G3D_PLL, 0, G3D_PLL_LOCK, G3D_PLL_CON0, NULL, G3D_MUX_G3D_PLL_USER, &pll141xx_ops);
|
|
CLK_PLL(14190, MIF_PLL, 0, MIF0_PLL_LOCK, MIF_CLK_CTRL0, NULL, TOP_MUX_MIF_PLL, &pll1419x_ops);
|
|
CLK_PLL(14180, BUS0_PLL, 0, BUS0_PLL_LOCK, BUS0_PLL_CON0, NULL, TOP_MUX_BUS0_PLL, &pll141xx_ops);
|
|
CLK_PLL(14180, BUS1_PLL, 0, BUS1_PLL_LOCK, BUS1_PLL_CON0, NULL, TOP_MUX_BUS1_PLL, &pll141xx_ops);
|
|
CLK_PLL(14180, BUS2_PLL, 0, BUS2_PLL_LOCK, BUS2_PLL_CON0, NULL, TOP_MUX_BUS2_PLL, &pll141xx_ops);
|
|
CLK_PLL(14170, BUS3_PLL, 0, BUS3_PLL_LOCK, BUS3_PLL_CON0, NULL, TOP_MUX_BUS3_PLL, &pll141xx_ops);
|
|
CLK_PLL(14180, MFC_PLL, 0, MFC_PLL_LOCK, MFC_PLL_CON0, NULL, TOP_MUX_MFC_PLL, &pll141xx_ops);
|
|
CLK_PLL(14180, ISP_PLL, 0, ISP_PLL_LOCK, ISP_PLL_CON0, NULL, TOP_MUX_ISP_PLL, &pll141xx_ops);
|
|
CLK_PLL(14180, DISP_PLL, 0, DISP_PLL_LOCK, DISP_PLL_CON0, NULL, DISP0_MUX_DISP_PLL, &pll141xx_ops);
|
|
CLK_PLL(14310, AUD_PLL, 0, AUD_PLL_LOCK, AUD_PLL_CON0, NULL, AUD_MUX_AUD_PLL_USER, &pll1431x_ops);
|
|
CLK_PLL(14310, PCIE_PLL, 0, PCIE_PLL_LOCK, PCIE_PLL_CON0, NULL, FSYS1_MUX_PCIE_PLL, &pll1431x_ops);
|
|
|
|
FIXEDRATE(OSCCLK, 26 * MHZ, 0);
|
|
FIXEDRATE(OSCCLK_26M, 26 * MHZ, 0);
|
|
FIXEDRATE(SCAN_CLK_OSC, 26 * MHZ, 0);
|
|
FIXEDRATE(I_CP2AP_MIF_CLK, 400 * MHZ, 0);
|
|
FIXEDRATE(OSCCLK_PHY, 26 * MHZ, 0);
|
|
FIXEDRATE(SCLK_CP2AP_AUD_CLK, 30 * MHZ, 0);
|
|
FIXEDRATE(IOCLK_AUDIOCDCLK0, 30 * MHZ, 0);
|
|
FIXEDRATE(IOCLK_SLIMBUS_CLK, 30 * MHZ, 0);
|
|
FIXEDRATE(IOCLK_I2S_BCLK, 30 * MHZ, 0);
|
|
FIXEDRATE(RTC_CLKIN, 30 * MHZ, 0);
|
|
FIXEDRATE(IOCLK_SPI0, 30 * MHZ, 0);
|
|
FIXEDRATE(IOCLK_SPI1, 30 * MHZ, 0);
|
|
FIXEDRATE(IOCLK_SPI2, 30 * MHZ, 0);
|
|
FIXEDRATE(IOCLK_SPI3, 30 * MHZ, 0);
|
|
FIXEDRATE(IOCLK_SPI4, 30 * MHZ, 0);
|
|
FIXEDRATE(IOCLK_SPI5, 30 * MHZ, 0);
|
|
FIXEDRATE(IOCLK_SPI6, 30 * MHZ, 0);
|
|
FIXEDRATE(IOCLK_SPI7, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_USB30_12MOHCI, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY, 60 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY, 125 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_UFS_TX0_SYMBOL_PHY, 300 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_UFS_RX0_SYMBOL_PHY, 300 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_UFS_RX_PWM_CLK_PHY, 300 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_UFS_TX_PWM_CLK_PHY, 300 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_UFS_REFCLK_OUT_SOC_PHY, 26 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_USBHOST20_PHYCLOCK_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_USBHOST20_FREECLK_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_USBHOST20_CLK48MOHCI_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_UFS_LINK_SDCARD_TX1_SYMBOL_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_UFS_LINK_SDCARD_RX1_SYMBOL_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_UFS_LINK_SDCARD_RX_PWM_CLK_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_UFS_LINK_SDCARD_TX_PWM_CLK_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_UFS_LINK_SDCARD_REFCLK_OUT_SOC_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_PCIE_WIFI0_TX0_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_PCIE_WIFI0_RX0_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_PCIE_WIFI1_TX0_PHY, 250 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_PCIE_WIFI1_RX0_PHY, 250 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_PCIE_WIFI0_DIG_REFCLK_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_PCIE_WIFI1_DIG_REFCLK_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_MIPIDPHY0_BITCLKDIV2_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_MIPIDPHY1_BITCLKDIV2_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_MIPIDPHY2_BITCLKDIV2_PHY, 30 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, 300 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_HDMIPHY_TMDS_CLKO_PHY, 300 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, 20 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, 187.5 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_MIPIDPHY1_RXCLKESC0_PHY, 20 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_MIPIDPHY1_BITCLKDIV8_PHY, 187.5 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_MIPIDPHY2_RXCLKESC0_PHY, 20 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_MIPIDPHY2_BITCLKDIV8_PHY, 187.5 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_DPPHY_CH0_TXD_CLK_PHY, 270 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_DPPHY_CH1_TXD_CLK_PHY, 270 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_DPPHY_CH2_TXD_CLK_PHY, 270 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_DPPHY_CH3_TXD_CLK_PHY, 270 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_PHY, 0 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_RXBYTECLKHS0_CSIS0, 250 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_RXBYTECLKHS1_CSIS0, 250 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_RXBYTECLKHS2_CSIS0, 250 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_RXBYTECLKHS3_CSIS0, 250 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_RXBYTECLKHS0_CSIS1, 250 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_RXBYTECLKHS1_CSIS1, 250 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_RXBYTECLKHS0_CSIS2, 250 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_RXBYTECLKHS1_CSIS2, 250 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_RXBYTECLKHS2_CSIS2, 250 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_RXBYTECLKHS3_CSIS2, 250 * MHZ, 0);
|
|
FIXEDRATE(PHYCLK_RXBYTECLKHS0_CSIS3, 250 * MHZ, 0);
|
|
|
|
|
|
|
|
FIXEDFACTOR(TOP_FF_BUS0_PLL_DIV2, TOP_MUX_BUS0_PLL, 2, 0);
|
|
FIXEDFACTOR(TOP_FF_BUS1_PLL_DIV2, TOP_MUX_BUS1_PLL, 2, 0);
|
|
FIXEDFACTOR(TOP_FF_BUS2_PLL_DIV2, TOP_MUX_BUS2_PLL, 2, 0);
|
|
FIXEDFACTOR(TOP_FF_BUS3_PLL_DIV2, TOP_MUX_BUS3_PLL, 2, 0);
|
|
FIXEDFACTOR(TOP_FF_BUS3_PLL_DIV4, TOP_MUX_BUS3_PLL, 4, 0);
|
|
FIXEDFACTOR(TOP_FF_MFC_PLL_DIV2, TOP_MUX_MFC_PLL, 2, 0);
|
|
FIXEDFACTOR(TOP_FF_ISP_PLL_DIV2, TOP_MUX_ISP_PLL, 2, 0);
|
|
FIXEDFACTOR(MIF0_FF_ACLK_MIF_PLL_DIV2, MIF0_MUX_ACLK_MIF_PLL, 2, 0);
|
|
FIXEDFACTOR(MIF0_FF_ACLK_MIF_PLL_DIV4, MIF0_MUX_ACLK_MIF_PLL, 4, 0);
|
|
FIXEDFACTOR(MIF1_FF_ACLK_MIF_PLL_DIV2, MIF1_MUX_ACLK_MIF_PLL, 2, 0);
|
|
FIXEDFACTOR(MIF1_FF_ACLK_MIF_PLL_DIV4, MIF1_MUX_ACLK_MIF_PLL, 4, 0);
|
|
FIXEDFACTOR(MIF2_FF_ACLK_MIF_PLL_DIV2, MIF2_MUX_ACLK_MIF_PLL, 2, 0);
|
|
FIXEDFACTOR(MIF2_FF_ACLK_MIF_PLL_DIV4, MIF2_MUX_ACLK_MIF_PLL, 4, 0);
|
|
FIXEDFACTOR(MIF3_FF_ACLK_MIF_PLL_DIV2, MIF3_MUX_ACLK_MIF_PLL, 2, 0);
|
|
FIXEDFACTOR(MIF3_FF_ACLK_MIF_PLL_DIV4, MIF3_MUX_ACLK_MIF_PLL, 4, 0);
|
|
FIXEDFACTOR(U_DFI_CLK_GEN_MIF0, MIF0_MUX_ACLK_MIF_PLL, 4, 0);
|
|
FIXEDFACTOR(U_DFI_CLK_GEN_MIF1, MIF1_MUX_ACLK_MIF_PLL, 4, 0);
|
|
FIXEDFACTOR(U_DFI_CLK_GEN_MIF2, MIF2_MUX_ACLK_MIF_PLL, 4, 0);
|
|
FIXEDFACTOR(U_DFI_CLK_GEN_MIF3, MIF3_MUX_ACLK_MIF_PLL, 4, 0);
|
|
|
|
|
|
|
|
static struct pwrcal_clk *apollo_mux_apollo_pll_p[] = { CLK(OSCCLK), CLK(APOLLO_PLL) };
|
|
static struct pwrcal_clk *apollo_mux_bus_pll_apollo_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_BUS_PLL_APOLLO) };
|
|
static struct pwrcal_clk *apollo_mux_apollo_p[] = { CLK(APOLLO_MUX_APOLLO_PLL), CLK(APOLLO_MUX_BUS_PLL_APOLLO_USER) };
|
|
static struct pwrcal_clk *aud_mux_aud_pll_user_p[] = { CLK(OSCCLK), CLK(AUD_PLL) };
|
|
static struct pwrcal_clk *aud_mux_sclk_i2s_p[] = { CLK(AUD_MUX_CDCLK_AUD), CLK(IOCLK_AUDIOCDCLK0) };
|
|
static struct pwrcal_clk *aud_mux_sclk_pcm_p[] = { CLK(AUD_MUX_CDCLK_AUD), CLK(IOCLK_AUDIOCDCLK0) };
|
|
static struct pwrcal_clk *aud_mux_cp2ap_aud_clk_user_p[] = { CLK(OSCCLK), CLK(SCLK_CP2AP_AUD_CLK) };
|
|
static struct pwrcal_clk *aud_mux_aclk_ca5_p[] = { CLK(AUD_DIV_AUD_CA5), CLK(AUD_DIV_CP_CA5) };
|
|
static struct pwrcal_clk *aud_mux_cdclk_aud_p[] = { CLK(AUD_DIV_AUD_CDCLK), CLK(AUD_DIV_CP_CDCLK) };
|
|
static struct pwrcal_clk *bus0_mux_aclk_bus0_528_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_BUS0_528) };
|
|
static struct pwrcal_clk *bus0_mux_aclk_bus0_200_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_BUS0_200) };
|
|
static struct pwrcal_clk *bus0_mux_pclk_bus0_132_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_PCLK_BUS0_132) };
|
|
static struct pwrcal_clk *bus1_mux_aclk_bus1_528_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_BUS1_528) };
|
|
static struct pwrcal_clk *bus1_mux_pclk_bus1_132_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_PCLK_BUS1_132) };
|
|
static struct pwrcal_clk *cam0_mux_aclk_cam0_csis0_414_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CAM0_CSIS0_414) };
|
|
static struct pwrcal_clk *cam0_mux_aclk_cam0_csis1_168_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CAM0_CSIS1_168) };
|
|
static struct pwrcal_clk *cam0_mux_aclk_cam0_csis2_234_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CAM0_CSIS2_234) };
|
|
static struct pwrcal_clk *cam0_mux_aclk_cam0_csis3_132_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CAM0_CSIS3_132) };
|
|
static struct pwrcal_clk *cam0_mux_aclk_cam0_3aa0_414_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CAM0_3AA0_414) };
|
|
static struct pwrcal_clk *cam0_mux_aclk_cam0_3aa1_414_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CAM0_3AA1_414) };
|
|
static struct pwrcal_clk *cam0_mux_aclk_cam0_trex_528_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CAM0_TREX_528) };
|
|
static struct pwrcal_clk *cam0_mux_phyclk_rxbyteclkhs0_csis0_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_RXBYTECLKHS0_CSIS0) };
|
|
static struct pwrcal_clk *cam0_mux_phyclk_rxbyteclkhs1_csis0_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_RXBYTECLKHS1_CSIS0) };
|
|
static struct pwrcal_clk *cam0_mux_phyclk_rxbyteclkhs2_csis0_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_RXBYTECLKHS2_CSIS0) };
|
|
static struct pwrcal_clk *cam0_mux_phyclk_rxbyteclkhs3_csis0_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_RXBYTECLKHS3_CSIS0) };
|
|
static struct pwrcal_clk *cam0_mux_phyclk_rxbyteclkhs0_csis1_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_RXBYTECLKHS0_CSIS1) };
|
|
static struct pwrcal_clk *cam0_mux_phyclk_rxbyteclkhs1_csis1_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_RXBYTECLKHS1_CSIS1) };
|
|
static struct pwrcal_clk *cam1_mux_aclk_cam1_arm_672_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CAM1_ARM_672) };
|
|
static struct pwrcal_clk *cam1_mux_aclk_cam1_trex_vra_528_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CAM1_TREX_VRA_528) };
|
|
static struct pwrcal_clk *cam1_mux_aclk_cam1_trex_b_528_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CAM1_TREX_B_528) };
|
|
static struct pwrcal_clk *cam1_mux_aclk_cam1_bus_264_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CAM1_BUS_264) };
|
|
static struct pwrcal_clk *cam1_mux_aclk_cam1_peri_84_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CAM1_PERI_84) };
|
|
static struct pwrcal_clk *cam1_mux_aclk_cam1_csis2_414_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CAM1_CSIS2_414) };
|
|
static struct pwrcal_clk *cam1_mux_aclk_cam1_csis3_132_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CAM1_CSIS3_132) };
|
|
static struct pwrcal_clk *cam1_mux_aclk_cam1_scl_566_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CAM1_SCL_566) };
|
|
static struct pwrcal_clk *cam1_mux_sclk_cam1_isp_spi0_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_CAM1_ISP_SPI0) };
|
|
static struct pwrcal_clk *cam1_mux_sclk_cam1_isp_spi1_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_CAM1_ISP_SPI1) };
|
|
static struct pwrcal_clk *cam1_mux_sclk_cam1_isp_uart_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_CAM1_ISP_UART) };
|
|
static struct pwrcal_clk *cam1_mux_phyclk_rxbyteclkhs0_csis2_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_RXBYTECLKHS0_CSIS2) };
|
|
static struct pwrcal_clk *cam1_mux_phyclk_rxbyteclkhs1_csis2_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_RXBYTECLKHS1_CSIS2) };
|
|
static struct pwrcal_clk *cam1_mux_phyclk_rxbyteclkhs2_csis2_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_RXBYTECLKHS2_CSIS2) };
|
|
static struct pwrcal_clk *cam1_mux_phyclk_rxbyteclkhs3_csis2_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_RXBYTECLKHS3_CSIS2) };
|
|
static struct pwrcal_clk *cam1_mux_phyclk_rxbyteclkhs0_csis3_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_RXBYTECLKHS0_CSIS3) };
|
|
static struct pwrcal_clk *ccore_mux_aclk_ccore_800_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CCORE_800) };
|
|
static struct pwrcal_clk *ccore_mux_aclk_ccore_264_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CCORE_264) };
|
|
static struct pwrcal_clk *ccore_mux_aclk_ccore_g3d_800_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CCORE_G3D_800) };
|
|
static struct pwrcal_clk *ccore_mux_aclk_ccore_528_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CCORE_528) };
|
|
static struct pwrcal_clk *ccore_mux_aclk_ccore_132_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_CCORE_132) };
|
|
static struct pwrcal_clk *ccore_mux_pclk_ccore_66_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_PCLK_CCORE_66) };
|
|
static struct pwrcal_clk *disp0_mux_disp_pll_p[] = { CLK(OSCCLK), CLK(DISP_PLL) };
|
|
static struct pwrcal_clk *disp0_mux_aclk_disp0_0_400_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_DISP0_0_400) };
|
|
static struct pwrcal_clk *disp0_mux_aclk_disp0_1_400_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_DISP0_1_400) };
|
|
static struct pwrcal_clk *disp0_mux_sclk_disp0_decon0_eclk0_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_DISP0_DECON0_ECLK0) };
|
|
static struct pwrcal_clk *disp0_mux_sclk_disp0_decon0_vclk0_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_DISP0_DECON0_VCLK0) };
|
|
static struct pwrcal_clk *disp0_mux_sclk_disp0_decon0_vclk1_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_DISP0_DECON0_VCLK1) };
|
|
static struct pwrcal_clk *disp0_mux_sclk_disp0_hdmi_audio_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_DISP0_HDMI_AUDIO) };
|
|
static struct pwrcal_clk *disp0_mux_phyclk_hdmiphy_pixel_clko_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_HDMIPHY_PIXEL_CLKO_PHY) };
|
|
static struct pwrcal_clk *disp0_mux_phyclk_hdmiphy_tmds_clko_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_HDMIPHY_TMDS_CLKO_PHY) };
|
|
static struct pwrcal_clk *disp0_mux_phyclk_mipidphy0_rxclkesc0_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_MIPIDPHY0_RXCLKESC0_PHY) };
|
|
static struct pwrcal_clk *disp0_mux_phyclk_mipidphy0_bitclkdiv2_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_MIPIDPHY0_BITCLKDIV2_PHY) };
|
|
static struct pwrcal_clk *disp0_mux_phyclk_mipidphy0_bitclkdiv8_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY) };
|
|
static struct pwrcal_clk *disp0_mux_phyclk_mipidphy1_rxclkesc0_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_MIPIDPHY1_RXCLKESC0_PHY) };
|
|
static struct pwrcal_clk *disp0_mux_phyclk_mipidphy1_bitclkdiv2_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_MIPIDPHY1_BITCLKDIV2_PHY) };
|
|
static struct pwrcal_clk *disp0_mux_phyclk_mipidphy1_bitclkdiv8_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_MIPIDPHY1_BITCLKDIV8_PHY) };
|
|
static struct pwrcal_clk *disp0_mux_phyclk_mipidphy2_rxclkesc0_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_MIPIDPHY2_RXCLKESC0_PHY) };
|
|
static struct pwrcal_clk *disp0_mux_phyclk_mipidphy2_bitclkdiv2_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_MIPIDPHY2_BITCLKDIV2_PHY) };
|
|
static struct pwrcal_clk *disp0_mux_phyclk_mipidphy2_bitclkdiv8_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_MIPIDPHY2_BITCLKDIV8_PHY) };
|
|
static struct pwrcal_clk *disp0_mux_phyclk_dpphy_ch0_txd_clk_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_DPPHY_CH0_TXD_CLK_PHY) };
|
|
static struct pwrcal_clk *disp0_mux_phyclk_dpphy_ch1_txd_clk_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_DPPHY_CH1_TXD_CLK_PHY) };
|
|
static struct pwrcal_clk *disp0_mux_phyclk_dpphy_ch2_txd_clk_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_DPPHY_CH2_TXD_CLK_PHY) };
|
|
static struct pwrcal_clk *disp0_mux_phyclk_dpphy_ch3_txd_clk_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_DPPHY_CH3_TXD_CLK_PHY) };
|
|
static struct pwrcal_clk *disp0_mux_aclk_disp0_1_400_p[] = { CLK(DISP0_MUX_ACLK_DISP0_0_400_USER), CLK(DISP0_MUX_ACLK_DISP0_1_400_USER) };
|
|
static struct pwrcal_clk *disp0_mux_sclk_disp0_decon0_eclk0_p[] = { CLK(DISP0_MUX_SCLK_DISP0_DECON0_ECLK0_USER), CLK(DISP0_MUX_ACLK_DISP0_0_400_USER), CLK(DISP0_MUX_DISP_PLL), CLK(DISP0_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER), CLK(DISP0_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER), CLK(DISP0_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER) };
|
|
static struct pwrcal_clk *disp0_mux_sclk_disp0_decon0_vclk0_p[] = { CLK(DISP0_MUX_SCLK_DISP0_DECON0_VCLK0_USER), CLK(DISP0_MUX_ACLK_DISP0_0_400_USER), CLK(DISP0_MUX_DISP_PLL), CLK(DISP0_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER), CLK(DISP0_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER), CLK(DISP0_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER) };
|
|
static struct pwrcal_clk *disp0_mux_sclk_disp0_decon0_vclk1_p[] = { CLK(DISP0_MUX_SCLK_DISP0_DECON0_VCLK1_USER), CLK(DISP0_MUX_ACLK_DISP0_0_400_USER), CLK(DISP0_MUX_DISP_PLL), CLK(DISP0_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER), CLK(DISP0_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER), CLK(DISP0_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER) };
|
|
static struct pwrcal_clk *disp0_mux_sclk_disp0_hdmi_audio_p[] = { CLK(DISP0_MUX_PHYCLK_HDMIPHY_TMDS_CLKO_USER), CLK(DISP0_MUX_SCLK_DISP0_HDMI_AUDIO_USER) };
|
|
static struct pwrcal_clk *disp1_mux_aclk_disp1_0_400_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_DISP1_0_400) };
|
|
static struct pwrcal_clk *disp1_mux_aclk_disp1_1_400_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_DISP1_1_400) };
|
|
static struct pwrcal_clk *disp1_mux_sclk_disp1_decon1_eclk0_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_DISP1_DECON1_ECLK0) };
|
|
static struct pwrcal_clk *disp1_mux_sclk_disp1_decon1_eclk1_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_DISP1_DECON1_ECLK1) };
|
|
static struct pwrcal_clk *disp1_mux_sclk_disp1_600_user_p[] = { CLK(OSCCLK), CLK(DISP0_GATE_SCLK_DISP1_400) };
|
|
static struct pwrcal_clk *disp1_mux_phyclk_mipidphy0_bitclkdiv2_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_MIPIDPHY0_BITCLKDIV2_PHY) };
|
|
static struct pwrcal_clk *disp1_mux_phyclk_mipidphy1_bitclkdiv2_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_MIPIDPHY1_BITCLKDIV2_PHY) };
|
|
static struct pwrcal_clk *disp1_mux_phyclk_mipidphy2_bitclkdiv2_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_MIPIDPHY2_BITCLKDIV2_PHY) };
|
|
static struct pwrcal_clk *disp1_mux_phyclk_disp1_hdmiphy_pixel_clko_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_PHY) };
|
|
static struct pwrcal_clk *disp1_mux_aclk_disp1_1_400_p[] = { CLK(DISP1_MUX_ACLK_DISP1_0_400_USER), CLK(DISP1_MUX_ACLK_DISP1_1_400_USER) };
|
|
static struct pwrcal_clk *disp1_mux_sclk_disp1_decon1_eclk0_p[] = { CLK(DISP1_MUX_SCLK_DISP1_DECON1_ECLK0_USER), CLK(DISP1_MUX_ACLK_DISP1_0_400_USER), CLK(DISP1_MUX_SCLK_DISP1_600_USER), CLK(DISP1_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER), CLK(DISP1_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER), CLK(DISP1_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER) };
|
|
static struct pwrcal_clk *disp1_mux_sclk_disp1_decon1_eclk1_p[] = { CLK(DISP1_MUX_SCLK_DISP1_DECON1_ECLK1_USER), CLK(DISP1_MUX_ACLK_DISP1_0_400_USER), CLK(DISP1_MUX_SCLK_DISP1_600_USER) };
|
|
static struct pwrcal_clk *disp1_mux_sclk_decon1_eclk1_p[] = { CLK(DISP1_DIV_SCLK_DECON1_ECLK1), CLK(DISP1_MUX_PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_USER) };
|
|
static struct pwrcal_clk *fsys0_mux_aclk_fsys0_200_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_FSYS0_200) };
|
|
static struct pwrcal_clk *fsys0_mux_sclk_fsys0_usbdrd30_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_FSYS0_USBDRD30) };
|
|
static struct pwrcal_clk *fsys0_mux_sclk_fsys0_mmc0_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_FSYS0_MMC0) };
|
|
static struct pwrcal_clk *fsys0_mux_sclk_fsys0_ufsunipro_embedded_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_FSYS0_UFSUNIPRO20) };
|
|
static struct pwrcal_clk *fsys0_mux_sclk_fsys0_24m_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_FSYS0_PHY_24M) };
|
|
static struct pwrcal_clk *fsys0_mux_sclk_fsys0_ufsunipro_embedded_cfg_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_FSYS0_UFSUNIPRO_CFG) };
|
|
static struct pwrcal_clk *fsys0_mux_phyclk_usbdrd30_udrd30_phyclock_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY) };
|
|
static struct pwrcal_clk *fsys0_mux_phyclk_usbdrd30_udrd30_pipe_pclk_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY) };
|
|
static struct pwrcal_clk *fsys0_mux_phyclk_ufs_tx0_symbol_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_UFS_TX0_SYMBOL_PHY) };
|
|
static struct pwrcal_clk *fsys0_mux_phyclk_ufs_rx0_symbol_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_UFS_RX0_SYMBOL_PHY) };
|
|
static struct pwrcal_clk *fsys0_mux_phyclk_usbhost20_phyclock_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_USBHOST20_PHYCLOCK_PHY) };
|
|
static struct pwrcal_clk *fsys0_mux_phyclk_usbhost20phy_ref_clk_p[] = { CLK(FSYS0_MUX_SCLK_FSYS0_24M_USER), CLK(PHYCLK_USB30_12MOHCI) };
|
|
static struct pwrcal_clk *fsys1_mux_aclk_fsys1_200_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_FSYS1_200) };
|
|
static struct pwrcal_clk *fsys1_mux_sclk_fsys1_mmc2_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_FSYS1_MMC2) };
|
|
static struct pwrcal_clk *fsys1_mux_sclk_fsys1_ufsunipro_sdcard_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_FSYS1_UFSUNIPRO20) };
|
|
static struct pwrcal_clk *fsys1_mux_sclk_fsys1_ufsunipro_sdcard_cfg_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_FSYS1_UFSUNIPRO_CFG) };
|
|
static struct pwrcal_clk *fsys1_mux_sclk_fsys1_pcie_phy_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_FSYS1_PCIE_PHY) };
|
|
static struct pwrcal_clk *fsys1_mux_pcie_pll_p[] = { CLK(OSCCLK), CLK(PCIE_PLL) };
|
|
static struct pwrcal_clk *fsys1_mux_phyclk_ufs_link_sdcard_tx0_symbol_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_PHY) };
|
|
static struct pwrcal_clk *fsys1_mux_phyclk_ufs_link_sdcard_rx0_symbol_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_PHY) };
|
|
static struct pwrcal_clk *fsys1_mux_phyclk_pcie_wifi0_tx0_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_PCIE_WIFI0_TX0_PHY) };
|
|
static struct pwrcal_clk *fsys1_mux_phyclk_pcie_wifi0_rx0_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_PCIE_WIFI0_RX0_PHY) };
|
|
static struct pwrcal_clk *fsys1_mux_phyclk_pcie_wifi1_tx0_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_PCIE_WIFI1_TX0_PHY) };
|
|
static struct pwrcal_clk *fsys1_mux_phyclk_pcie_wifi1_rx0_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_PCIE_WIFI1_RX0_PHY) };
|
|
static struct pwrcal_clk *fsys1_mux_phyclk_pcie_wifi0_dig_refclk_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_PCIE_WIFI0_DIG_REFCLK_PHY) };
|
|
static struct pwrcal_clk *fsys1_mux_phyclk_pcie_wifi1_dig_refclk_user_p[] = { CLK(OSCCLK), CLK(PHYCLK_PCIE_WIFI1_DIG_REFCLK_PHY) };
|
|
static struct pwrcal_clk *g3d_mux_g3d_pll_user_p[] = { CLK(OSCCLK), CLK(G3D_PLL) };
|
|
static struct pwrcal_clk *g3d_mux_bus_pll_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_BUS_PLL_G3D) };
|
|
static struct pwrcal_clk *g3d_mux_g3d_p[] = { CLK(G3D_MUX_G3D_PLL_USER), CLK(G3D_MUX_BUS_PLL_USER) };
|
|
static struct pwrcal_clk *imem_mux_aclk_imem_266_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_IMEM_266) };
|
|
static struct pwrcal_clk *imem_mux_aclk_imem_200_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_IMEM_200) };
|
|
static struct pwrcal_clk *imem_mux_aclk_imem_100_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_IMEM_100) };
|
|
static struct pwrcal_clk *isp0_mux_aclk_isp0_528_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_ISP0_ISP0_528) };
|
|
static struct pwrcal_clk *isp0_mux_aclk_isp0_tpu_400_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_ISP0_TPU_400) };
|
|
static struct pwrcal_clk *isp0_mux_aclk_isp0_trex_528_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_ISP0_TREX_528) };
|
|
static struct pwrcal_clk *isp0_mux_aclk_isp0_pxl_asbs_is_c_from_is_d_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D) };
|
|
static struct pwrcal_clk *isp1_mux_aclk_isp1_468_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_ISP1_ISP1_468) };
|
|
static struct pwrcal_clk *mfc_mux_aclk_mfc_600_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_MFC_600) };
|
|
static struct pwrcal_clk *mif0_mux_mif_pll_p[] = { CLK(OSCCLK), CLK(MIF_PLL) };
|
|
static struct pwrcal_clk *mif0_mux_bus_pll_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_BUS_PLL_MIF) };
|
|
static struct pwrcal_clk *mif0_mux_aclk_mif_pll_p[] = { CLK(MIF0_MUX_MIF_PLL), CLK(MIF0_MUX_BUS_PLL_USER) };
|
|
static struct pwrcal_clk *mif0_mux_pclk_mif_p[] = { CLK(MIF0_MUX_ACLK_MIF_PLL), CLK(MIF0_FF_ACLK_MIF_PLL_DIV2), CLK(MIF0_FF_ACLK_MIF_PLL_DIV4) };
|
|
static struct pwrcal_clk *mif0_mux_sclk_hpm_mif_p[] = { CLK(MIF0_MUX_ACLK_MIF_PLL), CLK(MIF0_FF_ACLK_MIF_PLL_DIV2), CLK(MIF0_FF_ACLK_MIF_PLL_DIV4) };
|
|
static struct pwrcal_clk *mif0_mux_pclk_smc_p[] = { CLK(MIF0_MUX_ACLK_MIF_PLL), CLK(MIF0_FF_ACLK_MIF_PLL_DIV2), CLK(MIF0_FF_ACLK_MIF_PLL_DIV4), CLK(U_DFI_CLK_GEN_MIF0) };
|
|
static struct pwrcal_clk *mif1_mux_mif_pll_p[] = { CLK(OSCCLK), CLK(MIF_PLL) };
|
|
static struct pwrcal_clk *mif1_mux_bus_pll_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_BUS_PLL_MIF) };
|
|
static struct pwrcal_clk *mif1_mux_aclk_mif_pll_p[] = { CLK(MIF1_MUX_MIF_PLL), CLK(MIF1_MUX_BUS_PLL_USER) };
|
|
static struct pwrcal_clk *mif1_mux_pclk_mif_p[] = { CLK(MIF1_MUX_ACLK_MIF_PLL), CLK(MIF1_FF_ACLK_MIF_PLL_DIV2), CLK(MIF1_FF_ACLK_MIF_PLL_DIV4) };
|
|
static struct pwrcal_clk *mif1_mux_sclk_hpm_mif_p[] = { CLK(MIF1_MUX_ACLK_MIF_PLL), CLK(MIF1_FF_ACLK_MIF_PLL_DIV2), CLK(MIF1_FF_ACLK_MIF_PLL_DIV4) };
|
|
static struct pwrcal_clk *mif1_mux_pclk_smc_p[] = { CLK(MIF1_MUX_ACLK_MIF_PLL), CLK(MIF1_FF_ACLK_MIF_PLL_DIV2), CLK(MIF1_FF_ACLK_MIF_PLL_DIV4), CLK(U_DFI_CLK_GEN_MIF1) };
|
|
static struct pwrcal_clk *mif2_mux_mif_pll_p[] = { CLK(OSCCLK), CLK(MIF_PLL) };
|
|
static struct pwrcal_clk *mif2_mux_bus_pll_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_BUS_PLL_MIF) };
|
|
static struct pwrcal_clk *mif2_mux_aclk_mif_pll_p[] = { CLK(MIF2_MUX_MIF_PLL), CLK(MIF2_MUX_BUS_PLL_USER) };
|
|
static struct pwrcal_clk *mif2_mux_pclk_mif_p[] = { CLK(MIF2_MUX_ACLK_MIF_PLL), CLK(MIF2_FF_ACLK_MIF_PLL_DIV2), CLK(MIF2_FF_ACLK_MIF_PLL_DIV4) };
|
|
static struct pwrcal_clk *mif2_mux_sclk_hpm_mif_p[] = { CLK(MIF2_MUX_ACLK_MIF_PLL), CLK(MIF2_FF_ACLK_MIF_PLL_DIV2), CLK(MIF2_FF_ACLK_MIF_PLL_DIV4) };
|
|
static struct pwrcal_clk *mif2_mux_pclk_smc_p[] = { CLK(MIF2_MUX_ACLK_MIF_PLL), CLK(MIF2_FF_ACLK_MIF_PLL_DIV2), CLK(MIF2_FF_ACLK_MIF_PLL_DIV4), CLK(U_DFI_CLK_GEN_MIF2) };
|
|
static struct pwrcal_clk *mif3_mux_mif_pll_p[] = { CLK(OSCCLK), CLK(MIF_PLL) };
|
|
static struct pwrcal_clk *mif3_mux_bus_pll_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_BUS_PLL_MIF) };
|
|
static struct pwrcal_clk *mif3_mux_aclk_mif_pll_p[] = { CLK(MIF3_MUX_MIF_PLL), CLK(MIF3_MUX_BUS_PLL_USER) };
|
|
static struct pwrcal_clk *mif3_mux_pclk_mif_p[] = { CLK(MIF3_MUX_ACLK_MIF_PLL), CLK(MIF3_FF_ACLK_MIF_PLL_DIV2), CLK(MIF3_FF_ACLK_MIF_PLL_DIV4) };
|
|
static struct pwrcal_clk *mif3_mux_sclk_hpm_mif_p[] = { CLK(MIF3_MUX_ACLK_MIF_PLL), CLK(MIF3_FF_ACLK_MIF_PLL_DIV2), CLK(MIF3_FF_ACLK_MIF_PLL_DIV4) };
|
|
static struct pwrcal_clk *mif3_mux_pclk_smc_p[] = { CLK(MIF3_MUX_ACLK_MIF_PLL), CLK(MIF3_FF_ACLK_MIF_PLL_DIV2), CLK(MIF3_FF_ACLK_MIF_PLL_DIV4), CLK(U_DFI_CLK_GEN_MIF3) };
|
|
static struct pwrcal_clk *mngs_mux_mngs_pll_p[] = { CLK(OSCCLK), CLK(MNGS_PLL) };
|
|
static struct pwrcal_clk *mngs_mux_bus_pll_mngs_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_BUS_PLL_MNGS) };
|
|
static struct pwrcal_clk *mngs_mux_mngs_p[] = { CLK(MNGS_MUX_MNGS_PLL), CLK(MNGS_MUX_BUS_PLL_MNGS_USER) };
|
|
static struct pwrcal_clk *mscl_mux_aclk_mscl0_528_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_MSCL0_528) };
|
|
static struct pwrcal_clk *mscl_mux_aclk_mscl1_528_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_MSCL1_528) };
|
|
static struct pwrcal_clk *mscl_mux_aclk_mscl1_528_p[] = { CLK(MSCL_MUX_ACLK_MSCL0_528_USER), CLK(MSCL_MUX_ACLK_MSCL1_528_USER) };
|
|
static struct pwrcal_clk *peric0_mux_aclk_peric0_66_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_PERIC0_66) };
|
|
static struct pwrcal_clk *peric0_mux_sclk_uart0_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_PERIC0_UART0) };
|
|
static struct pwrcal_clk *peric1_mux_aclk_peric1_66_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_PERIC1_66) };
|
|
static struct pwrcal_clk *peric1_mux_sclk_spi0_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_PERIC1_SPI0) };
|
|
static struct pwrcal_clk *peric1_mux_sclk_spi1_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_PERIC1_SPI1) };
|
|
static struct pwrcal_clk *peric1_mux_sclk_spi2_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_PERIC1_SPI2) };
|
|
static struct pwrcal_clk *peric1_mux_sclk_spi3_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_PERIC1_SPI3) };
|
|
static struct pwrcal_clk *peric1_mux_sclk_spi4_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_PERIC1_SPI4) };
|
|
static struct pwrcal_clk *peric1_mux_sclk_spi5_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_PERIC1_SPI5) };
|
|
static struct pwrcal_clk *peric1_mux_sclk_spi6_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_PERIC1_SPI6) };
|
|
static struct pwrcal_clk *peric1_mux_sclk_spi7_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_PERIC1_SPI7) };
|
|
static struct pwrcal_clk *peric1_mux_sclk_uart1_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_PERIC1_UART1) };
|
|
static struct pwrcal_clk *peric1_mux_sclk_uart2_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_PERIC1_UART2) };
|
|
static struct pwrcal_clk *peric1_mux_sclk_uart3_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_PERIC1_UART3) };
|
|
static struct pwrcal_clk *peric1_mux_sclk_uart4_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_PERIC1_UART4) };
|
|
static struct pwrcal_clk *peric1_mux_sclk_uart5_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_SCLK_PERIC1_UART5) };
|
|
static struct pwrcal_clk *peris_mux_aclk_peris_66_user_p[] = { CLK(OSCCLK), CLK(TOP_GATE_ACLK_PERIS_66) };
|
|
static struct pwrcal_clk *top_mux_bus0_pll_p[] = { CLK(OSCCLK), CLK(BUS0_PLL) };
|
|
static struct pwrcal_clk *top_mux_bus1_pll_p[] = { CLK(OSCCLK), CLK(BUS1_PLL) };
|
|
static struct pwrcal_clk *top_mux_bus2_pll_p[] = { CLK(OSCCLK), CLK(BUS2_PLL) };
|
|
static struct pwrcal_clk *top_mux_bus3_pll_p[] = { CLK(OSCCLK), CLK(BUS3_PLL) };
|
|
static struct pwrcal_clk *top_mux_mfc_pll_p[] = { CLK(OSCCLK), CLK(MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_isp_pll_p[] = { CLK(OSCCLK), CLK(ISP_PLL) };
|
|
static struct pwrcal_clk *top_mux_aud_pll_p[] = { CLK(OSCCLK), CLK(AUD_PLL) };
|
|
static struct pwrcal_clk *top_mux_g3d_pll_p[] = { CLK(OSCCLK), CLK(G3D_PLL) };
|
|
static struct pwrcal_clk *top_mux_sclk_bus0_pll_p[] = { CLK(TOP_MUX_BUS0_PLL), CLK(TOP_FF_BUS0_PLL_DIV2) };
|
|
static struct pwrcal_clk *top_mux_sclk_bus1_pll_p[] = { CLK(TOP_MUX_BUS1_PLL), CLK(TOP_FF_BUS1_PLL_DIV2) };
|
|
static struct pwrcal_clk *top_mux_sclk_bus2_pll_p[] = { CLK(TOP_MUX_BUS2_PLL), CLK(TOP_FF_BUS2_PLL_DIV2) };
|
|
static struct pwrcal_clk *top_mux_sclk_bus3_pll_p[] = { CLK(TOP_MUX_BUS3_PLL), CLK(TOP_FF_BUS3_PLL_DIV2), CLK(TOP_FF_BUS3_PLL_DIV4) };
|
|
static struct pwrcal_clk *top_mux_sclk_mfc_pll_p[] = { CLK(TOP_MUX_MFC_PLL), CLK(TOP_FF_MFC_PLL_DIV2) };
|
|
static struct pwrcal_clk *top_mux_sclk_isp_pll_p[] = { CLK(TOP_MUX_ISP_PLL), CLK(TOP_FF_ISP_PLL_DIV2) };
|
|
static struct pwrcal_clk *top_mux_aclk_ccore_800_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_BUS1_PLL), CLK(TOP_MUX_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_FF_BUS3_PLL_DIV2), CLK(TOP_MUX_SCLK_MFC_PLL), CLK(TOP_MUX_ISP_PLL), CLK(TOP_MUX_CP2AP_MIF_CLK_USER) };
|
|
static struct pwrcal_clk *top_mux_aclk_ccore_264_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK), CLK(TOP_MUX_CP2AP_MIF_CLK_USER) };
|
|
static struct pwrcal_clk *top_mux_aclk_ccore_g3d_800_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_BUS1_PLL), CLK(TOP_MUX_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_FF_BUS3_PLL_DIV2), CLK(TOP_MUX_SCLK_MFC_PLL), CLK(TOP_MUX_ISP_PLL), CLK(TOP_MUX_CP2AP_MIF_CLK_USER) };
|
|
static struct pwrcal_clk *top_mux_aclk_ccore_528_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_CP2AP_MIF_CLK_USER) };
|
|
static struct pwrcal_clk *top_mux_aclk_ccore_132_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK), CLK(TOP_MUX_CP2AP_MIF_CLK_USER) };
|
|
static struct pwrcal_clk *top_mux_pclk_ccore_66_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK), CLK(TOP_MUX_CP2AP_MIF_CLK_USER) };
|
|
static struct pwrcal_clk *top_mux_aclk_bus0_528_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_bus0_200_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_pclk_bus0_132_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(OSCCLK), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_aclk_bus1_528_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL) };
|
|
static struct pwrcal_clk *top_mux_pclk_bus1_132_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(OSCCLK), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_aclk_disp0_0_400_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_disp0_1_400_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_disp1_0_400_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_disp1_1_400_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_mfc_600_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_mscl0_528_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_mscl1_528_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_imem_266_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_aclk_imem_200_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_aclk_imem_100_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(OSCCLK), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_aclk_fsys0_200_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_aclk_fsys1_200_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_aclk_peris_66_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(OSCCLK), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_aclk_peric0_66_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(OSCCLK), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_aclk_peric1_66_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(OSCCLK), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_aclk_isp0_isp0_528_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_isp0_tpu_400_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_isp0_trex_528_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_isp0_pxl_asbs_is_c_from_is_d_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_isp1_isp1_468_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_cam0_csis0_414_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_cam0_csis1_168_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_cam0_csis2_234_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_cam0_3aa0_414_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_cam0_3aa1_414_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_cam0_csis3_132_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_cam0_trex_528_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_cam1_arm_672_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL), CLK(TOP_MUX_BUS2_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_cam1_trex_vra_528_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_cam1_trex_b_528_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_cam1_bus_264_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_cam1_peri_84_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_cam1_csis2_414_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_cam1_csis3_132_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_cam1_scl_566_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_SCLK_ISP_PLL), CLK(TOP_MUX_SCLK_MFC_PLL) };
|
|
static struct pwrcal_clk *top_mux_sclk_disp0_decon0_eclk0_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(OSCCLK), CLK(TOP_MUX_BUS2_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_disp0_decon0_vclk0_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(OSCCLK), CLK(TOP_MUX_BUS2_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_disp0_decon0_vclk1_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(OSCCLK), CLK(TOP_MUX_BUS2_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_disp0_hdmi_audio_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_AUD_PLL) };
|
|
static struct pwrcal_clk *top_mux_sclk_disp1_decon1_eclk0_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_BUS2_PLL) };
|
|
static struct pwrcal_clk *top_mux_sclk_disp1_decon1_eclk1_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_BUS2_PLL) };
|
|
static struct pwrcal_clk *top_mux_sclk_fsys0_usbdrd30_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_fsys0_mmc0_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_FF_BUS3_PLL_DIV2) };
|
|
static struct pwrcal_clk *top_mux_sclk_fsys0_ufsunipro20_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL) };
|
|
static struct pwrcal_clk *top_mux_sclk_fsys0_phy_24m_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_fsys0_ufsunipro_cfg_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(OSCCLK), CLK(TOP_MUX_SCLK_BUS2_PLL) };
|
|
static struct pwrcal_clk *top_mux_sclk_fsys1_mmc2_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_FF_BUS3_PLL_DIV2) };
|
|
static struct pwrcal_clk *top_mux_sclk_fsys1_ufsunipro20_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL) };
|
|
static struct pwrcal_clk *top_mux_sclk_fsys1_pcie_phy_p[] = { CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_fsys1_ufsunipro_cfg_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(OSCCLK), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_peric0_uart0_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_peric1_spi0_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_peric1_spi1_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_peric1_spi2_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_peric1_spi3_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_peric1_spi4_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_peric1_spi5_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_peric1_spi6_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_peric1_spi7_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_peric1_uart1_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_peric1_uart2_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_peric1_uart3_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_peric1_uart4_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_peric1_uart5_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_cam1_isp_spi0_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_cam1_isp_spi1_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_cam1_isp_uart_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL) };
|
|
static struct pwrcal_clk *top_mux_sclk_ap2cp_mif_pll_out_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_pscdc_400_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS3_PLL), CLK(TOP_MUX_CP2AP_MIF_CLK_USER) };
|
|
static struct pwrcal_clk *top_mux_sclk_bus_pll_mngs_p[] = { CLK(TOP_MUX_BUS0_PLL), CLK(TOP_MUX_BUS1_PLL), CLK(TOP_MUX_BUS2_PLL), CLK(TOP_FF_BUS3_PLL_DIV2) };
|
|
static struct pwrcal_clk *top_mux_sclk_bus_pll_apollo_p[] = { CLK(TOP_MUX_BUS0_PLL), CLK(TOP_MUX_BUS1_PLL), CLK(TOP_MUX_BUS2_PLL), CLK(TOP_FF_BUS3_PLL_DIV2) };
|
|
static struct pwrcal_clk *top_mux_sclk_bus_pll_mif_p[] = { CLK(TOP_MUX_BUS0_PLL), CLK(TOP_MUX_BUS1_PLL), CLK(TOP_MUX_BUS2_PLL), CLK(TOP_MUX_BUS3_PLL), CLK(TOP_FF_BUS3_PLL_DIV2), CLK(TOP_MUX_CP2AP_MIF_CLK_USER) };
|
|
static struct pwrcal_clk *top_mux_sclk_bus_pll_g3d_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_BUS1_PLL), CLK(TOP_MUX_BUS2_PLL), CLK(TOP_FF_BUS3_PLL_DIV2), CLK(TOP_MUX_G3D_PLL) };
|
|
static struct pwrcal_clk *top_mux_sclk_isp_sensor0_p[] = { CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_isp_sensor1_p[] = { CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_isp_sensor2_p[] = { CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_isp_sensor3_p[] = { CLK(OSCCLK) };
|
|
static struct pwrcal_clk *top_mux_sclk_promise_int_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL) };
|
|
static struct pwrcal_clk *top_mux_sclk_promise_disp_p[] = { CLK(TOP_MUX_SCLK_BUS0_PLL), CLK(TOP_MUX_SCLK_BUS1_PLL), CLK(TOP_MUX_SCLK_BUS2_PLL) };
|
|
static struct pwrcal_clk *top_mux_cp2ap_mif_clk_user_p[] = { CLK(OSCCLK), CLK(I_CP2AP_MIF_CLK) };
|
|
static struct pwrcal_clk *top_mux_mif_pll_p[] = { CLK(OSCCLK), CLK(MIF_PLL) };
|
|
static struct pwrcal_clk *top_mux_bus_pll_mif_p[] = { CLK(OSCCLK), CLK(TOP_MUX_SCLK_BUS1_PLL) };
|
|
static struct pwrcal_clk *top_mux_aclk_mif_pll_p[] = { CLK(TOP_MUX_MIF_PLL), CLK(TOP_MUX_BUS_PLL_MIF) };
|
|
|
|
|
|
|
|
|
|
CLK_MUX(APOLLO_MUX_APOLLO_PLL, apollo_mux_apollo_pll_p, CLK_CON_MUX_APOLLO_PLL, 12, 1, CLK_STAT_MUX_APOLLO_PLL, 12, 2, CLK_CON_MUX_APOLLO_PLL, 21, 0);
|
|
CLK_MUX(APOLLO_MUX_BUS_PLL_APOLLO_USER, apollo_mux_bus_pll_apollo_user_p, CLK_CON_MUX_BUS_PLL_APOLLO_USER, 12, 1, CLK_STAT_MUX_BUS_PLL_APOLLO_USER, 12, 2, CLK_CON_MUX_BUS_PLL_APOLLO_USER, 21, 0);
|
|
CLK_MUX(APOLLO_MUX_APOLLO, apollo_mux_apollo_p, CLK_CON_MUX_APOLLO, 12, 1, CLK_STAT_MUX_APOLLO, 12, 2, CLK_CON_MUX_APOLLO, 21, 0);
|
|
CLK_MUX(AUD_MUX_AUD_PLL_USER, aud_mux_aud_pll_user_p, CLK_CON_MUX_AUD_PLL_USER, 12, 1, CLK_STAT_MUX_AUD_PLL_USER, 12, 2, CLK_CON_MUX_AUD_PLL_USER, 21, 0);
|
|
CLK_MUX(AUD_MUX_SCLK_I2S, aud_mux_sclk_i2s_p, CLK_CON_MUX_SCLK_I2S, 12, 1, NULL, 12, 1, CLK_CON_MUX_SCLK_I2S, 21, 0);
|
|
CLK_MUX(AUD_MUX_SCLK_PCM, aud_mux_sclk_pcm_p, CLK_CON_MUX_SCLK_PCM, 12, 1, NULL, 12, 1, CLK_CON_MUX_SCLK_PCM, 21, 0);
|
|
CLK_MUX(AUD_MUX_CP2AP_AUD_CLK_USER, aud_mux_cp2ap_aud_clk_user_p, CLK_CON_MUX_CP2AP_AUD_CLK_USER, 12, 1, CLK_STAT_MUX_CP2AP_AUD_CLK_USER, 12, 2, CLK_CON_MUX_CP2AP_AUD_CLK_USER, 21, 0);
|
|
CLK_MUX(AUD_MUX_ACLK_CA5, aud_mux_aclk_ca5_p, CLK_CON_MUX_ACLK_CA5, 12, 1, CLK_STAT_MUX_ACLK_CA5, 12, 2, CLK_CON_MUX_ACLK_CA5, 21, 0);
|
|
CLK_MUX(AUD_MUX_CDCLK_AUD, aud_mux_cdclk_aud_p, CLK_CON_MUX_CDCLK_AUD, 12, 1, CLK_STAT_MUX_CDCLK_AUD, 12, 2, CLK_CON_MUX_CDCLK_AUD, 21, 0);
|
|
CLK_MUX(BUS0_MUX_ACLK_BUS0_528_USER, bus0_mux_aclk_bus0_528_user_p, CLK_CON_MUX_ACLK_BUS0_528_USER, 12, 1, CLK_STAT_MUX_ACLK_BUS0_528_USER, 12, 2, CLK_CON_MUX_ACLK_BUS0_528_USER, 21, 0);
|
|
CLK_MUX(BUS0_MUX_ACLK_BUS0_200_USER, bus0_mux_aclk_bus0_200_user_p, CLK_CON_MUX_ACLK_BUS0_200_USER, 12, 1, CLK_STAT_MUX_ACLK_BUS0_200_USER, 12, 2, CLK_CON_MUX_ACLK_BUS0_200_USER, 21, 0);
|
|
CLK_MUX(BUS0_MUX_PCLK_BUS0_132_USER, bus0_mux_pclk_bus0_132_user_p, CLK_CON_MUX_PCLK_BUS0_132_USER, 12, 1, CLK_STAT_MUX_PCLK_BUS0_132_USER, 12, 2, CLK_CON_MUX_PCLK_BUS0_132_USER, 21, 0);
|
|
CLK_MUX(BUS1_MUX_ACLK_BUS1_528_USER, bus1_mux_aclk_bus1_528_user_p, CLK_CON_MUX_ACLK_BUS1_528_USER, 12, 1, CLK_STAT_MUX_ACLK_BUS1_528_USER, 12, 2, CLK_CON_MUX_ACLK_BUS1_528_USER, 21, 0);
|
|
CLK_MUX(BUS1_MUX_PCLK_BUS1_132_USER, bus1_mux_pclk_bus1_132_user_p, CLK_CON_MUX_PCLK_BUS1_132_USER, 12, 1, CLK_STAT_MUX_PCLK_BUS1_132_USER, 12, 2, CLK_CON_MUX_PCLK_BUS1_132_USER, 21, 0);
|
|
CLK_MUX(CAM0_MUX_ACLK_CAM0_CSIS0_414_USER, cam0_mux_aclk_cam0_csis0_414_user_p, CLK_CON_MUX_ACLK_CAM0_CSIS0_414_USER, 12, 1, CLK_STAT_MUX_ACLK_CAM0_CSIS0_414_USER, 12, 2, CLK_CON_MUX_ACLK_CAM0_CSIS0_414_USER, 21, 0);
|
|
CLK_MUX(CAM0_MUX_ACLK_CAM0_CSIS1_168_USER, cam0_mux_aclk_cam0_csis1_168_user_p, CLK_CON_MUX_ACLK_CAM0_CSIS1_168_USER, 12, 1, CLK_STAT_MUX_ACLK_CAM0_CSIS1_168_USER, 12, 2, CLK_CON_MUX_ACLK_CAM0_CSIS1_168_USER, 21, 0);
|
|
CLK_MUX(CAM0_MUX_ACLK_CAM0_CSIS2_234_USER, cam0_mux_aclk_cam0_csis2_234_user_p, CLK_CON_MUX_ACLK_CAM0_CSIS2_234_USER, 12, 1, CLK_STAT_MUX_ACLK_CAM0_CSIS2_234_USER, 12, 2, CLK_CON_MUX_ACLK_CAM0_CSIS2_234_USER, 21, 0);
|
|
CLK_MUX(CAM0_MUX_ACLK_CAM0_CSIS3_132_USER, cam0_mux_aclk_cam0_csis3_132_user_p, CLK_CON_MUX_ACLK_CAM0_CSIS3_132_USER, 12, 1, CLK_STAT_MUX_ACLK_CAM0_CSIS3_132_USER, 12, 2, CLK_CON_MUX_ACLK_CAM0_CSIS3_132_USER, 21, 0);
|
|
CLK_MUX(CAM0_MUX_ACLK_CAM0_3AA0_414_USER, cam0_mux_aclk_cam0_3aa0_414_user_p, CLK_CON_MUX_ACLK_CAM0_3AA0_414_USER, 12, 1, CLK_STAT_MUX_ACLK_CAM0_3AA0_414_USER, 12, 2, CLK_CON_MUX_ACLK_CAM0_3AA0_414_USER, 21, 0);
|
|
CLK_MUX(CAM0_MUX_ACLK_CAM0_3AA1_414_USER, cam0_mux_aclk_cam0_3aa1_414_user_p, CLK_CON_MUX_ACLK_CAM0_3AA1_414_USER, 12, 1, CLK_STAT_MUX_ACLK_CAM0_3AA1_414_USER, 12, 2, CLK_CON_MUX_ACLK_CAM0_3AA1_414_USER, 21, 0);
|
|
CLK_MUX(CAM0_MUX_ACLK_CAM0_TREX_528_USER, cam0_mux_aclk_cam0_trex_528_user_p, CLK_CON_MUX_ACLK_CAM0_TREX_528_USER, 12, 1, CLK_STAT_MUX_ACLK_CAM0_TREX_528_USER, 12, 2, CLK_CON_MUX_ACLK_CAM0_TREX_528_USER, 21, 0);
|
|
CLK_MUX(CAM0_MUX_PHYCLK_RXBYTECLKHS0_CSIS0_USER, cam0_mux_phyclk_rxbyteclkhs0_csis0_user_p, CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS0_USER, 12, 1, CLK_STAT_MUX_PHYCLK_RXBYTECLKHS0_CSIS0_USER, 12, 2, CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS0_USER, 21, 0);
|
|
CLK_MUX(CAM0_MUX_PHYCLK_RXBYTECLKHS1_CSIS0_USER, cam0_mux_phyclk_rxbyteclkhs1_csis0_user_p, CLK_CON_MUX_PHYCLK_RXBYTECLKHS1_CSIS0_USER, 12, 1, CLK_STAT_MUX_PHYCLK_RXBYTECLKHS1_CSIS0_USER, 12, 2, CLK_CON_MUX_PHYCLK_RXBYTECLKHS1_CSIS0_USER, 21, 0);
|
|
CLK_MUX(CAM0_MUX_PHYCLK_RXBYTECLKHS2_CSIS0_USER, cam0_mux_phyclk_rxbyteclkhs2_csis0_user_p, CLK_CON_MUX_PHYCLK_RXBYTECLKHS2_CSIS0_USER, 12, 1, CLK_STAT_MUX_PHYCLK_RXBYTECLKHS2_CSIS0_USER, 12, 2, CLK_CON_MUX_PHYCLK_RXBYTECLKHS2_CSIS0_USER, 21, 0);
|
|
CLK_MUX(CAM0_MUX_PHYCLK_RXBYTECLKHS3_CSIS0_USER, cam0_mux_phyclk_rxbyteclkhs3_csis0_user_p, CLK_CON_MUX_PHYCLK_RXBYTECLKHS3_CSIS0_USER, 12, 1, CLK_STAT_MUX_PHYCLK_RXBYTECLKHS3_CSIS0_USER, 12, 2, CLK_CON_MUX_PHYCLK_RXBYTECLKHS3_CSIS0_USER, 21, 0);
|
|
CLK_MUX(CAM0_MUX_PHYCLK_RXBYTECLKHS0_CSIS1_USER, cam0_mux_phyclk_rxbyteclkhs0_csis1_user_p, CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS1_USER, 12, 1, CLK_STAT_MUX_PHYCLK_RXBYTECLKHS0_CSIS1_USER, 12, 2, CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS1_USER, 21, 0);
|
|
CLK_MUX(CAM0_MUX_PHYCLK_RXBYTECLKHS1_CSIS1_USER, cam0_mux_phyclk_rxbyteclkhs1_csis1_user_p, CLK_CON_MUX_PHYCLK_RXBYTECLKHS1_CSIS1_USER, 12, 1, CLK_STAT_MUX_PHYCLK_RXBYTECLKHS1_CSIS1_USER, 12, 2, CLK_CON_MUX_PHYCLK_RXBYTECLKHS1_CSIS1_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_ACLK_CAM1_ARM_672_USER, cam1_mux_aclk_cam1_arm_672_user_p, CLK_CON_MUX_ACLK_CAM1_ARM_672_USER, 12, 1, CLK_STAT_MUX_ACLK_CAM1_ARM_672_USER, 12, 2, CLK_CON_MUX_ACLK_CAM1_ARM_672_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_ACLK_CAM1_TREX_VRA_528_USER, cam1_mux_aclk_cam1_trex_vra_528_user_p, CLK_CON_MUX_ACLK_CAM1_TREX_VRA_528_USER, 12, 1, CLK_STAT_MUX_ACLK_CAM1_TREX_VRA_528_USER, 12, 2, CLK_CON_MUX_ACLK_CAM1_TREX_VRA_528_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_ACLK_CAM1_TREX_B_528_USER, cam1_mux_aclk_cam1_trex_b_528_user_p, CLK_CON_MUX_ACLK_CAM1_TREX_B_528_USER, 12, 1, CLK_STAT_MUX_ACLK_CAM1_TREX_B_528_USER, 12, 2, CLK_CON_MUX_ACLK_CAM1_TREX_B_528_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_ACLK_CAM1_BUS_264_USER, cam1_mux_aclk_cam1_bus_264_user_p, CLK_CON_MUX_ACLK_CAM1_BUS_264_USER, 12, 1, CLK_STAT_MUX_ACLK_CAM1_BUS_264_USER, 12, 2, CLK_CON_MUX_ACLK_CAM1_BUS_264_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_ACLK_CAM1_PERI_84_USER, cam1_mux_aclk_cam1_peri_84_user_p, CLK_CON_MUX_ACLK_CAM1_PERI_84_USER, 12, 1, CLK_STAT_MUX_ACLK_CAM1_PERI_84_USER, 12, 2, CLK_CON_MUX_ACLK_CAM1_PERI_84_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_ACLK_CAM1_CSIS2_414_USER, cam1_mux_aclk_cam1_csis2_414_user_p, CLK_CON_MUX_ACLK_CAM1_CSIS2_414_USER, 12, 1, CLK_STAT_MUX_ACLK_CAM1_CSIS2_414_USER, 12, 2, CLK_CON_MUX_ACLK_CAM1_CSIS2_414_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_ACLK_CAM1_CSIS3_132_USER, cam1_mux_aclk_cam1_csis3_132_user_p, CLK_CON_MUX_ACLK_CAM1_CSIS3_132_USER, 12, 1, CLK_STAT_MUX_ACLK_CAM1_CSIS3_132_USER, 12, 2, CLK_CON_MUX_ACLK_CAM1_CSIS3_132_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_ACLK_CAM1_SCL_566_USER, cam1_mux_aclk_cam1_scl_566_user_p, CLK_CON_MUX_ACLK_CAM1_SCL_566_USER, 12, 1, CLK_STAT_MUX_ACLK_CAM1_SCL_566_USER, 12, 2, CLK_CON_MUX_ACLK_CAM1_SCL_566_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_SCLK_CAM1_ISP_SPI0_USER, cam1_mux_sclk_cam1_isp_spi0_user_p, CLK_CON_MUX_SCLK_CAM1_ISP_SPI0_USER, 12, 1, CLK_STAT_MUX_SCLK_CAM1_ISP_SPI0_USER, 12, 2, CLK_CON_MUX_SCLK_CAM1_ISP_SPI0_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_SCLK_CAM1_ISP_SPI1_USER, cam1_mux_sclk_cam1_isp_spi1_user_p, CLK_CON_MUX_SCLK_CAM1_ISP_SPI1_USER, 12, 1, CLK_STAT_MUX_SCLK_CAM1_ISP_SPI1_USER, 12, 2, CLK_CON_MUX_SCLK_CAM1_ISP_SPI1_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_SCLK_CAM1_ISP_UART_USER, cam1_mux_sclk_cam1_isp_uart_user_p, CLK_CON_MUX_SCLK_CAM1_ISP_UART_USER, 12, 1, CLK_STAT_MUX_SCLK_CAM1_ISP_UART_USER, 12, 2, CLK_CON_MUX_SCLK_CAM1_ISP_UART_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_PHYCLK_RXBYTECLKHS0_CSIS2_USER, cam1_mux_phyclk_rxbyteclkhs0_csis2_user_p, CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS2_USER, 12, 1, CLK_STAT_MUX_PHYCLK_RXBYTECLKHS0_CSIS2_USER, 12, 2, CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS2_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_PHYCLK_RXBYTECLKHS1_CSIS2_USER, cam1_mux_phyclk_rxbyteclkhs1_csis2_user_p, CLK_CON_MUX_PHYCLK_RXBYTECLKHS1_CSIS2_USER, 12, 1, CLK_STAT_MUX_PHYCLK_RXBYTECLKHS1_CSIS2_USER, 12, 2, CLK_CON_MUX_PHYCLK_RXBYTECLKHS1_CSIS2_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_PHYCLK_RXBYTECLKHS2_CSIS2_USER, cam1_mux_phyclk_rxbyteclkhs2_csis2_user_p, CLK_CON_MUX_PHYCLK_RXBYTECLKHS2_CSIS2_USER, 12, 1, CLK_STAT_MUX_PHYCLK_RXBYTECLKHS2_CSIS2_USER, 12, 2, CLK_CON_MUX_PHYCLK_RXBYTECLKHS2_CSIS2_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_PHYCLK_RXBYTECLKHS3_CSIS2_USER, cam1_mux_phyclk_rxbyteclkhs3_csis2_user_p, CLK_CON_MUX_PHYCLK_RXBYTECLKHS3_CSIS2_USER, 12, 1, CLK_STAT_MUX_PHYCLK_RXBYTECLKHS3_CSIS2_USER, 12, 2, CLK_CON_MUX_PHYCLK_RXBYTECLKHS3_CSIS2_USER, 21, 0);
|
|
CLK_MUX(CAM1_MUX_PHYCLK_RXBYTECLKHS0_CSIS3_USER, cam1_mux_phyclk_rxbyteclkhs0_csis3_user_p, CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS3_USER, 12, 1, CLK_STAT_MUX_PHYCLK_RXBYTECLKHS0_CSIS3_USER, 12, 2, CLK_CON_MUX_PHYCLK_RXBYTECLKHS0_CSIS3_USER, 21, 0);
|
|
CLK_MUX(CCORE_MUX_ACLK_CCORE_800_USER, ccore_mux_aclk_ccore_800_user_p, CLK_CON_MUX_ACLK_CCORE_800_USER, 12, 1, CLK_STAT_MUX_ACLK_CCORE_800_USER, 12, 2, CLK_CON_MUX_ACLK_CCORE_800_USER, 21, 0);
|
|
CLK_MUX(CCORE_MUX_ACLK_CCORE_264_USER, ccore_mux_aclk_ccore_264_user_p, CLK_CON_MUX_ACLK_CCORE_264_USER, 12, 1, CLK_STAT_MUX_ACLK_CCORE_264_USER, 12, 2, CLK_CON_MUX_ACLK_CCORE_264_USER, 21, 0);
|
|
CLK_MUX(CCORE_MUX_ACLK_CCORE_G3D_800_USER, ccore_mux_aclk_ccore_g3d_800_user_p, CLK_CON_MUX_ACLK_CCORE_G3D_800_USER, 12, 1, CLK_STAT_MUX_ACLK_CCORE_G3D_800_USER, 12, 2, CLK_CON_MUX_ACLK_CCORE_G3D_800_USER, 21, 0);
|
|
CLK_MUX(CCORE_MUX_ACLK_CCORE_528_USER, ccore_mux_aclk_ccore_528_user_p, CLK_CON_MUX_ACLK_CCORE_528_USER, 12, 1, CLK_STAT_MUX_ACLK_CCORE_528_USER, 12, 2, CLK_CON_MUX_ACLK_CCORE_528_USER, 21, 0);
|
|
CLK_MUX(CCORE_MUX_ACLK_CCORE_132_USER, ccore_mux_aclk_ccore_132_user_p, CLK_CON_MUX_ACLK_CCORE_132_USER, 12, 1, CLK_STAT_MUX_ACLK_CCORE_132_USER, 12, 2, CLK_CON_MUX_ACLK_CCORE_132_USER, 21, 0);
|
|
CLK_MUX(CCORE_MUX_PCLK_CCORE_66_USER, ccore_mux_pclk_ccore_66_user_p, CLK_CON_MUX_PCLK_CCORE_66_USER, 12, 1, CLK_STAT_MUX_PCLK_CCORE_66_USER, 12, 2, CLK_CON_MUX_PCLK_CCORE_66_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_DISP_PLL, disp0_mux_disp_pll_p, CLK_CON_MUX_DISP_PLL, 12, 1, CLK_STAT_MUX_DISP_PLL, 12, 2, CLK_CON_MUX_DISP_PLL, 21, 0);
|
|
CLK_MUX(DISP0_MUX_ACLK_DISP0_0_400_USER, disp0_mux_aclk_disp0_0_400_user_p, CLK_CON_MUX_ACLK_DISP0_0_400_USER, 12, 1, CLK_STAT_MUX_ACLK_DISP0_0_400_USER, 12, 2, CLK_CON_MUX_ACLK_DISP0_0_400_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_ACLK_DISP0_1_400_USER, disp0_mux_aclk_disp0_1_400_user_p, CLK_CON_MUX_ACLK_DISP0_1_400_USER, 12, 1, CLK_STAT_MUX_ACLK_DISP0_1_400_USER, 12, 2, CLK_CON_MUX_ACLK_DISP0_1_400_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_SCLK_DISP0_DECON0_ECLK0_USER, disp0_mux_sclk_disp0_decon0_eclk0_user_p, CLK_CON_MUX_SCLK_DISP0_DECON0_ECLK0_USER, 12, 1, CLK_STAT_MUX_SCLK_DISP0_DECON0_ECLK0_USER, 12, 2, CLK_CON_MUX_SCLK_DISP0_DECON0_ECLK0_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_SCLK_DISP0_DECON0_VCLK0_USER, disp0_mux_sclk_disp0_decon0_vclk0_user_p, CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK0_USER, 12, 1, CLK_STAT_MUX_SCLK_DISP0_DECON0_VCLK0_USER, 12, 2, CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK0_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_SCLK_DISP0_DECON0_VCLK1_USER, disp0_mux_sclk_disp0_decon0_vclk1_user_p, CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK1_USER, 12, 1, CLK_STAT_MUX_SCLK_DISP0_DECON0_VCLK1_USER, 12, 2, CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK1_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_SCLK_DISP0_HDMI_AUDIO_USER, disp0_mux_sclk_disp0_hdmi_audio_user_p, CLK_CON_MUX_SCLK_DISP0_HDMI_AUDIO_USER, 12, 1, CLK_STAT_MUX_SCLK_DISP0_HDMI_AUDIO_USER, 12, 2, CLK_CON_MUX_SCLK_DISP0_HDMI_AUDIO_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, disp0_mux_phyclk_hdmiphy_pixel_clko_user_p, CLK_CON_MUX_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, 12, 1, CLK_STAT_MUX_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, 12, 2, CLK_CON_MUX_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_PHYCLK_HDMIPHY_TMDS_CLKO_USER, disp0_mux_phyclk_hdmiphy_tmds_clko_user_p, CLK_CON_MUX_PHYCLK_HDMIPHY_TMDS_CLKO_USER, 12, 1, CLK_STAT_MUX_PHYCLK_HDMIPHY_TMDS_CLKO_USER, 12, 2, CLK_CON_MUX_PHYCLK_HDMIPHY_TMDS_CLKO_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, disp0_mux_phyclk_mipidphy0_rxclkesc0_user_p, CLK_CON_MUX_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, 12, 1, CLK_STAT_MUX_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, 12, 2, CLK_CON_MUX_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER, disp0_mux_phyclk_mipidphy0_bitclkdiv2_user_p, CLK_CON_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER_DISP0, 12, 1, CLK_STAT_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER_DISP0, 12, 2, CLK_CON_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER_DISP0, 21, 0);
|
|
CLK_MUX(DISP0_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, disp0_mux_phyclk_mipidphy0_bitclkdiv8_user_p, CLK_CON_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, 12, 1, CLK_STAT_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, 12, 2, CLK_CON_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, disp0_mux_phyclk_mipidphy1_rxclkesc0_user_p, CLK_CON_MUX_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, 12, 1, CLK_STAT_MUX_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, 12, 2, CLK_CON_MUX_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER, disp0_mux_phyclk_mipidphy1_bitclkdiv2_user_p, CLK_CON_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER_DISP0, 12, 1, CLK_STAT_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER_DISP0, 12, 2, CLK_CON_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER_DISP0, 21, 0);
|
|
CLK_MUX(DISP0_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, disp0_mux_phyclk_mipidphy1_bitclkdiv8_user_p, CLK_CON_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, 12, 1, CLK_STAT_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, 12, 2, CLK_CON_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_PHYCLK_MIPIDPHY2_RXCLKESC0_USER, disp0_mux_phyclk_mipidphy2_rxclkesc0_user_p, CLK_CON_MUX_PHYCLK_MIPIDPHY2_RXCLKESC0_USER, 12, 1, CLK_STAT_MUX_PHYCLK_MIPIDPHY2_RXCLKESC0_USER, 12, 2, CLK_CON_MUX_PHYCLK_MIPIDPHY2_RXCLKESC0_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER, disp0_mux_phyclk_mipidphy2_bitclkdiv2_user_p, CLK_CON_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER_DISP0, 12, 1, CLK_STAT_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER_DISP0, 12, 2, CLK_CON_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER_DISP0, 21, 0);
|
|
CLK_MUX(DISP0_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV8_USER, disp0_mux_phyclk_mipidphy2_bitclkdiv8_user_p, CLK_CON_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV8_USER, 12, 1, CLK_STAT_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV8_USER, 12, 2, CLK_CON_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV8_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_PHYCLK_DPPHY_CH0_TXD_CLK_USER, disp0_mux_phyclk_dpphy_ch0_txd_clk_user_p, CLK_CON_MUX_PHYCLK_DPPHY_CH0_TXD_CLK_USER, 12, 1, CLK_STAT_MUX_PHYCLK_DPPHY_CH0_TXD_CLK_USER, 12, 2, CLK_CON_MUX_PHYCLK_DPPHY_CH0_TXD_CLK_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_PHYCLK_DPPHY_CH1_TXD_CLK_USER, disp0_mux_phyclk_dpphy_ch1_txd_clk_user_p, CLK_CON_MUX_PHYCLK_DPPHY_CH1_TXD_CLK_USER, 12, 1, CLK_STAT_MUX_PHYCLK_DPPHY_CH1_TXD_CLK_USER, 12, 2, CLK_CON_MUX_PHYCLK_DPPHY_CH1_TXD_CLK_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_PHYCLK_DPPHY_CH2_TXD_CLK_USER, disp0_mux_phyclk_dpphy_ch2_txd_clk_user_p, CLK_CON_MUX_PHYCLK_DPPHY_CH2_TXD_CLK_USER, 12, 1, CLK_STAT_MUX_PHYCLK_DPPHY_CH2_TXD_CLK_USER, 12, 2, CLK_CON_MUX_PHYCLK_DPPHY_CH2_TXD_CLK_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_PHYCLK_DPPHY_CH3_TXD_CLK_USER, disp0_mux_phyclk_dpphy_ch3_txd_clk_user_p, CLK_CON_MUX_PHYCLK_DPPHY_CH3_TXD_CLK_USER, 12, 1, CLK_STAT_MUX_PHYCLK_DPPHY_CH3_TXD_CLK_USER, 12, 2, CLK_CON_MUX_PHYCLK_DPPHY_CH3_TXD_CLK_USER, 21, 0);
|
|
CLK_MUX(DISP0_MUX_ACLK_DISP0_1_400, disp0_mux_aclk_disp0_1_400_p, CLK_CON_MUX_ACLK_DISP0_1_400_DISP0, 12, 1, CLK_STAT_MUX_ACLK_DISP0_1_400_DISP0, 12, 2, CLK_CON_MUX_ACLK_DISP0_1_400_DISP0, 21, 0);
|
|
CLK_MUX(DISP0_MUX_SCLK_DISP0_DECON0_ECLK0, disp0_mux_sclk_disp0_decon0_eclk0_p, CLK_CON_MUX_SCLK_DISP0_DECON0_ECLK0_DISP0, 12, 3, CLK_STAT_MUX_SCLK_DISP0_DECON0_ECLK0_DISP0, 12, 8, CLK_CON_MUX_SCLK_DISP0_DECON0_ECLK0_DISP0, 21, 0);
|
|
CLK_MUX(DISP0_MUX_SCLK_DISP0_DECON0_VCLK0, disp0_mux_sclk_disp0_decon0_vclk0_p, CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK0_DISP0, 12, 3, CLK_STAT_MUX_SCLK_DISP0_DECON0_VCLK0_DISP0, 12, 8, CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK0_DISP0, 21, 0);
|
|
CLK_MUX(DISP0_MUX_SCLK_DISP0_DECON0_VCLK1, disp0_mux_sclk_disp0_decon0_vclk1_p, CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK1_DISP0, 12, 3, CLK_STAT_MUX_SCLK_DISP0_DECON0_VCLK1_DISP0, 12, 8, CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK1_DISP0, 21, 0);
|
|
CLK_MUX(DISP0_MUX_SCLK_DISP0_HDMI_AUDIO, disp0_mux_sclk_disp0_hdmi_audio_p, CLK_CON_MUX_SCLK_DISP0_HDMI_AUDIO_DISP0, 12, 1, CLK_STAT_MUX_SCLK_DISP0_HDMI_AUDIO_DISP0, 12, 2, CLK_CON_MUX_SCLK_DISP0_HDMI_AUDIO_DISP0, 21, 0);
|
|
CLK_MUX(DISP1_MUX_ACLK_DISP1_0_400_USER, disp1_mux_aclk_disp1_0_400_user_p, CLK_CON_MUX_ACLK_DISP1_0_400_USER, 12, 1, CLK_STAT_MUX_ACLK_DISP1_0_400_USER, 12, 2, CLK_CON_MUX_ACLK_DISP1_0_400_USER, 21, 0);
|
|
CLK_MUX(DISP1_MUX_ACLK_DISP1_1_400_USER, disp1_mux_aclk_disp1_1_400_user_p, CLK_CON_MUX_ACLK_DISP1_1_400_USER, 12, 1, CLK_STAT_MUX_ACLK_DISP1_1_400_USER, 12, 2, CLK_CON_MUX_ACLK_DISP1_1_400_USER, 21, 0);
|
|
CLK_MUX(DISP1_MUX_SCLK_DISP1_DECON1_ECLK0_USER, disp1_mux_sclk_disp1_decon1_eclk0_user_p, CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK0_USER, 12, 1, CLK_STAT_MUX_SCLK_DISP1_DECON1_ECLK0_USER, 12, 2, CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK0_USER, 21, 0);
|
|
CLK_MUX(DISP1_MUX_SCLK_DISP1_DECON1_ECLK1_USER, disp1_mux_sclk_disp1_decon1_eclk1_user_p, CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK1_USER, 12, 1, CLK_STAT_MUX_SCLK_DISP1_DECON1_ECLK1_USER, 12, 2, CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK1_USER, 21, 0);
|
|
CLK_MUX(DISP1_MUX_SCLK_DISP1_600_USER, disp1_mux_sclk_disp1_600_user_p, CLK_CON_MUX_SCLK_DISP1_600_USER, 12, 1, CLK_STAT_MUX_SCLK_DISP1_600_USER, 12, 2, CLK_CON_MUX_SCLK_DISP1_600_USER, 21, 0);
|
|
CLK_MUX(DISP1_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER, disp1_mux_phyclk_mipidphy0_bitclkdiv2_user_p, CLK_CON_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER_DISP1, 12, 1, CLK_STAT_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER_DISP1, 12, 2, CLK_CON_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER_DISP1, 21, 0);
|
|
CLK_MUX(DISP1_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER, disp1_mux_phyclk_mipidphy1_bitclkdiv2_user_p, CLK_CON_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER_DISP1, 12, 1, CLK_STAT_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER_DISP1, 12, 2, CLK_CON_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER_DISP1, 21, 0);
|
|
CLK_MUX(DISP1_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER, disp1_mux_phyclk_mipidphy2_bitclkdiv2_user_p, CLK_CON_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER_DISP1, 12, 1, CLK_STAT_MUX_PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_USER, 12, 2, CLK_CON_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER_DISP1, 21, 0);
|
|
CLK_MUX(DISP1_MUX_PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_USER, disp1_mux_phyclk_disp1_hdmiphy_pixel_clko_user_p, CLK_CON_MUX_PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_USER, 12, 1, CLK_STAT_MUX_SCLK_DISP1_600_USER, 12, 2, CLK_CON_MUX_PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_USER, 21, 0);
|
|
CLK_MUX(DISP1_MUX_ACLK_DISP1_1_400, disp1_mux_aclk_disp1_1_400_p, CLK_CON_MUX_ACLK_DISP1_1_400_DISP1, 12, 1, CLK_STAT_MUX_ACLK_DISP1_1_400_DISP1, 12, 2, CLK_CON_MUX_ACLK_DISP1_1_400_DISP1, 21, 0);
|
|
CLK_MUX(DISP1_MUX_SCLK_DISP1_DECON1_ECLK0, disp1_mux_sclk_disp1_decon1_eclk0_p, CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK0_DISP1, 12, 3, CLK_STAT_MUX_SCLK_DISP1_DECON1_ECLK0_DISP1, 12, 8, CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK0_DISP1, 21, 0);
|
|
CLK_MUX(DISP1_MUX_SCLK_DISP1_DECON1_ECLK1, disp1_mux_sclk_disp1_decon1_eclk1_p, CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK1_DISP1, 12, 2, CLK_STAT_MUX_SCLK_DISP1_DECON1_ECLK1_DISP1, 12, 4, CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK1_DISP1, 21, 0);
|
|
CLK_MUX(DISP1_MUX_SCLK_DECON1_ECLK1, disp1_mux_sclk_decon1_eclk1_p, CLK_CON_MUX_SCLK_DECON1_ECLK1, 12, 1, CLK_STAT_MUX_SCLK_DECON1_ECLK1, 12, 2, CLK_CON_MUX_SCLK_DECON1_ECLK1, 21, 0);
|
|
CLK_MUX(FSYS0_MUX_ACLK_FSYS0_200_USER, fsys0_mux_aclk_fsys0_200_user_p, CLK_CON_MUX_ACLK_FSYS0_200_USER, 12, 1, CLK_STAT_MUX_ACLK_FSYS0_200_USER, 12, 2, CLK_CON_MUX_ACLK_FSYS0_200_USER, 21, 0);
|
|
CLK_MUX(FSYS0_MUX_SCLK_FSYS0_USBDRD30_USER, fsys0_mux_sclk_fsys0_usbdrd30_user_p, CLK_CON_MUX_SCLK_FSYS0_USBDRD30_USER, 12, 1, CLK_STAT_MUX_SCLK_FSYS0_USBDRD30_USER, 12, 2, CLK_CON_MUX_SCLK_FSYS0_USBDRD30_USER, 21, 0);
|
|
CLK_MUX(FSYS0_MUX_SCLK_FSYS0_MMC0_USER, fsys0_mux_sclk_fsys0_mmc0_user_p, CLK_CON_MUX_SCLK_FSYS0_MMC0_USER, 12, 1, CLK_STAT_MUX_SCLK_FSYS0_MMC0_USER, 12, 2, CLK_CON_MUX_SCLK_FSYS0_MMC0_USER, 21, 0);
|
|
CLK_MUX(FSYS0_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_USER, fsys0_mux_sclk_fsys0_ufsunipro_embedded_user_p, CLK_CON_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_USER, 12, 1, CLK_STAT_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_USER, 12, 2, CLK_CON_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_USER, 21, 0);
|
|
CLK_MUX(FSYS0_MUX_SCLK_FSYS0_24M_USER, fsys0_mux_sclk_fsys0_24m_user_p, CLK_CON_MUX_SCLK_FSYS0_24M_USER, 12, 1, CLK_STAT_MUX_SCLK_FSYS0_24M_USER, 12, 2, CLK_CON_MUX_SCLK_FSYS0_24M_USER, 21, 0);
|
|
CLK_MUX(FSYS0_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_CFG_USER, fsys0_mux_sclk_fsys0_ufsunipro_embedded_cfg_user_p, CLK_CON_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_CFG_USER, 12, 1, CLK_STAT_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_CFG_USER, 12, 2, CLK_CON_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_CFG_USER, 21, 0);
|
|
CLK_MUX(FSYS0_MUX_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER, fsys0_mux_phyclk_usbdrd30_udrd30_phyclock_user_p, CLK_CON_MUX_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER, 12, 1, CLK_STAT_MUX_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER, 12, 2, CLK_CON_MUX_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER, 21, 0);
|
|
CLK_MUX(FSYS0_MUX_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER, fsys0_mux_phyclk_usbdrd30_udrd30_pipe_pclk_user_p, CLK_CON_MUX_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER, 12, 1, CLK_STAT_MUX_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER, 12, 2, CLK_CON_MUX_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER, 21, 0);
|
|
CLK_MUX(FSYS0_MUX_PHYCLK_UFS_TX0_SYMBOL_USER, fsys0_mux_phyclk_ufs_tx0_symbol_user_p, CLK_CON_MUX_PHYCLK_UFS_TX0_SYMBOL_USER, 12, 1, CLK_STAT_MUX_PHYCLK_UFS_TX0_SYMBOL_USER, 12, 2, CLK_CON_MUX_PHYCLK_UFS_TX0_SYMBOL_USER, 21, 0);
|
|
CLK_MUX(FSYS0_MUX_PHYCLK_UFS_RX0_SYMBOL_USER, fsys0_mux_phyclk_ufs_rx0_symbol_user_p, CLK_CON_MUX_PHYCLK_UFS_RX0_SYMBOL_USER, 12, 1, CLK_STAT_MUX_PHYCLK_UFS_RX0_SYMBOL_USER, 12, 2, CLK_CON_MUX_PHYCLK_UFS_RX0_SYMBOL_USER, 21, 0);
|
|
CLK_MUX(FSYS0_MUX_PHYCLK_USBHOST20_PHYCLOCK_USER, fsys0_mux_phyclk_usbhost20_phyclock_user_p, CLK_CON_MUX_PHYCLK_USBHOST20_PHYCLOCK_USER, 12, 1, CLK_STAT_MUX_PHYCLK_USBHOST20_PHYCLOCK_USER, 12, 2, CLK_CON_MUX_PHYCLK_USBHOST20_PHYCLOCK_USER, 21, 0);
|
|
CLK_MUX(FSYS0_MUX_PHYCLK_USBHOST20PHY_REF_CLK, fsys0_mux_phyclk_usbhost20phy_ref_clk_p, CLK_CON_MUX_PHYCLK_USBHOST20PHY_REF_CLK, 12, 1, CLK_STAT_MUX_PHYCLK_USBHOST20PHY_REF_CLK, 12, 2, CLK_CON_MUX_PHYCLK_USBHOST20PHY_REF_CLK, 21, 0);
|
|
CLK_MUX(FSYS1_MUX_ACLK_FSYS1_200_USER, fsys1_mux_aclk_fsys1_200_user_p, CLK_CON_MUX_ACLK_FSYS1_200_USER, 12, 1, CLK_STAT_MUX_ACLK_FSYS1_200_USER, 12, 2, CLK_CON_MUX_ACLK_FSYS1_200_USER, 21, 0);
|
|
CLK_MUX(FSYS1_MUX_SCLK_FSYS1_MMC2_USER, fsys1_mux_sclk_fsys1_mmc2_user_p, CLK_CON_MUX_SCLK_FSYS1_MMC2_USER, 12, 1, CLK_STAT_MUX_SCLK_FSYS1_MMC2_USER, 12, 2, CLK_CON_MUX_SCLK_FSYS1_MMC2_USER, 21, 0);
|
|
CLK_MUX(FSYS1_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_USER, fsys1_mux_sclk_fsys1_ufsunipro_sdcard_user_p, CLK_CON_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_USER, 12, 1, CLK_STAT_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_USER, 12, 2, CLK_CON_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_USER, 21, 0);
|
|
CLK_MUX(FSYS1_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_CFG_USER, fsys1_mux_sclk_fsys1_ufsunipro_sdcard_cfg_user_p, CLK_CON_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_CFG_USER, 12, 1, CLK_STAT_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_CFG_USER, 12, 2, CLK_CON_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_CFG_USER, 21, 0);
|
|
CLK_MUX(FSYS1_MUX_SCLK_FSYS1_PCIE_PHY_USER, fsys1_mux_sclk_fsys1_pcie_phy_user_p, CLK_CON_MUX_SCLK_FSYS1_PCIE_PHY_USER, 12, 1, CLK_STAT_MUX_SCLK_FSYS1_PCIE_PHY_USER, 12, 2, CLK_CON_MUX_SCLK_FSYS1_PCIE_PHY_USER, 21, 0);
|
|
CLK_MUX(FSYS1_MUX_PCIE_PLL, fsys1_mux_pcie_pll_p, CLK_CON_MUX_PCIE_PLL, 12, 1, CLK_STAT_MUX_PCIE_PLL, 12, 2, CLK_CON_MUX_PCIE_PLL, 21, 0);
|
|
CLK_MUX(FSYS1_MUX_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_USER, fsys1_mux_phyclk_ufs_link_sdcard_tx0_symbol_user_p, CLK_CON_MUX_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_USER, 12, 1, CLK_STAT_MUX_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_USER, 12, 2, CLK_CON_MUX_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_USER, 21, 0);
|
|
CLK_MUX(FSYS1_MUX_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_USER, fsys1_mux_phyclk_ufs_link_sdcard_rx0_symbol_user_p, CLK_CON_MUX_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_USER, 12, 1, CLK_STAT_MUX_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_USER, 12, 2, CLK_CON_MUX_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_USER, 21, 0);
|
|
CLK_MUX(FSYS1_MUX_PHYCLK_PCIE_WIFI0_TX0_USER, fsys1_mux_phyclk_pcie_wifi0_tx0_user_p, CLK_CON_MUX_PHYCLK_PCIE_WIFI0_TX0_USER, 12, 1, CLK_STAT_MUX_PHYCLK_PCIE_WIFI0_TX0_USER, 12, 2, CLK_CON_MUX_PHYCLK_PCIE_WIFI0_TX0_USER, 21, 0);
|
|
CLK_MUX(FSYS1_MUX_PHYCLK_PCIE_WIFI0_RX0_USER, fsys1_mux_phyclk_pcie_wifi0_rx0_user_p, CLK_CON_MUX_PHYCLK_PCIE_WIFI0_RX0_USER, 12, 1, CLK_STAT_MUX_PHYCLK_PCIE_WIFI0_RX0_USER, 12, 2, CLK_CON_MUX_PHYCLK_PCIE_WIFI0_RX0_USER, 21, 0);
|
|
CLK_MUX(FSYS1_MUX_PHYCLK_PCIE_WIFI1_TX0_USER, fsys1_mux_phyclk_pcie_wifi1_tx0_user_p, CLK_CON_MUX_PHYCLK_PCIE_WIFI1_TX0_USER, 12, 1, CLK_STAT_MUX_PHYCLK_PCIE_WIFI1_TX0_USER, 12, 2, CLK_CON_MUX_PHYCLK_PCIE_WIFI1_TX0_USER, 21, 0);
|
|
CLK_MUX(FSYS1_MUX_PHYCLK_PCIE_WIFI1_RX0_USER, fsys1_mux_phyclk_pcie_wifi1_rx0_user_p, CLK_CON_MUX_PHYCLK_PCIE_WIFI1_RX0_USER, 12, 1, CLK_STAT_MUX_PHYCLK_PCIE_WIFI1_RX0_USER, 12, 2, CLK_CON_MUX_PHYCLK_PCIE_WIFI1_RX0_USER, 21, 0);
|
|
CLK_MUX(FSYS1_MUX_PHYCLK_PCIE_WIFI0_DIG_REFCLK_USER, fsys1_mux_phyclk_pcie_wifi0_dig_refclk_user_p, CLK_CON_MUX_PHYCLK_PCIE_WIFI0_DIG_REFCLK_USER, 12, 1, CLK_STAT_MUX_PHYCLK_PCIE_WIFI0_DIG_REFCLK_USER, 12, 2, CLK_CON_MUX_PHYCLK_PCIE_WIFI0_DIG_REFCLK_USER, 21, 0);
|
|
CLK_MUX(FSYS1_MUX_PHYCLK_PCIE_WIFI1_DIG_REFCLK_USER, fsys1_mux_phyclk_pcie_wifi1_dig_refclk_user_p, CLK_CON_MUX_PHYCLK_PCIE_WIFI1_DIG_REFCLK_USER, 12, 1, CLK_STAT_MUX_PHYCLK_PCIE_WIFI1_DIG_REFCLK_USER, 12, 2, CLK_CON_MUX_PHYCLK_PCIE_WIFI1_DIG_REFCLK_USER, 21, 0);
|
|
CLK_MUX(G3D_MUX_G3D_PLL_USER, g3d_mux_g3d_pll_user_p, CLK_CON_MUX_G3D_PLL_USER, 12, 1, CLK_STAT_MUX_G3D_PLL_USER, 12, 2, CLK_CON_MUX_G3D_PLL_USER, 21, 0);
|
|
CLK_MUX(G3D_MUX_BUS_PLL_USER, g3d_mux_bus_pll_user_p, CLK_CON_MUX_BUS_PLL_USER_G3D, 12, 1, CLK_STAT_MUX_BUS_PLL_USER_G3D, 12, 2, CLK_CON_MUX_BUS_PLL_USER_G3D, 21, 0);
|
|
CLK_MUX(G3D_MUX_G3D, g3d_mux_g3d_p, CLK_CON_MUX_G3D, 12, 1, CLK_STAT_MUX_G3D, 12, 2, CLK_CON_MUX_G3D, 21, 0);
|
|
CLK_MUX(IMEM_MUX_ACLK_IMEM_266_USER, imem_mux_aclk_imem_266_user_p, CLK_CON_MUX_ACLK_IMEM_266_USER, 12, 1, CLK_STAT_MUX_ACLK_IMEM_266_USER, 12, 2, CLK_CON_MUX_ACLK_IMEM_266_USER, 21, 0);
|
|
CLK_MUX(IMEM_MUX_ACLK_IMEM_200_USER, imem_mux_aclk_imem_200_user_p, CLK_CON_MUX_ACLK_IMEM_200_USER, 12, 1, CLK_STAT_MUX_ACLK_IMEM_200_USER, 12, 2, CLK_CON_MUX_ACLK_IMEM_200_USER, 21, 0);
|
|
CLK_MUX(IMEM_MUX_ACLK_IMEM_100_USER, imem_mux_aclk_imem_100_user_p, CLK_CON_MUX_ACLK_IMEM_100_USER, 12, 1, CLK_STAT_MUX_ACLK_IMEM_100_USER, 12, 2, CLK_CON_MUX_ACLK_IMEM_100_USER, 21, 0);
|
|
CLK_MUX(ISP0_MUX_ACLK_ISP0_528_USER, isp0_mux_aclk_isp0_528_user_p, CLK_CON_MUX_ACLK_ISP0_528_USER, 12, 1, CLK_STAT_MUX_ACLK_ISP0_528_USER, 12, 2, CLK_CON_MUX_ACLK_ISP0_528_USER, 21, 0);
|
|
CLK_MUX(ISP0_MUX_ACLK_ISP0_TPU_400_USER, isp0_mux_aclk_isp0_tpu_400_user_p, CLK_CON_MUX_ACLK_ISP0_TPU_400_USER, 12, 1, CLK_STAT_MUX_ACLK_ISP0_TPU_400_USER, 12, 2, CLK_CON_MUX_ACLK_ISP0_TPU_400_USER, 21, 0);
|
|
CLK_MUX(ISP0_MUX_ACLK_ISP0_TREX_528_USER, isp0_mux_aclk_isp0_trex_528_user_p, CLK_CON_MUX_ACLK_ISP0_TREX_528_USER, 12, 1, CLK_STAT_MUX_ACLK_ISP0_TREX_528_USER, 12, 2, CLK_CON_MUX_ACLK_ISP0_TREX_528_USER, 21, 0);
|
|
CLK_MUX(ISP0_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_USER, isp0_mux_aclk_isp0_pxl_asbs_is_c_from_is_d_user_p, CLK_CON_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_USER, 12, 1, CLK_STAT_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_USER, 12, 2, CLK_CON_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_USER, 21, 0);
|
|
CLK_MUX(ISP1_MUX_ACLK_ISP1_468_USER, isp1_mux_aclk_isp1_468_user_p, CLK_CON_MUX_ACLK_ISP1_468_USER, 12, 1, CLK_STAT_MUX_ACLK_ISP1_468_USER, 12, 2, CLK_CON_MUX_ACLK_ISP1_468_USER, 21, 0);
|
|
CLK_MUX(MFC_MUX_ACLK_MFC_600_USER, mfc_mux_aclk_mfc_600_user_p, CLK_CON_MUX_ACLK_MFC_600_USER, 12, 1, CLK_STAT_MUX_ACLK_MFC_600_USER, 12, 2, CLK_CON_MUX_ACLK_MFC_600_USER, 21, 0);
|
|
CLK_MUX(MIF0_MUX_MIF_PLL, mif0_mux_mif_pll_p, CLK_CON_MUX_MIF0_PLL, 12, 1, CLK_STAT_MUX_MIF0_PLL, 12, 2, CLK_CON_MUX_MIF0_PLL, 21, 0);
|
|
CLK_MUX(MIF0_MUX_BUS_PLL_USER, mif0_mux_bus_pll_user_p, CLK_CON_MUX_BUS_PLL_USER_MIF0, 12, 1, CLK_STAT_MUX_BUS_PLL_USER_MIF0, 12, 2, CLK_CON_MUX_BUS_PLL_USER_MIF0, 21, 0);
|
|
CLK_MUX(MIF0_MUX_ACLK_MIF_PLL, mif0_mux_aclk_mif_pll_p, CLK_CON_MUX_ACLK_MIF0_PLL, 12, 1, CLK_STAT_MUX_ACLK_MIF0_PLL, 12, 2, CLK_CON_MUX_ACLK_MIF0_PLL, 21, 0);
|
|
CLK_MUX(MIF0_MUX_PCLK_MIF, mif0_mux_pclk_mif_p, CLK_CON_MUX_PCLK_MIF0, 12, 2, CLK_STAT_MUX_PCLK_MIF0, 12, 4, CLK_CON_MUX_PCLK_MIF0, 21, 0);
|
|
CLK_MUX(MIF0_MUX_SCLK_HPM_MIF, mif0_mux_sclk_hpm_mif_p, CLK_CON_MUX_SCLK_HPM_MIF0, 12, 2, CLK_STAT_MUX_SCLK_HPM_MIF0, 12, 4, CLK_CON_MUX_SCLK_HPM_MIF0, 21, 0);
|
|
CLK_MUX(MIF1_MUX_MIF_PLL, mif1_mux_mif_pll_p, CLK_CON_MUX_MIF1_PLL, 12, 1, CLK_STAT_MUX_MIF1_PLL, 12, 2, CLK_CON_MUX_MIF1_PLL, 21, 0);
|
|
CLK_MUX(MIF1_MUX_BUS_PLL_USER, mif1_mux_bus_pll_user_p, CLK_CON_MUX_BUS_PLL_USER_MIF1, 12, 1, CLK_STAT_MUX_BUS_PLL_USER_MIF1, 12, 2, CLK_CON_MUX_BUS_PLL_USER_MIF1, 21, 0);
|
|
CLK_MUX(MIF1_MUX_ACLK_MIF_PLL, mif1_mux_aclk_mif_pll_p, CLK_CON_MUX_ACLK_MIF1_PLL, 12, 1, CLK_STAT_MUX_ACLK_MIF1_PLL, 12, 2, CLK_CON_MUX_ACLK_MIF1_PLL, 21, 0);
|
|
CLK_MUX(MIF1_MUX_PCLK_MIF, mif1_mux_pclk_mif_p, CLK_CON_MUX_PCLK_MIF1, 12, 2, CLK_STAT_MUX_PCLK_MIF1, 12, 4, CLK_CON_MUX_PCLK_MIF1, 21, 0);
|
|
CLK_MUX(MIF1_MUX_SCLK_HPM_MIF, mif1_mux_sclk_hpm_mif_p, CLK_CON_MUX_SCLK_HPM_MIF1, 12, 2, CLK_STAT_MUX_SCLK_HPM_MIF1, 12, 4, CLK_CON_MUX_SCLK_HPM_MIF1, 21, 0);
|
|
CLK_MUX(MIF2_MUX_MIF_PLL, mif2_mux_mif_pll_p, CLK_CON_MUX_MIF2_PLL, 12, 1, CLK_STAT_MUX_MIF2_PLL, 12, 2, CLK_CON_MUX_MIF2_PLL, 21, 0);
|
|
CLK_MUX(MIF2_MUX_BUS_PLL_USER, mif2_mux_bus_pll_user_p, CLK_CON_MUX_BUS_PLL_USER_MIF2, 12, 1, CLK_STAT_MUX_BUS_PLL_USER_MIF2, 12, 2, CLK_CON_MUX_BUS_PLL_USER_MIF2, 21, 0);
|
|
CLK_MUX(MIF2_MUX_ACLK_MIF_PLL, mif2_mux_aclk_mif_pll_p, CLK_CON_MUX_ACLK_MIF2_PLL, 12, 1, CLK_STAT_MUX_ACLK_MIF2_PLL, 12, 2, CLK_CON_MUX_ACLK_MIF2_PLL, 21, 0);
|
|
CLK_MUX(MIF2_MUX_PCLK_MIF, mif2_mux_pclk_mif_p, CLK_CON_MUX_PCLK_MIF2, 12, 2, CLK_STAT_MUX_PCLK_MIF2, 12, 4, CLK_CON_MUX_PCLK_MIF2, 21, 0);
|
|
CLK_MUX(MIF2_MUX_SCLK_HPM_MIF, mif2_mux_sclk_hpm_mif_p, CLK_CON_MUX_SCLK_HPM_MIF2, 12, 2, CLK_STAT_MUX_SCLK_HPM_MIF2, 12, 4, CLK_CON_MUX_SCLK_HPM_MIF2, 21, 0);
|
|
CLK_MUX(MIF3_MUX_MIF_PLL, mif3_mux_mif_pll_p, CLK_CON_MUX_MIF3_PLL, 12, 1, CLK_STAT_MUX_MIF3_PLL, 12, 2, CLK_CON_MUX_MIF3_PLL, 21, 0);
|
|
CLK_MUX(MIF3_MUX_BUS_PLL_USER, mif3_mux_bus_pll_user_p, CLK_CON_MUX_BUS_PLL_USER_MIF3, 12, 1, CLK_STAT_MUX_BUS_PLL_USER_MIF3, 12, 2, CLK_CON_MUX_BUS_PLL_USER_MIF3, 21, 0);
|
|
CLK_MUX(MIF3_MUX_ACLK_MIF_PLL, mif3_mux_aclk_mif_pll_p, CLK_CON_MUX_ACLK_MIF3_PLL, 12, 1, CLK_STAT_MUX_ACLK_MIF3_PLL, 12, 2, CLK_CON_MUX_ACLK_MIF3_PLL, 21, 0);
|
|
CLK_MUX(MIF3_MUX_PCLK_MIF, mif3_mux_pclk_mif_p, CLK_CON_MUX_PCLK_MIF3, 12, 2, CLK_STAT_MUX_PCLK_MIF3, 12, 4, CLK_CON_MUX_PCLK_MIF3, 21, 0);
|
|
CLK_MUX(MIF3_MUX_SCLK_HPM_MIF, mif3_mux_sclk_hpm_mif_p, CLK_CON_MUX_SCLK_HPM_MIF3, 12, 2, CLK_STAT_MUX_SCLK_HPM_MIF3, 12, 4, CLK_CON_MUX_SCLK_HPM_MIF3, 21, 0);
|
|
CLK_MUX(MIF0_MUX_PCLK_SMC, mif0_mux_pclk_smc_p, CLK_CON_MUX_PCLK_SMC_MIF0, 12, 2, CLK_STAT_MUX_PCLK_SMC_MIF0, 12, 4, CLK_CON_MUX_PCLK_SMC_MIF0, 21, 0);
|
|
CLK_MUX(MIF1_MUX_PCLK_SMC, mif1_mux_pclk_smc_p, CLK_CON_MUX_PCLK_SMC_MIF1, 12, 2, CLK_STAT_MUX_PCLK_SMC_MIF1, 12, 4, CLK_CON_MUX_PCLK_SMC_MIF1, 21, 0);
|
|
CLK_MUX(MIF2_MUX_PCLK_SMC, mif2_mux_pclk_smc_p, CLK_CON_MUX_PCLK_SMC_MIF2, 12, 2, CLK_STAT_MUX_PCLK_SMC_MIF2, 12, 4, CLK_CON_MUX_PCLK_SMC_MIF2, 21, 0);
|
|
CLK_MUX(MIF3_MUX_PCLK_SMC, mif3_mux_pclk_smc_p, CLK_CON_MUX_PCLK_SMC_MIF3, 12, 2, CLK_STAT_MUX_PCLK_SMC_MIF3, 12, 4, CLK_CON_MUX_PCLK_SMC_MIF3, 21, 0);
|
|
CLK_MUX(MNGS_MUX_MNGS_PLL, mngs_mux_mngs_pll_p, CLK_CON_MUX_MNGS_PLL, 12, 1, CLK_STAT_MUX_MNGS_PLL, 12, 2, CLK_CON_MUX_MNGS_PLL, 21, 0);
|
|
CLK_MUX(MNGS_MUX_BUS_PLL_MNGS_USER, mngs_mux_bus_pll_mngs_user_p, CLK_CON_MUX_BUS_PLL_MNGS_USER, 12, 1, CLK_STAT_MUX_BUS_PLL_MNGS_USER, 12, 2, CLK_CON_MUX_BUS_PLL_MNGS_USER, 21, 0);
|
|
CLK_MUX(MNGS_MUX_MNGS, mngs_mux_mngs_p, CLK_CON_MUX_MNGS, 12, 1, CLK_STAT_MUX_MNGS, 12, 2, CLK_CON_MUX_MNGS, 21, 0);
|
|
CLK_MUX(MSCL_MUX_ACLK_MSCL0_528_USER, mscl_mux_aclk_mscl0_528_user_p, CLK_CON_MUX_ACLK_MSCL0_528_USER, 12, 1, CLK_STAT_MUX_ACLK_MSCL0_528_USER, 12, 2, CLK_CON_MUX_ACLK_MSCL0_528_USER, 21, 0);
|
|
CLK_MUX(MSCL_MUX_ACLK_MSCL1_528_USER, mscl_mux_aclk_mscl1_528_user_p, CLK_CON_MUX_ACLK_MSCL1_528_USER, 12, 1, CLK_STAT_MUX_ACLK_MSCL1_528_USER, 12, 2, CLK_CON_MUX_ACLK_MSCL1_528_USER, 21, 0);
|
|
CLK_MUX(MSCL_MUX_ACLK_MSCL1_528, mscl_mux_aclk_mscl1_528_p, CLK_CON_MUX_ACLK_MSCL1_528_MSCL, 12, 1, CLK_STAT_MUX_ACLK_MSCL1_528_MSCL, 12, 2, CLK_CON_MUX_ACLK_MSCL1_528_MSCL, 21, 0);
|
|
CLK_MUX(PERIC0_MUX_ACLK_PERIC0_66_USER, peric0_mux_aclk_peric0_66_user_p, CLK_CON_MUX_ACLK_PERIC0_66_USER, 12, 1, CLK_STAT_MUX_ACLK_PERIC0_66_USER, 12, 2, CLK_CON_MUX_ACLK_PERIC0_66_USER, 21, 0);
|
|
CLK_MUX(PERIC0_MUX_SCLK_UART0_USER, peric0_mux_sclk_uart0_user_p, CLK_CON_MUX_SCLK_UART0_USER, 12, 1, CLK_STAT_MUX_SCLK_UART0_USER, 12, 2, CLK_CON_MUX_SCLK_UART0_USER, 21, 0);
|
|
CLK_MUX(PERIC1_MUX_ACLK_PERIC1_66_USER, peric1_mux_aclk_peric1_66_user_p, CLK_CON_MUX_ACLK_PERIC1_66_USER, 12, 1, CLK_STAT_MUX_ACLK_PERIC1_66_USER, 12, 2, CLK_CON_MUX_ACLK_PERIC1_66_USER, 21, 0);
|
|
CLK_MUX(PERIC1_MUX_SCLK_SPI0_USER, peric1_mux_sclk_spi0_user_p, CLK_CON_MUX_SCLK_SPI0_USER, 12, 1, CLK_STAT_MUX_SCLK_SPI0_USER, 12, 2, CLK_CON_MUX_SCLK_SPI0_USER, 21, 0);
|
|
CLK_MUX(PERIC1_MUX_SCLK_SPI1_USER, peric1_mux_sclk_spi1_user_p, CLK_CON_MUX_SCLK_SPI1_USER, 12, 1, CLK_STAT_MUX_SCLK_SPI1_USER, 12, 2, CLK_CON_MUX_SCLK_SPI1_USER, 21, 0);
|
|
CLK_MUX(PERIC1_MUX_SCLK_SPI2_USER, peric1_mux_sclk_spi2_user_p, CLK_CON_MUX_SCLK_SPI2_USER, 12, 1, CLK_STAT_MUX_SCLK_SPI2_USER, 12, 2, CLK_CON_MUX_SCLK_SPI2_USER, 21, 0);
|
|
CLK_MUX(PERIC1_MUX_SCLK_SPI3_USER, peric1_mux_sclk_spi3_user_p, CLK_CON_MUX_SCLK_SPI3_USER, 12, 1, CLK_STAT_MUX_SCLK_SPI3_USER, 12, 2, CLK_CON_MUX_SCLK_SPI3_USER, 21, 0);
|
|
CLK_MUX(PERIC1_MUX_SCLK_SPI4_USER, peric1_mux_sclk_spi4_user_p, CLK_CON_MUX_SCLK_SPI4_USER, 12, 1, CLK_STAT_MUX_SCLK_SPI4_USER, 12, 2, CLK_CON_MUX_SCLK_SPI4_USER, 21, 0);
|
|
CLK_MUX(PERIC1_MUX_SCLK_SPI5_USER, peric1_mux_sclk_spi5_user_p, CLK_CON_MUX_SCLK_SPI5_USER, 12, 1, CLK_STAT_MUX_SCLK_SPI5_USER, 12, 2, CLK_CON_MUX_SCLK_SPI5_USER, 21, 0);
|
|
CLK_MUX(PERIC1_MUX_SCLK_SPI6_USER, peric1_mux_sclk_spi6_user_p, CLK_CON_MUX_SCLK_SPI6_USER, 12, 1, CLK_STAT_MUX_SCLK_SPI6_USER, 12, 2, CLK_CON_MUX_SCLK_SPI6_USER, 21, 0);
|
|
CLK_MUX(PERIC1_MUX_SCLK_SPI7_USER, peric1_mux_sclk_spi7_user_p, CLK_CON_MUX_SCLK_SPI7_USER, 12, 1, CLK_STAT_MUX_SCLK_SPI7_USER, 12, 2, CLK_CON_MUX_SCLK_SPI7_USER, 21, 0);
|
|
CLK_MUX(PERIC1_MUX_SCLK_UART1_USER, peric1_mux_sclk_uart1_user_p, CLK_CON_MUX_SCLK_UART1_USER, 12, 1, CLK_STAT_MUX_SCLK_UART1_USER, 12, 2, CLK_CON_MUX_SCLK_UART1_USER, 21, 0);
|
|
CLK_MUX(PERIC1_MUX_SCLK_UART2_USER, peric1_mux_sclk_uart2_user_p, CLK_CON_MUX_SCLK_UART2_USER, 12, 1, CLK_STAT_MUX_SCLK_UART2_USER, 12, 2, CLK_CON_MUX_SCLK_UART2_USER, 21, 0);
|
|
CLK_MUX(PERIC1_MUX_SCLK_UART3_USER, peric1_mux_sclk_uart3_user_p, CLK_CON_MUX_SCLK_UART3_USER, 12, 1, CLK_STAT_MUX_SCLK_UART3_USER, 12, 2, CLK_CON_MUX_SCLK_UART3_USER, 21, 0);
|
|
CLK_MUX(PERIC1_MUX_SCLK_UART4_USER, peric1_mux_sclk_uart4_user_p, CLK_CON_MUX_SCLK_UART4_USER, 12, 1, CLK_STAT_MUX_SCLK_UART4_USER, 12, 2, CLK_CON_MUX_SCLK_UART4_USER, 21, 0);
|
|
CLK_MUX(PERIC1_MUX_SCLK_UART5_USER, peric1_mux_sclk_uart5_user_p, CLK_CON_MUX_SCLK_UART5_USER, 12, 1, CLK_STAT_MUX_SCLK_UART5_USER, 12, 2, CLK_CON_MUX_SCLK_UART5_USER, 21, 0);
|
|
CLK_MUX(PERIS_MUX_ACLK_PERIS_66_USER, peris_mux_aclk_peris_66_user_p, CLK_CON_MUX_ACLK_PERIS_66_USER, 12, 1, CLK_STAT_MUX_ACLK_PERIS_66_USER, 12, 2, CLK_CON_MUX_ACLK_PERIS_66_USER, 21, 0);
|
|
CLK_MUX(TOP_MUX_BUS0_PLL, top_mux_bus0_pll_p, CLK_CON_MUX_BUS0_PLL, 12, 1, CLK_STAT_MUX_BUS0_PLL, 12, 2, CLK_CON_MUX_BUS0_PLL, 21, 0);
|
|
CLK_MUX(TOP_MUX_BUS1_PLL, top_mux_bus1_pll_p, CLK_CON_MUX_BUS1_PLL, 12, 1, CLK_STAT_MUX_BUS1_PLL, 12, 2, CLK_CON_MUX_BUS1_PLL, 21, 0);
|
|
CLK_MUX(TOP_MUX_BUS2_PLL, top_mux_bus2_pll_p, CLK_CON_MUX_BUS2_PLL, 12, 1, CLK_STAT_MUX_BUS2_PLL, 12, 2, CLK_CON_MUX_BUS2_PLL, 21, 0);
|
|
CLK_MUX(TOP_MUX_BUS3_PLL, top_mux_bus3_pll_p, CLK_CON_MUX_BUS3_PLL, 12, 1, CLK_STAT_MUX_BUS3_PLL, 12, 2, CLK_CON_MUX_BUS3_PLL, 21, 0);
|
|
CLK_MUX(TOP_MUX_MFC_PLL, top_mux_mfc_pll_p, CLK_CON_MUX_MFC_PLL, 12, 1, CLK_STAT_MUX_MFC_PLL, 12, 2, CLK_CON_MUX_MFC_PLL, 21, 0);
|
|
CLK_MUX(TOP_MUX_ISP_PLL, top_mux_isp_pll_p, CLK_CON_MUX_ISP_PLL, 12, 1, CLK_STAT_MUX_ISP_PLL, 12, 2, CLK_CON_MUX_ISP_PLL, 21, 0);
|
|
CLK_MUX(TOP_MUX_AUD_PLL, top_mux_aud_pll_p, CLK_CON_MUX_AUD_PLL, 12, 1, CLK_STAT_MUX_AUD_PLL, 12, 2, CLK_CON_MUX_AUD_PLL, 21, 0);
|
|
CLK_MUX(TOP_MUX_G3D_PLL, top_mux_g3d_pll_p, CLK_CON_MUX_G3D_PLL, 12, 1, CLK_STAT_MUX_G3D_PLL, 12, 2, CLK_CON_MUX_G3D_PLL, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_BUS0_PLL, top_mux_sclk_bus0_pll_p, CLK_CON_MUX_SCLK_BUS0_PLL, 12, 1, CLK_STAT_MUX_SCLK_BUS0_PLL, 12, 2, CLK_CON_MUX_SCLK_BUS0_PLL, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_BUS1_PLL, top_mux_sclk_bus1_pll_p, CLK_CON_MUX_SCLK_BUS1_PLL, 12, 1, CLK_STAT_MUX_SCLK_BUS1_PLL, 12, 2, CLK_CON_MUX_SCLK_BUS1_PLL, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_BUS2_PLL, top_mux_sclk_bus2_pll_p, CLK_CON_MUX_SCLK_BUS2_PLL, 12, 1, CLK_STAT_MUX_SCLK_BUS2_PLL, 12, 2, CLK_CON_MUX_SCLK_BUS2_PLL, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_BUS3_PLL, top_mux_sclk_bus3_pll_p, CLK_CON_MUX_SCLK_BUS3_PLL, 12, 2, CLK_STAT_MUX_SCLK_BUS3_PLL, 12, 4, CLK_CON_MUX_SCLK_BUS3_PLL, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_MFC_PLL, top_mux_sclk_mfc_pll_p, CLK_CON_MUX_SCLK_MFC_PLL, 12, 1, CLK_STAT_MUX_SCLK_MFC_PLL, 12, 2, CLK_CON_MUX_SCLK_MFC_PLL, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_ISP_PLL, top_mux_sclk_isp_pll_p, CLK_CON_MUX_SCLK_ISP_PLL, 12, 1, CLK_STAT_MUX_SCLK_ISP_PLL, 12, 2, CLK_CON_MUX_SCLK_ISP_PLL, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CCORE_800, top_mux_aclk_ccore_800_p, CLK_CON_MUX_ACLK_CCORE_800, 12, 3, CLK_STAT_MUX_ACLK_CCORE_800, 12, 8, CLK_CON_MUX_ACLK_CCORE_800, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CCORE_264, top_mux_aclk_ccore_264_p, CLK_CON_MUX_ACLK_CCORE_264, 12, 2, CLK_STAT_MUX_ACLK_CCORE_264, 12, 4, CLK_CON_MUX_ACLK_CCORE_264, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CCORE_G3D_800, top_mux_aclk_ccore_g3d_800_p, CLK_CON_MUX_ACLK_CCORE_G3D_800, 12, 3, CLK_STAT_MUX_ACLK_CCORE_G3D_800, 12, 8, CLK_CON_MUX_ACLK_CCORE_G3D_800, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CCORE_528, top_mux_aclk_ccore_528_p, CLK_CON_MUX_ACLK_CCORE_528, 12, 3, CLK_STAT_MUX_ACLK_CCORE_528, 12, 8, CLK_CON_MUX_ACLK_CCORE_528, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CCORE_132, top_mux_aclk_ccore_132_p, CLK_CON_MUX_ACLK_CCORE_132, 12, 2, CLK_STAT_MUX_ACLK_CCORE_132, 12, 4, CLK_CON_MUX_ACLK_CCORE_132, 21, 0);
|
|
CLK_MUX(TOP_MUX_PCLK_CCORE_66, top_mux_pclk_ccore_66_p, CLK_CON_MUX_PCLK_CCORE_66, 12, 2, CLK_STAT_MUX_PCLK_CCORE_66, 12, 4, CLK_CON_MUX_PCLK_CCORE_66, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_BUS0_528, top_mux_aclk_bus0_528_p, CLK_CON_MUX_ACLK_BUS0_528, 12, 2, CLK_STAT_MUX_ACLK_BUS0_528, 12, 4, CLK_CON_MUX_ACLK_BUS0_528, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_BUS0_200, top_mux_aclk_bus0_200_p, CLK_CON_MUX_ACLK_BUS0_200, 12, 2, CLK_STAT_MUX_ACLK_BUS0_200, 12, 4, CLK_CON_MUX_ACLK_BUS0_200, 21, 0);
|
|
CLK_MUX(TOP_MUX_PCLK_BUS0_132, top_mux_pclk_bus0_132_p, CLK_CON_MUX_PCLK_BUS0_132, 12, 2, CLK_STAT_MUX_PCLK_BUS0_132, 12, 4, CLK_CON_MUX_PCLK_BUS0_132, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_BUS1_528, top_mux_aclk_bus1_528_p, CLK_CON_MUX_ACLK_BUS1_528, 12, 2, CLK_STAT_MUX_ACLK_BUS1_528, 12, 4, CLK_CON_MUX_ACLK_BUS1_528, 21, 0);
|
|
CLK_MUX(TOP_MUX_PCLK_BUS1_132, top_mux_pclk_bus1_132_p, CLK_CON_MUX_PCLK_BUS1_132, 12, 2, CLK_STAT_MUX_PCLK_BUS1_132, 12, 4, CLK_CON_MUX_PCLK_BUS1_132, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_DISP0_0_400, top_mux_aclk_disp0_0_400_p, CLK_CON_MUX_ACLK_DISP0_0_400, 12, 2, CLK_STAT_MUX_ACLK_DISP0_0_400, 12, 4, CLK_CON_MUX_ACLK_DISP0_0_400, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_DISP0_1_400, top_mux_aclk_disp0_1_400_p, CLK_CON_MUX_ACLK_DISP0_1_400_TOP, 12, 2, CLK_STAT_MUX_ACLK_DISP0_1_400_TOP, 12, 4, CLK_CON_MUX_ACLK_DISP0_1_400_TOP, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_DISP1_0_400, top_mux_aclk_disp1_0_400_p, CLK_CON_MUX_ACLK_DISP1_0_400, 12, 2, CLK_STAT_MUX_ACLK_DISP1_0_400, 12, 4, CLK_CON_MUX_ACLK_DISP1_0_400, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_DISP1_1_400, top_mux_aclk_disp1_1_400_p, CLK_CON_MUX_ACLK_DISP1_1_400_TOP, 12, 2, CLK_STAT_MUX_ACLK_DISP1_1_400_TOP, 12, 4, CLK_CON_MUX_ACLK_DISP1_1_400_TOP, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_MFC_600, top_mux_aclk_mfc_600_p, CLK_CON_MUX_ACLK_MFC_600, 12, 3, CLK_STAT_MUX_ACLK_MFC_600, 12, 8, CLK_CON_MUX_ACLK_MFC_600, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_MSCL0_528, top_mux_aclk_mscl0_528_p, CLK_CON_MUX_ACLK_MSCL0_528, 12, 2, CLK_STAT_MUX_ACLK_MSCL0_528, 12, 4, CLK_CON_MUX_ACLK_MSCL0_528, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_MSCL1_528, top_mux_aclk_mscl1_528_p, CLK_CON_MUX_ACLK_MSCL1_528_TOP, 12, 2, CLK_STAT_MUX_ACLK_MSCL1_528_TOP, 12, 4, CLK_CON_MUX_ACLK_MSCL1_528_TOP, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_IMEM_266, top_mux_aclk_imem_266_p, CLK_CON_MUX_ACLK_IMEM_266, 12, 2, CLK_STAT_MUX_ACLK_IMEM_266, 12, 4, CLK_CON_MUX_ACLK_IMEM_266, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_IMEM_200, top_mux_aclk_imem_200_p, CLK_CON_MUX_ACLK_IMEM_200, 12, 2, CLK_STAT_MUX_ACLK_IMEM_200, 12, 4, CLK_CON_MUX_ACLK_IMEM_200, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_IMEM_100, top_mux_aclk_imem_100_p, CLK_CON_MUX_ACLK_IMEM_100, 12, 2, CLK_STAT_MUX_ACLK_IMEM_100, 12, 4, CLK_CON_MUX_ACLK_IMEM_100, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_FSYS0_200, top_mux_aclk_fsys0_200_p, CLK_CON_MUX_ACLK_FSYS0_200, 12, 2, CLK_STAT_MUX_ACLK_FSYS0_200, 12, 4, CLK_CON_MUX_ACLK_FSYS0_200, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_FSYS1_200, top_mux_aclk_fsys1_200_p, CLK_CON_MUX_ACLK_FSYS1_200, 12, 2, CLK_STAT_MUX_ACLK_FSYS1_200, 12, 4, CLK_CON_MUX_ACLK_FSYS1_200, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_PERIS_66, top_mux_aclk_peris_66_p, CLK_CON_MUX_ACLK_PERIS_66, 12, 2, CLK_STAT_MUX_ACLK_PERIS_66, 12, 4, CLK_CON_MUX_ACLK_PERIS_66, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_PERIC0_66, top_mux_aclk_peric0_66_p, CLK_CON_MUX_ACLK_PERIC0_66, 12, 2, CLK_STAT_MUX_ACLK_PERIC0_66, 12, 4, CLK_CON_MUX_ACLK_PERIC0_66, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_PERIC1_66, top_mux_aclk_peric1_66_p, CLK_CON_MUX_ACLK_PERIC1_66, 12, 2, CLK_STAT_MUX_ACLK_PERIC1_66, 12, 4, CLK_CON_MUX_ACLK_PERIC1_66, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_ISP0_ISP0_528, top_mux_aclk_isp0_isp0_528_p, CLK_CON_MUX_ACLK_ISP0_ISP0_528, 12, 3, CLK_STAT_MUX_ACLK_ISP0_ISP0_528, 12, 8, CLK_CON_MUX_ACLK_ISP0_ISP0_528, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_ISP0_TPU_400, top_mux_aclk_isp0_tpu_400_p, CLK_CON_MUX_ACLK_ISP0_TPU_400, 12, 3, CLK_STAT_MUX_ACLK_ISP0_TPU_400, 12, 8, CLK_CON_MUX_ACLK_ISP0_TPU_400, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_ISP0_TREX_528, top_mux_aclk_isp0_trex_528_p, CLK_CON_MUX_ACLK_ISP0_TREX_528, 12, 3, CLK_STAT_MUX_ACLK_ISP0_TREX_528, 12, 8, CLK_CON_MUX_ACLK_ISP0_TREX_528, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D, top_mux_aclk_isp0_pxl_asbs_is_c_from_is_d_p, CLK_CON_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_TOP, 12, 3, CLK_STAT_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_TOP, 12, 8, CLK_CON_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_TOP, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_ISP1_ISP1_468, top_mux_aclk_isp1_isp1_468_p, CLK_CON_MUX_ACLK_ISP1_ISP1_468, 12, 3, CLK_STAT_MUX_ACLK_ISP1_ISP1_468, 12, 8, CLK_CON_MUX_ACLK_ISP1_ISP1_468, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CAM0_CSIS0_414, top_mux_aclk_cam0_csis0_414_p, CLK_CON_MUX_ACLK_CAM0_CSIS0_414, 12, 3, CLK_STAT_MUX_ACLK_CAM0_CSIS0_414, 12, 8, CLK_CON_MUX_ACLK_CAM0_CSIS0_414, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CAM0_CSIS1_168, top_mux_aclk_cam0_csis1_168_p, CLK_CON_MUX_ACLK_CAM0_CSIS1_168, 12, 1, CLK_STAT_MUX_ACLK_CAM0_CSIS1_168, 12, 2, CLK_CON_MUX_ACLK_CAM0_CSIS1_168, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CAM0_CSIS2_234, top_mux_aclk_cam0_csis2_234_p, CLK_CON_MUX_ACLK_CAM0_CSIS2_234, 12, 3, CLK_STAT_MUX_ACLK_CAM0_CSIS2_234, 12, 8, CLK_CON_MUX_ACLK_CAM0_CSIS2_234, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CAM0_3AA0_414, top_mux_aclk_cam0_3aa0_414_p, CLK_CON_MUX_ACLK_CAM0_3AA0_414, 12, 3, CLK_STAT_MUX_ACLK_CAM0_3AA0_414, 12, 8, CLK_CON_MUX_ACLK_CAM0_3AA0_414, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CAM0_3AA1_414, top_mux_aclk_cam0_3aa1_414_p, CLK_CON_MUX_ACLK_CAM0_3AA1_414, 12, 3, CLK_STAT_MUX_ACLK_CAM0_3AA1_414, 12, 8, CLK_CON_MUX_ACLK_CAM0_3AA1_414, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CAM0_CSIS3_132, top_mux_aclk_cam0_csis3_132_p, CLK_CON_MUX_ACLK_CAM0_CSIS3_132, 12, 1, CLK_STAT_MUX_ACLK_CAM0_CSIS3_132, 12, 2, CLK_CON_MUX_ACLK_CAM0_CSIS3_132, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CAM0_TREX_528, top_mux_aclk_cam0_trex_528_p, CLK_CON_MUX_ACLK_CAM0_TREX_528, 12, 3, CLK_STAT_MUX_ACLK_CAM0_TREX_528, 12, 8, CLK_CON_MUX_ACLK_CAM0_TREX_528, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CAM1_ARM_672, top_mux_aclk_cam1_arm_672_p, CLK_CON_MUX_ACLK_CAM1_ARM_672, 12, 3, CLK_STAT_MUX_ACLK_CAM1_ARM_672, 12, 8, CLK_CON_MUX_ACLK_CAM1_ARM_672, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CAM1_TREX_VRA_528, top_mux_aclk_cam1_trex_vra_528_p, CLK_CON_MUX_ACLK_CAM1_TREX_VRA_528, 12, 3, CLK_STAT_MUX_ACLK_CAM1_TREX_VRA_528, 12, 8, CLK_CON_MUX_ACLK_CAM1_TREX_VRA_528, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CAM1_TREX_B_528, top_mux_aclk_cam1_trex_b_528_p, CLK_CON_MUX_ACLK_CAM1_TREX_B_528, 12, 3, CLK_STAT_MUX_ACLK_CAM1_TREX_B_528, 12, 8, CLK_CON_MUX_ACLK_CAM1_TREX_B_528, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CAM1_BUS_264, top_mux_aclk_cam1_bus_264_p, CLK_CON_MUX_ACLK_CAM1_BUS_264, 12, 3, CLK_STAT_MUX_ACLK_CAM1_BUS_264, 12, 8, CLK_CON_MUX_ACLK_CAM1_BUS_264, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CAM1_PERI_84, top_mux_aclk_cam1_peri_84_p, CLK_CON_MUX_ACLK_CAM1_PERI_84, 12, 1, CLK_STAT_MUX_ACLK_CAM1_PERI_84, 12, 2, CLK_CON_MUX_ACLK_CAM1_PERI_84, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CAM1_CSIS2_414, top_mux_aclk_cam1_csis2_414_p, CLK_CON_MUX_ACLK_CAM1_CSIS2_414, 12, 3, CLK_STAT_MUX_ACLK_CAM1_CSIS2_414, 12, 8, CLK_CON_MUX_ACLK_CAM1_CSIS2_414, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CAM1_CSIS3_132, top_mux_aclk_cam1_csis3_132_p, CLK_CON_MUX_ACLK_CAM1_CSIS3_132, 12, 1, CLK_STAT_MUX_ACLK_CAM1_CSIS3_132, 12, 2, CLK_CON_MUX_ACLK_CAM1_CSIS3_132, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_CAM1_SCL_566, top_mux_aclk_cam1_scl_566_p, CLK_CON_MUX_ACLK_CAM1_SCL_566, 12, 3, CLK_STAT_MUX_ACLK_CAM1_SCL_566, 12, 8, CLK_CON_MUX_ACLK_CAM1_SCL_566, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_DISP0_DECON0_ECLK0, top_mux_sclk_disp0_decon0_eclk0_p, CLK_CON_MUX_SCLK_DISP0_DECON0_ECLK0_TOP, 12, 2, CLK_STAT_MUX_SCLK_DISP0_DECON0_ECLK0_TOP, 12, 4, CLK_CON_MUX_SCLK_DISP0_DECON0_ECLK0_TOP, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_DISP0_DECON0_VCLK0, top_mux_sclk_disp0_decon0_vclk0_p, CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK0_TOP, 12, 2, CLK_STAT_MUX_SCLK_DISP0_DECON0_VCLK0_TOP, 12, 4, CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK0_TOP, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_DISP0_DECON0_VCLK1, top_mux_sclk_disp0_decon0_vclk1_p, CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK1_TOP, 12, 2, CLK_STAT_MUX_SCLK_DISP0_DECON0_VCLK1_TOP, 12, 4, CLK_CON_MUX_SCLK_DISP0_DECON0_VCLK1_TOP, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_DISP0_HDMI_AUDIO, top_mux_sclk_disp0_hdmi_audio_p, CLK_CON_MUX_SCLK_DISP0_HDMI_AUDIO_TOP, 12, 1, CLK_STAT_MUX_SCLK_DISP0_HDMI_AUDIO_TOP, 12, 2, CLK_CON_MUX_SCLK_DISP0_HDMI_AUDIO_TOP, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_DISP1_DECON1_ECLK0, top_mux_sclk_disp1_decon1_eclk0_p, CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK0_TOP, 12, 2, CLK_STAT_MUX_SCLK_DISP1_DECON1_ECLK0_TOP, 12, 4, CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK0_TOP, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_DISP1_DECON1_ECLK1, top_mux_sclk_disp1_decon1_eclk1_p, CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK1_TOP, 12, 2, CLK_STAT_MUX_SCLK_DISP1_DECON1_ECLK1_TOP, 12, 4, CLK_CON_MUX_SCLK_DISP1_DECON1_ECLK1_TOP, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_FSYS0_USBDRD30, top_mux_sclk_fsys0_usbdrd30_p, CLK_CON_MUX_SCLK_FSYS0_USBDRD30, 12, 2, CLK_STAT_MUX_SCLK_FSYS0_USBDRD30, 12, 4, CLK_CON_MUX_SCLK_FSYS0_USBDRD30, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_FSYS0_MMC0, top_mux_sclk_fsys0_mmc0_p, CLK_CON_MUX_SCLK_FSYS0_MMC0, 12, 2, CLK_STAT_MUX_SCLK_FSYS0_MMC0, 12, 4, CLK_CON_MUX_SCLK_FSYS0_MMC0, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_FSYS0_UFSUNIPRO20, top_mux_sclk_fsys0_ufsunipro20_p, CLK_CON_MUX_SCLK_FSYS0_UFSUNIPRO20, 12, 2, CLK_STAT_MUX_SCLK_FSYS0_UFSUNIPRO20, 12, 4, CLK_CON_MUX_SCLK_FSYS0_UFSUNIPRO20, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_FSYS0_PHY_24M, top_mux_sclk_fsys0_phy_24m_p, CLK_CON_MUX_SCLK_FSYS0_PHY_24M, 12, 1, CLK_STAT_MUX_SCLK_FSYS0_PHY_24M, 12, 2, CLK_CON_MUX_SCLK_FSYS0_PHY_24M, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_FSYS0_UFSUNIPRO_CFG, top_mux_sclk_fsys0_ufsunipro_cfg_p, CLK_CON_MUX_SCLK_FSYS0_UFSUNIPRO_CFG, 12, 2, CLK_STAT_MUX_SCLK_FSYS0_UFSUNIPRO_CFG, 12, 4, CLK_CON_MUX_SCLK_FSYS0_UFSUNIPRO_CFG, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_FSYS1_MMC2, top_mux_sclk_fsys1_mmc2_p, CLK_CON_MUX_SCLK_FSYS1_MMC2, 12, 2, CLK_STAT_MUX_SCLK_FSYS1_MMC2, 12, 4, CLK_CON_MUX_SCLK_FSYS1_MMC2, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_FSYS1_UFSUNIPRO20, top_mux_sclk_fsys1_ufsunipro20_p, CLK_CON_MUX_SCLK_FSYS1_UFSUNIPRO20, 12, 2, CLK_STAT_MUX_SCLK_FSYS1_UFSUNIPRO20, 12, 4, CLK_CON_MUX_SCLK_FSYS1_UFSUNIPRO20, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_FSYS1_PCIE_PHY, top_mux_sclk_fsys1_pcie_phy_p, CLK_CON_MUX_SCLK_FSYS1_PCIE_PHY, 12, 1, CLK_STAT_MUX_SCLK_FSYS1_PCIE_PHY, 12, 2, CLK_CON_MUX_SCLK_FSYS1_PCIE_PHY, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_FSYS1_UFSUNIPRO_CFG, top_mux_sclk_fsys1_ufsunipro_cfg_p, CLK_CON_MUX_SCLK_FSYS1_UFSUNIPRO_CFG, 12, 2, CLK_STAT_MUX_SCLK_FSYS1_UFSUNIPRO_CFG, 12, 4, CLK_CON_MUX_SCLK_FSYS1_UFSUNIPRO_CFG, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PERIC0_UART0, top_mux_sclk_peric0_uart0_p, CLK_CON_MUX_SCLK_PERIC0_UART0, 12, 2, CLK_STAT_MUX_SCLK_PERIC0_UART0, 12, 4, CLK_CON_MUX_SCLK_PERIC0_UART0, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PERIC1_SPI0, top_mux_sclk_peric1_spi0_p, CLK_CON_MUX_SCLK_PERIC1_SPI0, 12, 2, CLK_STAT_MUX_SCLK_PERIC1_SPI0, 12, 4, CLK_CON_MUX_SCLK_PERIC1_SPI0, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PERIC1_SPI1, top_mux_sclk_peric1_spi1_p, CLK_CON_MUX_SCLK_PERIC1_SPI1, 12, 2, CLK_STAT_MUX_SCLK_PERIC1_SPI1, 12, 4, CLK_CON_MUX_SCLK_PERIC1_SPI1, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PERIC1_SPI2, top_mux_sclk_peric1_spi2_p, CLK_CON_MUX_SCLK_PERIC1_SPI2, 12, 2, CLK_STAT_MUX_SCLK_PERIC1_SPI2, 12, 4, CLK_CON_MUX_SCLK_PERIC1_SPI2, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PERIC1_SPI3, top_mux_sclk_peric1_spi3_p, CLK_CON_MUX_SCLK_PERIC1_SPI3, 12, 2, CLK_STAT_MUX_SCLK_PERIC1_SPI3, 12, 4, CLK_CON_MUX_SCLK_PERIC1_SPI3, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PERIC1_SPI4, top_mux_sclk_peric1_spi4_p, CLK_CON_MUX_SCLK_PERIC1_SPI4, 12, 2, CLK_STAT_MUX_SCLK_PERIC1_SPI4, 12, 4, CLK_CON_MUX_SCLK_PERIC1_SPI4, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PERIC1_SPI5, top_mux_sclk_peric1_spi5_p, CLK_CON_MUX_SCLK_PERIC1_SPI5, 12, 2, CLK_STAT_MUX_SCLK_PERIC1_SPI5, 12, 4, CLK_CON_MUX_SCLK_PERIC1_SPI5, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PERIC1_SPI6, top_mux_sclk_peric1_spi6_p, CLK_CON_MUX_SCLK_PERIC1_SPI6, 12, 2, CLK_STAT_MUX_SCLK_PERIC1_SPI6, 12, 4, CLK_CON_MUX_SCLK_PERIC1_SPI6, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PERIC1_SPI7, top_mux_sclk_peric1_spi7_p, CLK_CON_MUX_SCLK_PERIC1_SPI7, 12, 2, CLK_STAT_MUX_SCLK_PERIC1_SPI7, 12, 4, CLK_CON_MUX_SCLK_PERIC1_SPI7, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PERIC1_UART1, top_mux_sclk_peric1_uart1_p, CLK_CON_MUX_SCLK_PERIC1_UART1, 12, 2, CLK_STAT_MUX_SCLK_PERIC1_UART1, 12, 4, CLK_CON_MUX_SCLK_PERIC1_UART1, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PERIC1_UART2, top_mux_sclk_peric1_uart2_p, CLK_CON_MUX_SCLK_PERIC1_UART2, 12, 2, CLK_STAT_MUX_SCLK_PERIC1_UART2, 12, 4, CLK_CON_MUX_SCLK_PERIC1_UART2, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PERIC1_UART3, top_mux_sclk_peric1_uart3_p, CLK_CON_MUX_SCLK_PERIC1_UART3, 12, 2, CLK_STAT_MUX_SCLK_PERIC1_UART3, 12, 4, CLK_CON_MUX_SCLK_PERIC1_UART3, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PERIC1_UART4, top_mux_sclk_peric1_uart4_p, CLK_CON_MUX_SCLK_PERIC1_UART4, 12, 2, CLK_STAT_MUX_SCLK_PERIC1_UART4, 12, 4, CLK_CON_MUX_SCLK_PERIC1_UART4, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PERIC1_UART5, top_mux_sclk_peric1_uart5_p, CLK_CON_MUX_SCLK_PERIC1_UART5, 12, 2, CLK_STAT_MUX_SCLK_PERIC1_UART5, 12, 4, CLK_CON_MUX_SCLK_PERIC1_UART5, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_CAM1_ISP_SPI0, top_mux_sclk_cam1_isp_spi0_p, CLK_CON_MUX_SCLK_CAM1_ISP_SPI0, 12, 2, CLK_STAT_MUX_SCLK_CAM1_ISP_SPI0, 12, 4, CLK_CON_MUX_SCLK_CAM1_ISP_SPI0, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_CAM1_ISP_SPI1, top_mux_sclk_cam1_isp_spi1_p, CLK_CON_MUX_SCLK_CAM1_ISP_SPI1, 12, 2, CLK_STAT_MUX_SCLK_CAM1_ISP_SPI1, 12, 4, CLK_CON_MUX_SCLK_CAM1_ISP_SPI1, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_CAM1_ISP_UART, top_mux_sclk_cam1_isp_uart_p, CLK_CON_MUX_SCLK_CAM1_ISP_UART, 12, 1, CLK_STAT_MUX_SCLK_CAM1_ISP_UART, 12, 2, CLK_CON_MUX_SCLK_CAM1_ISP_UART, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_AP2CP_MIF_PLL_OUT, top_mux_sclk_ap2cp_mif_pll_out_p, CLK_CON_MUX_SCLK_AP2CP_MIF_PLL_OUT, 12, 2, CLK_STAT_MUX_SCLK_AP2CP_MIF_PLL_OUT, 12, 4, CLK_CON_MUX_SCLK_AP2CP_MIF_PLL_OUT, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_PSCDC_400, top_mux_aclk_pscdc_400_p, CLK_CON_MUX_ACLK_PSCDC_400, 12, 2, CLK_STAT_MUX_ACLK_PSCDC_400, 12, 4, CLK_CON_MUX_ACLK_PSCDC_400, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_BUS_PLL_MNGS, top_mux_sclk_bus_pll_mngs_p, CLK_CON_MUX_SCLK_BUS_PLL_MNGS, 12, 2, CLK_STAT_MUX_SCLK_BUS_PLL_MNGS, 12, 4, CLK_CON_MUX_SCLK_BUS_PLL_MNGS, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_BUS_PLL_APOLLO, top_mux_sclk_bus_pll_apollo_p, CLK_CON_MUX_SCLK_BUS_PLL_APOLLO, 12, 2, CLK_STAT_MUX_SCLK_BUS_PLL_APOLLO, 12, 4, CLK_CON_MUX_SCLK_BUS_PLL_APOLLO, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_BUS_PLL_MIF, top_mux_sclk_bus_pll_mif_p, CLK_CON_MUX_SCLK_BUS_PLL_MIF, 12, 3, CLK_STAT_MUX_SCLK_BUS_PLL_MIF, 12, 8, CLK_CON_MUX_SCLK_BUS_PLL_MIF, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_BUS_PLL_G3D, top_mux_sclk_bus_pll_g3d_p, CLK_CON_MUX_SCLK_BUS_PLL_G3D, 12, 3, CLK_STAT_MUX_SCLK_BUS_PLL_G3D, 12, 8, CLK_CON_MUX_SCLK_BUS_PLL_G3D, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_ISP_SENSOR0, top_mux_sclk_isp_sensor0_p, CLK_CON_MUX_SCLK_ISP_SENSOR0, 12, 3, CLK_STAT_MUX_SCLK_ISP_SENSOR0, 12, 8, CLK_CON_MUX_SCLK_ISP_SENSOR0, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_ISP_SENSOR1, top_mux_sclk_isp_sensor1_p, CLK_CON_MUX_SCLK_ISP_SENSOR1, 12, 3, CLK_STAT_MUX_SCLK_ISP_SENSOR1, 12, 8, CLK_CON_MUX_SCLK_ISP_SENSOR1, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_ISP_SENSOR2, top_mux_sclk_isp_sensor2_p, CLK_CON_MUX_SCLK_ISP_SENSOR2, 12, 3, CLK_STAT_MUX_SCLK_ISP_SENSOR2, 12, 8, CLK_CON_MUX_SCLK_ISP_SENSOR2, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_ISP_SENSOR3, top_mux_sclk_isp_sensor3_p, CLK_CON_MUX_SCLK_ISP_SENSOR3, 12, 3, CLK_STAT_MUX_SCLK_ISP_SENSOR3, 12, 8, CLK_CON_MUX_SCLK_ISP_SENSOR3, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PROMISE_INT, top_mux_sclk_promise_int_p, CLK_CON_MUX_SCLK_PROMISE_INT, 12, 2, CLK_STAT_MUX_SCLK_PROMISE_INT, 12, 4, CLK_CON_MUX_SCLK_PROMISE_INT, 21, 0);
|
|
CLK_MUX(TOP_MUX_SCLK_PROMISE_DISP, top_mux_sclk_promise_disp_p, CLK_CON_MUX_SCLK_PROMISE_DISP, 12, 2, CLK_STAT_MUX_SCLK_PROMISE_DISP, 12, 4, CLK_CON_MUX_SCLK_PROMISE_DISP, 21, 0);
|
|
CLK_MUX(TOP_MUX_CP2AP_MIF_CLK_USER, top_mux_cp2ap_mif_clk_user_p, CLK_CON_MUX_CP2AP_MIF_CLK_USER, 12, 1, CLK_STAT_MUX_CP2AP_MIF_CLK_USER, 12, 2, CLK_CON_MUX_CP2AP_MIF_CLK_USER, 21, 0);
|
|
CLK_MUX(TOP_MUX_MIF_PLL, top_mux_mif_pll_p, MIF_CLK_CTRL2, 12, 1, CLK_STAT_MUX_MIF0_PLL, 12, 2, NULL, 21, 0);
|
|
CLK_MUX(TOP_MUX_BUS_PLL_MIF, top_mux_bus_pll_mif_p, MIF_CLK_CTRL3, 12, 1, CLK_STAT_MUX_BUS_PLL_USER_MIF0, 12, 2, NULL, 21, 0);
|
|
CLK_MUX(TOP_MUX_ACLK_MIF_PLL, top_mux_aclk_mif_pll_p, MIF_CLK_CTRL4, 12, 1, CLK_STAT_MUX_ACLK_MIF0_PLL, 12, 2, NULL, 21, 0);
|
|
|
|
|
|
int _pwrcal_is_private_mux_set_src(struct pwrcal_clk *clk)
|
|
{
|
|
if (clk->id == TOP_MUX_MIF_PLL ||
|
|
clk->id == TOP_MUX_BUS_PLL_MIF ||
|
|
clk->id == TOP_MUX_ACLK_MIF_PLL)
|
|
return 1;
|
|
return 0;
|
|
}
|
|
|
|
int _pwrcal_private_mux_set_src(struct pwrcal_clk *clk, unsigned int src)
|
|
{
|
|
struct pwrcal_clk *mout_top_mif_pll_submux[4] = {CLK(MIF0_MUX_MIF_PLL), CLK(MIF1_MUX_MIF_PLL), CLK(MIF2_MUX_MIF_PLL), CLK(MIF3_MUX_MIF_PLL)};
|
|
struct pwrcal_clk *mout_top_bus_pll_user_submux[4] = {CLK(MIF0_MUX_BUS_PLL_USER), CLK(MIF1_MUX_BUS_PLL_USER), CLK(MIF2_MUX_BUS_PLL_USER), CLK(MIF3_MUX_BUS_PLL_USER)};
|
|
struct pwrcal_clk *mout_top_aclk_mif_pll_submux[4] = {CLK(MIF0_MUX_ACLK_MIF_PLL), CLK(MIF1_MUX_ACLK_MIF_PLL), CLK(MIF2_MUX_ACLK_MIF_PLL), CLK(MIF3_MUX_ACLK_MIF_PLL)};
|
|
struct pwrcal_clk **submux;
|
|
struct pwrcal_mux *mux = to_mux(clk);
|
|
int timeout;
|
|
unsigned int mux_stat;
|
|
int i;
|
|
|
|
switch (clk->id) {
|
|
case TOP_MUX_MIF_PLL:
|
|
submux = mout_top_mif_pll_submux;
|
|
break;
|
|
case TOP_MUX_BUS_PLL_MIF:
|
|
submux = mout_top_bus_pll_user_submux;
|
|
break;
|
|
case TOP_MUX_ACLK_MIF_PLL:
|
|
submux = mout_top_aclk_mif_pll_submux;
|
|
break;
|
|
default:
|
|
return -1;
|
|
}
|
|
|
|
if (src >= (unsigned int)(mux->num_parents))
|
|
return -1;
|
|
|
|
pwrcal_setf(clk->offset, clk->shift, TO_MASK(clk->width), src);
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
for (timeout = 0;; timeout++) {
|
|
mux_stat = pwrcal_getf(submux[i]->status,
|
|
submux[i]->s_shift,
|
|
TO_MASK(submux[i]->s_width));
|
|
if (mux_stat == (1 << src))
|
|
break;
|
|
|
|
if (timeout > CLK_WAIT_CNT)
|
|
goto timeout_error;
|
|
cpu_relax();
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
timeout_error:
|
|
pr_err("stat(=%d) check time out, \'%s\', src_num(=%d)",
|
|
mux_stat, clk->name, src);
|
|
return -1;
|
|
}
|
|
|
|
|
|
CLK_DIV(APOLLO_DIV_APOLLO, APOLLO_MUX_APOLLO, CLK_CON_DIV_APOLLO, 0, 6, CLK_CON_DIV_APOLLO, 25, 1, 0);
|
|
CLK_DIV(APOLLO_DIV_ACLK_APOLLO, APOLLO_DIV_APOLLO, CLK_CON_DIV_ACLK_APOLLO, 0, 3, CLK_CON_DIV_ACLK_APOLLO, 25, 1, 0);
|
|
CLK_DIV(APOLLO_DIV_ATCLK_APOLLO, APOLLO_DIV_APOLLO, CLK_CON_DIV_ATCLK_APOLLO, 0, 4, CLK_CON_DIV_ATCLK_APOLLO, 25, 1, 0);
|
|
CLK_DIV(APOLLO_DIV_PCLK_DBG_APOLLO, APOLLO_DIV_APOLLO, CLK_CON_DIV_PCLK_DBG_APOLLO, 0, 4, CLK_CON_DIV_PCLK_DBG_APOLLO, 25, 1, 0);
|
|
CLK_DIV(APOLLO_DIV_PCLK_APOLLO, APOLLO_DIV_APOLLO, CLK_CON_DIV_PCLK_APOLLO, 0, 4, CLK_CON_DIV_PCLK_APOLLO, 25, 1, 0);
|
|
CLK_DIV(APOLLO_DIV_CNTCLK_APOLLO, APOLLO_DIV_APOLLO, CLK_CON_DIV_CNTCLK_APOLLO, 0, 4, CLK_CON_DIV_CNTCLK_APOLLO, 25, 1, 0);
|
|
CLK_DIV(APOLLO_DIV_APOLLO_RUN_MONITOR, APOLLO_DIV_APOLLO, CLK_CON_DIV_APOLLO_RUN_MONITOR, 0, 3, CLK_CON_DIV_APOLLO_RUN_MONITOR, 25, 1, 0);
|
|
CLK_DIV(APOLLO_DIV_SCLK_PROMISE_APOLLO, APOLLO_MUX_APOLLO, CLK_CON_DIV_SCLK_PROMISE_APOLLO, 0, 3, CLK_CON_DIV_SCLK_PROMISE_APOLLO, 25, 1, 0);
|
|
CLK_DIV(APOLLO_DIV_APOLLO_PLL, APOLLO_MUX_APOLLO, CLK_CON_DIV_APOLLO_PLL, 0, 3, CLK_CON_DIV_APOLLO_PLL, 25, 1, 0);
|
|
CLK_DIV(AUD_DIV_AUD_CA5, AUD_MUX_AUD_PLL_USER, CLK_CON_DIV_AUD_CA5, 0, 4, CLK_CON_DIV_AUD_CA5, 25, 1, 0);
|
|
CLK_DIV(AUD_DIV_ACLK_AUD, AUD_MUX_ACLK_CA5, CLK_CON_DIV_ACLK_AUD, 0, 4, CLK_CON_DIV_ACLK_AUD, 25, 1, 0);
|
|
CLK_DIV(AUD_DIV_PCLK_DBG, AUD_MUX_ACLK_CA5, CLK_CON_DIV_PCLK_DBG, 0, 4, CLK_CON_DIV_PCLK_DBG, 25, 1, 0);
|
|
CLK_DIV(AUD_DIV_ATCLK_AUD, AUD_MUX_ACLK_CA5, CLK_CON_DIV_ATCLK_AUD, 0, 4, CLK_CON_DIV_ATCLK_AUD, 25, 1, 0);
|
|
CLK_DIV(AUD_DIV_AUD_CDCLK, AUD_MUX_AUD_PLL_USER, CLK_CON_DIV_AUD_CDCLK, 0, 4, CLK_CON_DIV_AUD_CDCLK, 25, 1, 0);
|
|
CLK_DIV(AUD_DIV_SCLK_I2S, AUD_MUX_SCLK_I2S, CLK_CON_DIV_SCLK_I2S, 0, 4, CLK_CON_DIV_SCLK_I2S, 25, 1, 0);
|
|
CLK_DIV(AUD_DIV_SCLK_PCM, AUD_MUX_SCLK_PCM, CLK_CON_DIV_SCLK_PCM, 0, 8, CLK_CON_DIV_SCLK_PCM, 25, 1, 0);
|
|
CLK_DIV(AUD_DIV_SCLK_SLIMBUS, AUD_MUX_CDCLK_AUD, CLK_CON_DIV_SCLK_SLIMBUS, 0, 5, CLK_CON_DIV_SCLK_SLIMBUS, 25, 1, 0);
|
|
CLK_DIV(AUD_DIV_SCLK_CP_I2S, AUD_MUX_CDCLK_AUD, CLK_CON_DIV_SCLK_CP_I2S, 0, 6, CLK_CON_DIV_SCLK_CP_I2S, 25, 1, 0);
|
|
CLK_DIV(AUD_DIV_SCLK_ASRC, AUD_MUX_CDCLK_AUD, CLK_CON_DIV_SCLK_ASRC, 0, 5, CLK_CON_DIV_SCLK_ASRC, 25, 1, 0);
|
|
CLK_DIV(AUD_DIV_CP_CA5, AUD_MUX_CP2AP_AUD_CLK_USER, CLK_CON_DIV_CP_CA5, 0, 5, CLK_CON_DIV_CP_CA5, 25, 1, 0);
|
|
CLK_DIV(AUD_DIV_CP_CDCLK, AUD_MUX_CP2AP_AUD_CLK_USER, CLK_CON_DIV_CP_CDCLK, 0, 5, CLK_CON_DIV_CP_CDCLK, 25, 1, 0);
|
|
CLK_DIV(CAM0_DIV_PCLK_CAM0_CSIS0_207, CAM0_MUX_ACLK_CAM0_CSIS0_414_USER, CLK_CON_DIV_PCLK_CAM0_CSIS0_207, 0, 3, CLK_CON_DIV_PCLK_CAM0_CSIS0_207, 25, 1, 0);
|
|
CLK_DIV(CAM0_DIV_PCLK_CAM0_3AA0_207, CAM0_MUX_ACLK_CAM0_3AA0_414_USER, CLK_CON_DIV_PCLK_CAM0_3AA0_207, 0, 3, CLK_CON_DIV_PCLK_CAM0_3AA0_207, 25, 1, 0);
|
|
CLK_DIV(CAM0_DIV_PCLK_CAM0_3AA1_207, CAM0_MUX_ACLK_CAM0_3AA1_414_USER, CLK_CON_DIV_PCLK_CAM0_3AA1_207, 0, 3, CLK_CON_DIV_PCLK_CAM0_3AA1_207, 25, 1, 0);
|
|
CLK_DIV(CAM0_DIV_PCLK_CAM0_TREX_264, CAM0_MUX_ACLK_CAM0_TREX_528_USER, CLK_CON_DIV_PCLK_CAM0_TREX_264, 0, 3, CLK_CON_DIV_PCLK_CAM0_TREX_264, 25, 1, 0);
|
|
CLK_DIV(CAM0_DIV_PCLK_CAM0_TREX_132, CAM0_MUX_ACLK_CAM0_TREX_528_USER, CLK_CON_DIV_PCLK_CAM0_TREX_132, 0, 3, CLK_CON_DIV_PCLK_CAM0_TREX_132, 25, 1, 0);
|
|
CLK_DIV(CAM1_DIV_PCLK_CAM1_ARM_168, CAM1_MUX_ACLK_CAM1_ARM_672_USER, CLK_CON_DIV_PCLK_CAM1_ARM_168, 0, 3, CLK_CON_DIV_PCLK_CAM1_ARM_168, 25, 1, 0);
|
|
CLK_DIV(CAM1_DIV_PCLK_CAM1_TREX_VRA_264, CAM1_MUX_ACLK_CAM1_TREX_VRA_528_USER, CLK_CON_DIV_PCLK_CAM1_TREX_VRA_264, 0, 3, CLK_CON_DIV_PCLK_CAM1_TREX_VRA_264, 25, 1, 0);
|
|
CLK_DIV(CAM1_DIV_PCLK_CAM1_BUS_132, CAM1_MUX_ACLK_CAM1_BUS_264_USER, CLK_CON_DIV_PCLK_CAM1_BUS_132, 0, 3, CLK_CON_DIV_PCLK_CAM1_BUS_132, 25, 1, 0);
|
|
CLK_DIV(CCORE_DIV_SCLK_HPM_CCORE, CCORE_MUX_ACLK_CCORE_800_USER, CLK_CON_DIV_SCLK_HPM_CCORE, 0, 4, CLK_CON_DIV_SCLK_HPM_CCORE, 25, 1, 0);
|
|
CLK_DIV(DISP0_DIV_PCLK_DISP0_0_133, DISP0_MUX_ACLK_DISP0_0_400_USER, CLK_CON_DIV_PCLK_DISP0_0_133, 0, 3, CLK_CON_DIV_PCLK_DISP0_0_133, 25, 1, 0);
|
|
CLK_DIV(DISP0_DIV_SCLK_DECON0_ECLK0, DISP0_MUX_SCLK_DISP0_DECON0_ECLK0, CLK_CON_DIV_SCLK_DECON0_ECLK0, 0, 3, CLK_CON_DIV_SCLK_DECON0_ECLK0, 25, 1, 0);
|
|
CLK_DIV(DISP0_DIV_SCLK_DECON0_VCLK0, DISP0_MUX_SCLK_DISP0_DECON0_VCLK0, CLK_CON_DIV_SCLK_DECON0_VCLK0, 0, 3, CLK_CON_DIV_SCLK_DECON0_VCLK0, 25, 1, 0);
|
|
CLK_DIV(DISP0_DIV_SCLK_DECON0_VCLK1, DISP0_MUX_SCLK_DISP0_DECON0_VCLK1, CLK_CON_DIV_SCLK_DECON0_VCLK1, 0, 3, CLK_CON_DIV_SCLK_DECON0_VCLK1, 25, 1, 0);
|
|
CLK_DIV(DISP0_DIV_PHYCLK_HDMIPHY_PIXEL_CLKO, DISP0_MUX_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, CLK_CON_DIV_PHYCLK_HDMIPHY_PIXEL_CLKO, 0, 1, CLK_CON_DIV_PHYCLK_HDMIPHY_PIXEL_CLKO, 25, 1, 0);
|
|
CLK_DIV(DISP0_DIV_PHYCLK_HDMIPHY_TMDS_20B_CLKO, DISP0_MUX_PHYCLK_HDMIPHY_TMDS_CLKO_USER, CLK_CON_DIV_PHYCLK_HDMIPHY_TMDS_20B_CLKO, 0, 1, CLK_CON_DIV_PHYCLK_HDMIPHY_TMDS_20B_CLKO, 25, 1, 0);
|
|
CLK_DIV(DISP1_DIV_PCLK_DISP1_0_133, DISP1_MUX_ACLK_DISP1_0_400_USER, CLK_CON_DIV_PCLK_DISP1_0_133, 0, 3, CLK_CON_DIV_PCLK_DISP1_0_133, 25, 1, 0);
|
|
CLK_DIV(DISP1_DIV_SCLK_DECON1_ECLK0, DISP1_MUX_SCLK_DISP1_DECON1_ECLK0, CLK_CON_DIV_SCLK_DECON1_ECLK0, 0, 3, CLK_CON_DIV_SCLK_DECON1_ECLK0, 25, 1, 0);
|
|
CLK_DIV(DISP1_DIV_SCLK_DECON1_ECLK1, DISP1_MUX_SCLK_DISP1_DECON1_ECLK1, CLK_CON_DIV_SCLK_DECON1_ECLK1, 0, 3, CLK_CON_DIV_SCLK_DECON1_ECLK1, 25, 1, 0);
|
|
CLK_DIV(FSYS1_DIV_PCLK_COMBO_PHY_WIFI, FSYS1_MUX_ACLK_FSYS1_200_USER, CLK_CON_DIV_PCLK_COMBO_PHY_WIFI, 0, 2, CLK_CON_DIV_PCLK_COMBO_PHY_WIFI, 25, 1, 0);
|
|
CLK_DIV(G3D_DIV_ACLK_G3D, G3D_MUX_G3D, CLK_CON_DIV_ACLK_G3D, 0, 3, CLK_CON_DIV_ACLK_G3D, 25, 1, 0);
|
|
CLK_DIV(G3D_DIV_PCLK_G3D, G3D_DIV_ACLK_G3D, CLK_CON_DIV_PCLK_G3D, 0, 3, CLK_CON_DIV_PCLK_G3D, 25, 1, 0);
|
|
CLK_DIV(G3D_DIV_SCLK_HPM_G3D, G3D_MUX_G3D, CLK_CON_DIV_SCLK_HPM_G3D, 0, 2, CLK_CON_DIV_SCLK_HPM_G3D, 25, 1, 0);
|
|
CLK_DIV(G3D_DIV_SCLK_ATE_G3D, G3D_MUX_G3D, CLK_CON_DIV_SCLK_ATE_G3D, 0, 4, CLK_CON_DIV_SCLK_ATE_G3D, 25, 1, 0);
|
|
CLK_DIV(ISP0_DIV_PCLK_ISP0, ISP0_MUX_ACLK_ISP0_528_USER, CLK_CON_DIV_PCLK_ISP0, 0, 3, CLK_CON_DIV_PCLK_ISP0, 25, 1, 0);
|
|
CLK_DIV(ISP0_DIV_PCLK_ISP0_TPU, ISP0_MUX_ACLK_ISP0_TPU_400_USER, CLK_CON_DIV_PCLK_ISP0_TPU, 0, 3, CLK_CON_DIV_PCLK_ISP0_TPU, 25, 1, 0);
|
|
CLK_DIV(ISP0_DIV_PCLK_ISP0_TREX_264, ISP0_MUX_ACLK_ISP0_TREX_528_USER, CLK_CON_DIV_PCLK_ISP0_TREX_264, 0, 3, CLK_CON_DIV_PCLK_ISP0_TREX_264, 25, 1, 0);
|
|
CLK_DIV(ISP0_DIV_PCLK_ISP0_TREX_132, ISP0_MUX_ACLK_ISP0_TREX_528_USER, CLK_CON_DIV_PCLK_ISP0_TREX_132, 0, 3, CLK_CON_DIV_PCLK_ISP0_TREX_132, 25, 1, 0);
|
|
CLK_DIV(ISP1_DIV_PCLK_ISP1_234, ISP1_MUX_ACLK_ISP1_468_USER, CLK_CON_DIV_PCLK_ISP1_234, 0, 3, CLK_CON_DIV_PCLK_ISP1_234, 25, 1, 0);
|
|
CLK_DIV(MFC_DIV_PCLK_MFC_150, MFC_MUX_ACLK_MFC_600_USER, CLK_CON_DIV_PCLK_MFC_150, 0, 2, CLK_CON_DIV_PCLK_MFC_150, 25, 1, 0);
|
|
CLK_DIV(MIF0_DIV_PCLK_MIF, MIF0_MUX_PCLK_MIF, CLK_CON_DIV_PCLK_MIF0, 0, 3, CLK_CON_DIV_PCLK_MIF0, 25, 1, 0);
|
|
CLK_DIV(MIF0_DIV_SCLK_HPM_MIF, MIF0_MUX_SCLK_HPM_MIF, CLK_CON_DIV_SCLK_HPM_MIF0, 0, 2, CLK_CON_DIV_SCLK_HPM_MIF0, 25, 1, 0);
|
|
CLK_DIV(MIF1_DIV_PCLK_MIF, MIF1_MUX_PCLK_MIF, CLK_CON_DIV_PCLK_MIF1, 0, 3, CLK_CON_DIV_PCLK_MIF1, 25, 1, 0);
|
|
CLK_DIV(MIF1_DIV_SCLK_HPM_MIF, MIF1_MUX_SCLK_HPM_MIF, CLK_CON_DIV_SCLK_HPM_MIF1, 0, 2, CLK_CON_DIV_SCLK_HPM_MIF1, 25, 1, 0);
|
|
CLK_DIV(MIF2_DIV_PCLK_MIF, MIF2_MUX_PCLK_MIF, CLK_CON_DIV_PCLK_MIF2, 0, 3, CLK_CON_DIV_PCLK_MIF2, 25, 1, 0);
|
|
CLK_DIV(MIF2_DIV_SCLK_HPM_MIF, MIF2_MUX_SCLK_HPM_MIF, CLK_CON_DIV_SCLK_HPM_MIF2, 0, 2, CLK_CON_DIV_SCLK_HPM_MIF2, 25, 1, 0);
|
|
CLK_DIV(MIF3_DIV_PCLK_MIF, MIF3_MUX_PCLK_MIF, CLK_CON_DIV_PCLK_MIF3, 0, 3, CLK_CON_DIV_PCLK_MIF3, 25, 1, 0);
|
|
CLK_DIV(MIF3_DIV_SCLK_HPM_MIF, MIF3_MUX_SCLK_HPM_MIF, CLK_CON_DIV_SCLK_HPM_MIF3, 0, 2, CLK_CON_DIV_SCLK_HPM_MIF3, 25, 1, 0);
|
|
CLK_DIV(MIF0_DIV_PCLK_SMC, MIF0_MUX_PCLK_SMC, CLK_CON_DIV_PCLK_SMC_MIF0, 0, 3, CLK_CON_DIV_PCLK_SMC_MIF0, 25, 1, 0);
|
|
CLK_DIV(MIF1_DIV_PCLK_SMC, MIF1_MUX_PCLK_SMC, CLK_CON_DIV_PCLK_SMC_MIF1, 0, 3, CLK_CON_DIV_PCLK_SMC_MIF1, 25, 1, 0);
|
|
CLK_DIV(MIF2_DIV_PCLK_SMC, MIF2_MUX_PCLK_SMC, CLK_CON_DIV_PCLK_SMC_MIF2, 0, 3, CLK_CON_DIV_PCLK_SMC_MIF2, 25, 1, 0);
|
|
CLK_DIV(MIF3_DIV_PCLK_SMC, MIF3_MUX_PCLK_SMC, CLK_CON_DIV_PCLK_SMC_MIF3, 0, 3, CLK_CON_DIV_PCLK_SMC_MIF3, 25, 1, 0);
|
|
CLK_DIV(MNGS_DIV_MNGS, MNGS_MUX_MNGS, CLK_CON_DIV_MNGS, 0, 6, CLK_CON_DIV_MNGS, 25, 1, 0);
|
|
CLK_DIV(MNGS_DIV_ACLK_MNGS, MNGS_DIV_MNGS, CLK_CON_DIV_ACLK_MNGS, 0, 4, CLK_CON_DIV_ACLK_MNGS, 25, 1, 0);
|
|
CLK_DIV(MNGS_DIV_ATCLK_MNGS_CORE, MNGS_DIV_MNGS, CLK_CON_DIV_ATCLK_MNGS_CORE, 0, 4, CLK_CON_DIV_ATCLK_MNGS_CORE, 25, 1, 0);
|
|
CLK_DIV(MNGS_DIV_ATCLK_MNGS_SOC, MNGS_DIV_MNGS, CLK_CON_DIV_ATCLK_MNGS_SOC, 0, 6, CLK_CON_DIV_ATCLK_MNGS_SOC, 25, 1, 0);
|
|
CLK_DIV(MNGS_DIV_ATCLK_MNGS_CSSYS_TRACECLK, MNGS_DIV_ATCLK_MNGS_SOC, CLK_CON_DIV_ATCLK_MNGS_CSSYS_TRACECLK, 0, 4, CLK_CON_DIV_ATCLK_MNGS_CSSYS_TRACECLK, 25, 1, 0);
|
|
CLK_DIV(MNGS_DIV_ATCLK_MNGS_ASYNCATB_CAM1, MNGS_DIV_ATCLK_MNGS_SOC, CLK_CON_DIV_ATCLK_MNGS_ASYNCATB_CAM1, 0, 4, CLK_CON_DIV_ATCLK_MNGS_ASYNCATB_CAM1, 25, 1, 0);
|
|
CLK_DIV(MNGS_DIV_ATCLK_MNGS_ASYNCATB_AUD, MNGS_DIV_ATCLK_MNGS_SOC, CLK_CON_DIV_ATCLK_MNGS_ASYNCATB_AUD, 0, 4, CLK_CON_DIV_ATCLK_MNGS_ASYNCATB_AUD, 25, 1, 0);
|
|
CLK_DIV(MNGS_DIV_PCLK_DBG_MNGS, MNGS_DIV_MNGS, CLK_CON_DIV_PCLK_DBG_MNGS, 0, 6, CLK_CON_DIV_PCLK_DBG_MNGS, 25, 1, 0);
|
|
CLK_DIV(MNGS_DIV_PCLK_RUN_MONITOR, MNGS_DIV_PCLK_DBG_MNGS, CLK_CON_DIV_PCLK_RUN_MONITOR, 0, 3, CLK_CON_DIV_PCLK_RUN_MONITOR, 25, 1, 0);
|
|
CLK_DIV(MNGS_DIV_PCLK_MNGS, MNGS_DIV_MNGS, CLK_CON_DIV_PCLK_MNGS, 0, 6, CLK_CON_DIV_PCLK_MNGS, 25, 1, 0);
|
|
CLK_DIV(MNGS_DIV_CNTCLK_MNGS, MNGS_DIV_MNGS, CLK_CON_DIV_CNTCLK_MNGS, 0, 4, CLK_CON_DIV_CNTCLK_MNGS, 25, 1, 0);
|
|
CLK_DIV(MNGS_DIV_MNGS_RUN_MONITOR, MNGS_DIV_MNGS, CLK_CON_DIV_MNGS_RUN_MONITOR, 0, 3, CLK_CON_DIV_MNGS_RUN_MONITOR, 25, 1, 0);
|
|
CLK_DIV(MNGS_DIV_SCLK_PROMISE_MNGS, MNGS_MUX_MNGS, CLK_CON_DIV_SCLK_PROMISE_MNGS, 0, 3, CLK_CON_DIV_SCLK_PROMISE_MNGS, 25, 1, 0);
|
|
CLK_DIV(MNGS_DIV_MNGS_PLL, MNGS_MUX_MNGS, CLK_CON_DIV_MNGS_PLL, 0, 3, CLK_CON_DIV_MNGS_PLL, 25, 1, 0);
|
|
CLK_DIV(MSCL_DIV_PCLK_MSCL, MSCL_MUX_ACLK_MSCL0_528_USER, CLK_CON_DIV_PCLK_MSCL, 0, 3, CLK_CON_DIV_PCLK_MSCL, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CCORE_800, TOP_MUX_ACLK_CCORE_800, CLK_CON_DIV_ACLK_CCORE_800, 0, 4, CLK_CON_DIV_ACLK_CCORE_800, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CCORE_264, TOP_MUX_ACLK_CCORE_264, CLK_CON_DIV_ACLK_CCORE_264, 0, 4, CLK_CON_DIV_ACLK_CCORE_264, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CCORE_G3D_800, TOP_MUX_ACLK_CCORE_G3D_800, CLK_CON_DIV_ACLK_CCORE_G3D_800, 0, 4, CLK_CON_DIV_ACLK_CCORE_G3D_800, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CCORE_528, TOP_MUX_ACLK_CCORE_528, CLK_CON_DIV_ACLK_CCORE_528, 0, 4, CLK_CON_DIV_ACLK_CCORE_528, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CCORE_132, TOP_MUX_ACLK_CCORE_132, CLK_CON_DIV_ACLK_CCORE_132, 0, 4, CLK_CON_DIV_ACLK_CCORE_132, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_PCLK_CCORE_66, TOP_MUX_PCLK_CCORE_66, CLK_CON_DIV_PCLK_CCORE_66, 0, 4, CLK_CON_DIV_PCLK_CCORE_66, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_BUS0_528, TOP_MUX_ACLK_BUS0_528, CLK_CON_DIV_ACLK_BUS0_528, 0, 4, CLK_CON_DIV_ACLK_BUS0_528, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_BUS0_200, TOP_MUX_ACLK_BUS0_200, CLK_CON_DIV_ACLK_BUS0_200, 0, 4, CLK_CON_DIV_ACLK_BUS0_200, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_PCLK_BUS0_132, TOP_MUX_PCLK_BUS0_132, CLK_CON_DIV_PCLK_BUS0_132, 0, 4, CLK_CON_DIV_PCLK_BUS0_132, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_BUS1_528, TOP_MUX_ACLK_BUS1_528, CLK_CON_DIV_ACLK_BUS1_528, 0, 4, CLK_CON_DIV_ACLK_BUS1_528, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_PCLK_BUS1_132, TOP_MUX_PCLK_BUS1_132, CLK_CON_DIV_PCLK_BUS1_132, 0, 4, CLK_CON_DIV_PCLK_BUS1_132, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_DISP0_0_400, TOP_MUX_ACLK_DISP0_0_400, CLK_CON_DIV_ACLK_DISP0_0_400, 0, 4, CLK_CON_DIV_ACLK_DISP0_0_400, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_DISP0_1_400, TOP_MUX_ACLK_DISP0_1_400, CLK_CON_DIV_ACLK_DISP0_1_400, 0, 4, CLK_CON_DIV_ACLK_DISP0_1_400, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_DISP1_0_400, TOP_MUX_ACLK_DISP1_0_400, CLK_CON_DIV_ACLK_DISP1_0_400, 0, 4, CLK_CON_DIV_ACLK_DISP1_0_400, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_DISP1_1_400, TOP_MUX_ACLK_DISP1_1_400, CLK_CON_DIV_ACLK_DISP1_1_400, 0, 4, CLK_CON_DIV_ACLK_DISP1_1_400, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_MFC_600, TOP_MUX_ACLK_MFC_600, CLK_CON_DIV_ACLK_MFC_600, 0, 4, CLK_CON_DIV_ACLK_MFC_600, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_MSCL0_528, TOP_MUX_ACLK_MSCL0_528, CLK_CON_DIV_ACLK_MSCL0_528, 0, 4, CLK_CON_DIV_ACLK_MSCL0_528, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_MSCL1_528, TOP_MUX_ACLK_MSCL1_528, CLK_CON_DIV_ACLK_MSCL1_528, 0, 4, CLK_CON_DIV_ACLK_MSCL1_528, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_IMEM_266, TOP_MUX_ACLK_IMEM_266, CLK_CON_DIV_ACLK_IMEM_266, 0, 4, CLK_CON_DIV_ACLK_IMEM_266, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_IMEM_200, TOP_MUX_ACLK_IMEM_200, CLK_CON_DIV_ACLK_IMEM_200, 0, 4, CLK_CON_DIV_ACLK_IMEM_200, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_IMEM_100, TOP_MUX_ACLK_IMEM_100, CLK_CON_DIV_ACLK_IMEM_100, 0, 4, CLK_CON_DIV_ACLK_IMEM_100, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_FSYS0_200, TOP_MUX_ACLK_FSYS0_200, CLK_CON_DIV_ACLK_FSYS0_200, 0, 4, CLK_CON_DIV_ACLK_FSYS0_200, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_FSYS1_200, TOP_MUX_ACLK_FSYS1_200, CLK_CON_DIV_ACLK_FSYS1_200, 0, 4, CLK_CON_DIV_ACLK_FSYS1_200, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_PERIS_66, TOP_MUX_ACLK_PERIS_66, CLK_CON_DIV_ACLK_PERIS_66, 0, 4, CLK_CON_DIV_ACLK_PERIS_66, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_PERIC0_66, TOP_MUX_ACLK_PERIC0_66, CLK_CON_DIV_ACLK_PERIC0_66, 0, 4, CLK_CON_DIV_ACLK_PERIC0_66, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_PERIC1_66, TOP_MUX_ACLK_PERIC1_66, CLK_CON_DIV_ACLK_PERIC1_66, 0, 4, CLK_CON_DIV_ACLK_PERIC1_66, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_ISP0_ISP0_528, TOP_MUX_ACLK_ISP0_ISP0_528, CLK_CON_DIV_ACLK_ISP0_ISP0_528, 0, 4, CLK_CON_DIV_ACLK_ISP0_ISP0_528, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_ISP0_TPU_400, TOP_MUX_ACLK_ISP0_TPU_400, CLK_CON_DIV_ACLK_ISP0_TPU_400, 0, 4, CLK_CON_DIV_ACLK_ISP0_TPU_400, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_ISP0_TREX_528, TOP_MUX_ACLK_ISP0_TREX_528, CLK_CON_DIV_ACLK_ISP0_TREX_528, 0, 4, CLK_CON_DIV_ACLK_ISP0_TREX_528, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D, TOP_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D, CLK_CON_DIV_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_TOP, 0, 4, CLK_CON_DIV_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_TOP, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_ISP1_ISP1_468, TOP_MUX_ACLK_ISP1_ISP1_468, CLK_CON_DIV_ACLK_ISP1_ISP1_468, 0, 4, CLK_CON_DIV_ACLK_ISP1_ISP1_468, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CAM0_CSIS0_414, TOP_MUX_ACLK_CAM0_CSIS0_414, CLK_CON_DIV_ACLK_CAM0_CSIS0_414, 0, 4, CLK_CON_DIV_ACLK_CAM0_CSIS0_414, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CAM0_CSIS1_168, TOP_MUX_ACLK_CAM0_CSIS1_168, CLK_CON_DIV_ACLK_CAM0_CSIS1_168, 0, 4, CLK_CON_DIV_ACLK_CAM0_CSIS1_168, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CAM0_CSIS2_234, TOP_MUX_ACLK_CAM0_CSIS2_234, CLK_CON_DIV_ACLK_CAM0_CSIS2_234, 0, 4, CLK_CON_DIV_ACLK_CAM0_CSIS2_234, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CAM0_3AA0_414, TOP_MUX_ACLK_CAM0_3AA0_414, CLK_CON_DIV_ACLK_CAM0_3AA0_414, 0, 4, CLK_CON_DIV_ACLK_CAM0_3AA0_414, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CAM0_3AA1_414, TOP_MUX_ACLK_CAM0_3AA1_414, CLK_CON_DIV_ACLK_CAM0_3AA1_414, 0, 4, CLK_CON_DIV_ACLK_CAM0_3AA1_414, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CAM0_CSIS3_132, TOP_MUX_ACLK_CAM0_CSIS3_132, CLK_CON_DIV_ACLK_CAM0_CSIS3_132, 0, 4, CLK_CON_DIV_ACLK_CAM0_CSIS3_132, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CAM0_TREX_528, TOP_MUX_ACLK_CAM0_TREX_528, CLK_CON_DIV_ACLK_CAM0_TREX_528, 0, 4, CLK_CON_DIV_ACLK_CAM0_TREX_528, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CAM1_ARM_672, TOP_MUX_ACLK_CAM1_ARM_672, CLK_CON_DIV_ACLK_CAM1_ARM_672, 0, 4, CLK_CON_DIV_ACLK_CAM1_ARM_672, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CAM1_TREX_VRA_528, TOP_MUX_ACLK_CAM1_TREX_VRA_528, CLK_CON_DIV_ACLK_CAM1_TREX_VRA_528, 0, 4, CLK_CON_DIV_ACLK_CAM1_TREX_VRA_528, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CAM1_TREX_B_528, TOP_MUX_ACLK_CAM1_TREX_B_528, CLK_CON_DIV_ACLK_CAM1_TREX_B_528, 0, 4, CLK_CON_DIV_ACLK_CAM1_TREX_B_528, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CAM1_BUS_264, TOP_MUX_ACLK_CAM1_BUS_264, CLK_CON_DIV_ACLK_CAM1_BUS_264, 0, 4, CLK_CON_DIV_ACLK_CAM1_BUS_264, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CAM1_PERI_84, TOP_MUX_ACLK_CAM1_PERI_84, CLK_CON_DIV_ACLK_CAM1_PERI_84, 0, 4, CLK_CON_DIV_ACLK_CAM1_PERI_84, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CAM1_CSIS2_414, TOP_MUX_ACLK_CAM1_CSIS2_414, CLK_CON_DIV_ACLK_CAM1_CSIS2_414, 0, 8, CLK_CON_DIV_ACLK_CAM1_CSIS2_414, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CAM1_CSIS3_132, TOP_MUX_ACLK_CAM1_CSIS3_132, CLK_CON_DIV_ACLK_CAM1_CSIS3_132, 0, 4, CLK_CON_DIV_ACLK_CAM1_CSIS3_132, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_CAM1_SCL_566, TOP_MUX_ACLK_CAM1_SCL_566, CLK_CON_DIV_ACLK_CAM1_SCL_566, 0, 4, CLK_CON_DIV_ACLK_CAM1_SCL_566, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_DISP0_DECON0_ECLK0, TOP_MUX_SCLK_DISP0_DECON0_ECLK0, CLK_CON_DIV_SCLK_DISP0_DECON0_ECLK0, 0, 4, CLK_CON_DIV_SCLK_DISP0_DECON0_ECLK0, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_DISP0_DECON0_VCLK0, TOP_MUX_SCLK_DISP0_DECON0_VCLK0, CLK_CON_DIV_SCLK_DISP0_DECON0_VCLK0, 0, 4, CLK_CON_DIV_SCLK_DISP0_DECON0_VCLK0, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_DISP0_DECON0_VCLK1, TOP_MUX_SCLK_DISP0_DECON0_VCLK1, CLK_CON_DIV_SCLK_DISP0_DECON0_VCLK1, 0, 4, CLK_CON_DIV_SCLK_DISP0_DECON0_VCLK1, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_DISP0_HDMI_AUDIO, TOP_MUX_SCLK_DISP0_HDMI_AUDIO, CLK_CON_DIV_SCLK_DISP0_HDMI_AUDIO, 0, 4, CLK_CON_DIV_SCLK_DISP0_HDMI_AUDIO, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_DISP1_DECON1_ECLK0, TOP_MUX_SCLK_DISP1_DECON1_ECLK0, CLK_CON_DIV_SCLK_DISP1_DECON1_ECLK0, 0, 4, CLK_CON_DIV_SCLK_DISP1_DECON1_ECLK0, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_DISP1_DECON1_ECLK1, TOP_MUX_SCLK_DISP1_DECON1_ECLK1, CLK_CON_DIV_SCLK_DISP1_DECON1_ECLK1, 0, 4, CLK_CON_DIV_SCLK_DISP1_DECON1_ECLK1, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_FSYS0_USBDRD30, TOP_MUX_SCLK_FSYS0_USBDRD30, CLK_CON_DIV_SCLK_FSYS0_USBDRD30, 0, 4, CLK_CON_DIV_SCLK_FSYS0_USBDRD30, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_FSYS0_MMC0, TOP_MUX_SCLK_FSYS0_MMC0, CLK_CON_DIV_SCLK_FSYS0_MMC0, 0, 10, CLK_CON_DIV_SCLK_FSYS0_MMC0, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_FSYS0_UFSUNIPRO20, TOP_MUX_SCLK_FSYS0_UFSUNIPRO20, CLK_CON_DIV_SCLK_FSYS0_UFSUNIPRO20, 0, 6, CLK_CON_DIV_SCLK_FSYS0_UFSUNIPRO20, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_FSYS0_PHY_24M, TOP_MUX_SCLK_FSYS0_PHY_24M, CLK_CON_DIV_SCLK_FSYS0_PHY_24M, 0, 6, CLK_CON_DIV_SCLK_FSYS0_PHY_24M, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_FSYS0_UFSUNIPRO_CFG, TOP_MUX_SCLK_FSYS0_UFSUNIPRO_CFG, CLK_CON_DIV_SCLK_FSYS0_UFSUNIPRO_CFG, 0, 4, CLK_CON_DIV_SCLK_FSYS0_UFSUNIPRO_CFG, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_FSYS1_MMC2, TOP_MUX_SCLK_FSYS1_MMC2, CLK_CON_DIV_SCLK_FSYS1_MMC2, 0, 10, CLK_CON_DIV_SCLK_FSYS1_MMC2, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_FSYS1_UFSUNIPRO20, TOP_MUX_SCLK_FSYS1_UFSUNIPRO20, CLK_CON_DIV_SCLK_FSYS1_UFSUNIPRO20, 0, 6, CLK_CON_DIV_SCLK_FSYS1_UFSUNIPRO20, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_FSYS1_PCIE_PHY, TOP_MUX_SCLK_FSYS1_PCIE_PHY, CLK_CON_DIV_SCLK_FSYS1_PCIE_PHY, 0, 6, CLK_CON_DIV_SCLK_FSYS1_PCIE_PHY, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_FSYS1_UFSUNIPRO_CFG, TOP_MUX_SCLK_FSYS1_UFSUNIPRO_CFG, CLK_CON_DIV_SCLK_FSYS1_UFSUNIPRO_CFG, 0, 4, CLK_CON_DIV_SCLK_FSYS1_UFSUNIPRO_CFG, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PERIC0_UART0, TOP_MUX_SCLK_PERIC0_UART0, CLK_CON_DIV_SCLK_PERIC0_UART0, 0, 4, CLK_CON_DIV_SCLK_PERIC0_UART0, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PERIC1_SPI0, TOP_MUX_SCLK_PERIC1_SPI0, CLK_CON_DIV_SCLK_PERIC1_SPI0, 0, 4, CLK_CON_DIV_SCLK_PERIC1_SPI0, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PERIC1_SPI1, TOP_MUX_SCLK_PERIC1_SPI1, CLK_CON_DIV_SCLK_PERIC1_SPI1, 0, 4, CLK_CON_DIV_SCLK_PERIC1_SPI1, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PERIC1_SPI2, TOP_MUX_SCLK_PERIC1_SPI2, CLK_CON_DIV_SCLK_PERIC1_SPI2, 0, 4, CLK_CON_DIV_SCLK_PERIC1_SPI2, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PERIC1_SPI3, TOP_MUX_SCLK_PERIC1_SPI3, CLK_CON_DIV_SCLK_PERIC1_SPI3, 0, 4, CLK_CON_DIV_SCLK_PERIC1_SPI3, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PERIC1_SPI4, TOP_MUX_SCLK_PERIC1_SPI4, CLK_CON_DIV_SCLK_PERIC1_SPI4, 0, 4, CLK_CON_DIV_SCLK_PERIC1_SPI4, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PERIC1_SPI5, TOP_MUX_SCLK_PERIC1_SPI5, CLK_CON_DIV_SCLK_PERIC1_SPI5, 0, 4, CLK_CON_DIV_SCLK_PERIC1_SPI5, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PERIC1_SPI6, TOP_MUX_SCLK_PERIC1_SPI6, CLK_CON_DIV_SCLK_PERIC1_SPI6, 0, 4, CLK_CON_DIV_SCLK_PERIC1_SPI6, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PERIC1_SPI7, TOP_MUX_SCLK_PERIC1_SPI7, CLK_CON_DIV_SCLK_PERIC1_SPI7, 0, 4, CLK_CON_DIV_SCLK_PERIC1_SPI7, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PERIC1_UART1, TOP_MUX_SCLK_PERIC1_UART1, CLK_CON_DIV_SCLK_PERIC1_UART1, 0, 4, CLK_CON_DIV_SCLK_PERIC1_UART1, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PERIC1_UART2, TOP_MUX_SCLK_PERIC1_UART2, CLK_CON_DIV_SCLK_PERIC1_UART2, 0, 4, CLK_CON_DIV_SCLK_PERIC1_UART2, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PERIC1_UART3, TOP_MUX_SCLK_PERIC1_UART3, CLK_CON_DIV_SCLK_PERIC1_UART3, 0, 4, CLK_CON_DIV_SCLK_PERIC1_UART3, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PERIC1_UART4, TOP_MUX_SCLK_PERIC1_UART4, CLK_CON_DIV_SCLK_PERIC1_UART4, 0, 4, CLK_CON_DIV_SCLK_PERIC1_UART4, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PERIC1_UART5, TOP_MUX_SCLK_PERIC1_UART5, CLK_CON_DIV_SCLK_PERIC1_UART5, 0, 4, CLK_CON_DIV_SCLK_PERIC1_UART5, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_CAM1_ISP_SPI0, TOP_MUX_SCLK_CAM1_ISP_SPI0, CLK_CON_DIV_SCLK_CAM1_ISP_SPI0, 0, 4, CLK_CON_DIV_SCLK_CAM1_ISP_SPI0, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_CAM1_ISP_SPI1, TOP_MUX_SCLK_CAM1_ISP_SPI1, CLK_CON_DIV_SCLK_CAM1_ISP_SPI1, 0, 4, CLK_CON_DIV_SCLK_CAM1_ISP_SPI1, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_CAM1_ISP_UART, TOP_MUX_SCLK_CAM1_ISP_UART, CLK_CON_DIV_SCLK_CAM1_ISP_UART, 0, 4, CLK_CON_DIV_SCLK_CAM1_ISP_UART, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_AP2CP_MIF_PLL_OUT, TOP_MUX_SCLK_AP2CP_MIF_PLL_OUT, CLK_CON_DIV_SCLK_AP2CP_MIF_PLL_OUT, 0, 4, CLK_CON_DIV_SCLK_AP2CP_MIF_PLL_OUT, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_ACLK_PSCDC_400, TOP_MUX_ACLK_PSCDC_400, CLK_CON_DIV_ACLK_PSCDC_400, 0, 4, CLK_CON_DIV_ACLK_PSCDC_400, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_BUS_PLL_MNGS, TOP_MUX_SCLK_BUS_PLL_MNGS, CLK_CON_DIV_SCLK_BUS_PLL_MNGS, 0, 4, CLK_CON_DIV_SCLK_BUS_PLL_MNGS, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_BUS_PLL_APOLLO, TOP_MUX_SCLK_BUS_PLL_APOLLO, CLK_CON_DIV_SCLK_BUS_PLL_APOLLO, 0, 4, CLK_CON_DIV_SCLK_BUS_PLL_APOLLO, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_BUS_PLL_MIF, TOP_MUX_SCLK_BUS_PLL_MIF, CLK_CON_DIV_SCLK_BUS_PLL_MIF, 0, 4, CLK_CON_DIV_SCLK_BUS_PLL_MIF, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_BUS_PLL_G3D, TOP_MUX_SCLK_BUS_PLL_G3D, CLK_CON_DIV_SCLK_BUS_PLL_G3D, 0, 4, CLK_CON_DIV_SCLK_BUS_PLL_G3D, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_ISP_SENSOR0, TOP_MUX_SCLK_ISP_SENSOR0, CLK_CON_DIV_SCLK_ISP_SENSOR0, 0, 8, CLK_CON_DIV_SCLK_ISP_SENSOR0, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_ISP_SENSOR1, TOP_MUX_SCLK_ISP_SENSOR1, CLK_CON_DIV_SCLK_ISP_SENSOR1, 0, 8, CLK_CON_DIV_SCLK_ISP_SENSOR1, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_ISP_SENSOR2, TOP_MUX_SCLK_ISP_SENSOR2, CLK_CON_DIV_SCLK_ISP_SENSOR2, 0, 8, CLK_CON_DIV_SCLK_ISP_SENSOR2, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_ISP_SENSOR3, TOP_MUX_SCLK_ISP_SENSOR3, CLK_CON_DIV_SCLK_ISP_SENSOR3, 0, 8, CLK_CON_DIV_SCLK_ISP_SENSOR3, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PROMISE_INT, TOP_MUX_SCLK_PROMISE_INT, CLK_CON_DIV_SCLK_PROMISE_INT, 0, 4, CLK_CON_DIV_SCLK_PROMISE_INT, 25, 1, 0);
|
|
CLK_DIV(TOP_DIV_SCLK_PROMISE_DISP, TOP_MUX_SCLK_PROMISE_DISP, CLK_CON_DIV_SCLK_PROMISE_DISP, 0, 4, CLK_CON_DIV_SCLK_PROMISE_DISP, 25, 1, 0);
|
|
|
|
|
|
CLK_GATE(APOLLO_GATE_ACLK_ASYNCACES_APOLLO_CCI, APOLLO_DIV_ACLK_APOLLO, CLK_ENABLE_ACLK_APOLLO, 0);
|
|
CLK_GATE(APOLLO_GATE_ACLK_ASATBSLV_APOLLO3_CSSYS, APOLLO_DIV_ATCLK_APOLLO, CLK_ENABLE_ATCLK_APOLLO, 3);
|
|
CLK_GATE(APOLLO_GATE_ACLK_ASATBSLV_APOLLO2_CSSYS, APOLLO_DIV_ATCLK_APOLLO, CLK_ENABLE_ATCLK_APOLLO, 2);
|
|
CLK_GATE(APOLLO_GATE_ACLK_ASATBSLV_APOLLO1_CSSYS, APOLLO_DIV_ATCLK_APOLLO, CLK_ENABLE_ATCLK_APOLLO, 1);
|
|
CLK_GATE(APOLLO_GATE_ACLK_ASATBSLV_APOLLO0_CSSYS, APOLLO_DIV_ATCLK_APOLLO, CLK_ENABLE_ATCLK_APOLLO, 0);
|
|
CLK_GATE(APOLLO_GATE_PCLKDBG_DUMP_PC_APOLLO, APOLLO_DIV_PCLK_DBG_APOLLO, CLK_ENABLE_PCLK_DBG_APOLLO, 1);
|
|
CLK_GATE(APOLLO_GATE_PCLKDBG_ASAPBMST_CSSYS_APOLLO, APOLLO_DIV_PCLK_DBG_APOLLO, CLK_ENABLE_PCLK_DBG_APOLLO, 0);
|
|
CLK_GATE(APOLLO_GATE_PCLK_SYSREG_APOLLO, APOLLO_DIV_PCLK_APOLLO, CLK_ENABLE_PCLK_APOLLO, 3);
|
|
CLK_GATE(APOLLO_GATE_PCLK_PMU_APOLLO, APOLLO_DIV_PCLK_APOLLO, CLK_ENABLE_PCLK_APOLLO, 2);
|
|
CLK_GATE(APOLLO_GATE_PCLK_AXI2APB_APOLLO_ACLK, APOLLO_DIV_PCLK_APOLLO, CLK_ENABLE_PCLK_APOLLO, 1);
|
|
CLK_GATE(APOLLO_GATE_PCLK_XIU_PERI_APOLLO_ACLK, APOLLO_DIV_PCLK_APOLLO, CLK_ENABLE_PCLK_APOLLO, 0);
|
|
CLK_GATE(APOLLO_GATE_PCLK_HPM_APOLLO, APOLLO_DIV_PCLK_APOLLO, CLK_ENABLE_PCLK_HPM_APOLLO, 0);
|
|
CLK_GATE(APOLLO_GATE_SCLK_APOLLO, APOLLO_DIV_APOLLO, CLK_ENABLE_SCLK_APOLLO, 0);
|
|
CLK_GATE(APOLLO_GATE_SCLK_PROMISE_APOLLO, APOLLO_DIV_SCLK_PROMISE_APOLLO, CLK_ENABLE_SCLK_PROMISE_APOLLO, 0);
|
|
CLK_GATE(AUD_GATE_SCLK_CA5, AUD_MUX_ACLK_CA5, CLK_ENABLE_SCLK_CA5, 0);
|
|
CLK_GATE(AUD_GATE_PCLK_PPMU_AUD, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 20);
|
|
CLK_GATE(AUD_GATE_PCLK_CP_I2S, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 19);
|
|
CLK_GATE(AUD_GATE_PCLK_SYSREG_AUD, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 18);
|
|
CLK_GATE(AUD_GATE_PCLK_GPIO_AUD, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 17);
|
|
CLK_GATE(AUD_GATE_PCLK_PMU_AUD, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 16);
|
|
CLK_GATE(AUD_GATE_PCLK_SLIMBUS, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 15);
|
|
CLK_GATE(AUD_GATE_PCLK_PCM, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 14);
|
|
CLK_GATE(AUD_GATE_PCLK_I2S, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 13);
|
|
CLK_GATE(AUD_GATE_PCLK_TIMER, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 12);
|
|
CLK_GATE(AUD_GATE_PCLK_SFR1, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 11);
|
|
CLK_GATE(AUD_GATE_PCLK_SFR0, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 10);
|
|
CLK_GATE(AUD_GATE_PCLK_SMMU, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 9);
|
|
CLK_GATE(AUD_GATE_ACLK_PPMU_AUD, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 8);
|
|
CLK_GATE(AUD_GATE_ACLK_INTR, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 7);
|
|
CLK_GATE(AUD_GATE_ACLK_XIU_LPASSX, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 6);
|
|
CLK_GATE(AUD_GATE_ACLK_SMMU, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 5);
|
|
CLK_GATE(AUD_GATE_ACLK_AXI_LH_ASYNC_SI_TOP, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 4);
|
|
CLK_GATE(AUD_GATE_ACLK_AXI_LH_ASYNC_MI_TOP, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 3);
|
|
CLK_GATE(AUD_GATE_ACLK_AXI_US_32TO64, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 2);
|
|
CLK_GATE(AUD_GATE_ACLK_SRAMC, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 1);
|
|
CLK_GATE(AUD_GATE_ACLK_DMAC, AUD_DIV_ACLK_AUD, CLK_ENABLE_ACLK_AUD, 0);
|
|
CLK_GATE(AUD_GATE_PCLK_DBG, AUD_DIV_PCLK_DBG, CLK_ENABLE_PCLK_AUD, 0);
|
|
CLK_GATE(AUD_GATE_ACLK_ATCLK_AUD, AUD_DIV_ATCLK_AUD, CLK_ENABLE_ACLK_ATCLK_AUD, 0);
|
|
CLK_GATE(AUD_GATE_SCLK_I2S, AUD_DIV_SCLK_I2S, CLK_ENABLE_SCLK_I2S, 0);
|
|
CLK_GATE(AUD_GATE_SCLK_PCM, AUD_DIV_SCLK_PCM, CLK_ENABLE_SCLK_PCM, 0);
|
|
CLK_GATE(AUD_GATE_SCLK_SLIMBUS, AUD_DIV_SCLK_SLIMBUS, CLK_ENABLE_SCLK_SLIMBUS, 0);
|
|
CLK_GATE(AUD_GATE_SCLK_CP_I2S, AUD_DIV_SCLK_CP_I2S, CLK_ENABLE_SCLK_CP_I2S, 0);
|
|
CLK_GATE(AUD_GATE_SCLK_ASRC, AUD_DIV_SCLK_ASRC, CLK_ENABLE_SCLK_ASRC, 0);
|
|
CLK_GATE(AUD_GATE_SCLK_SLIMBUS_CLKIN, IOCLK_SLIMBUS_CLK, CLK_ENABLE_SCLK_SLIMBUS_CLKIN, 0);
|
|
CLK_GATE(AUD_GATE_SCLK_I2S_BCLK, IOCLK_I2S_BCLK, CLK_ENABLE_SCLK_I2S_BCLK, 0);
|
|
CLK_GATE(BUS0_GATE_ACLK_ACE_FSYS1, BUS0_MUX_ACLK_BUS0_528_USER, CG_CTRL_VAL_ACLK_BUS0_528_BUS0, 8);
|
|
CLK_GATE(BUS0_GATE_ACLK_LH_ISP0, BUS0_MUX_ACLK_BUS0_528_USER, CG_CTRL_VAL_ACLK_BUS0_528_BUS0, 7);
|
|
CLK_GATE(BUS0_GATE_ACLK_LH_DISP11, BUS0_MUX_ACLK_BUS0_528_USER, CG_CTRL_VAL_ACLK_BUS0_528_BUS0, 6);
|
|
CLK_GATE(BUS0_GATE_ACLK_LH_DISP10, BUS0_MUX_ACLK_BUS0_528_USER, CG_CTRL_VAL_ACLK_BUS0_528_BUS0, 5);
|
|
CLK_GATE(BUS0_GATE_ACLK_LH_DISP01, BUS0_MUX_ACLK_BUS0_528_USER, CG_CTRL_VAL_ACLK_BUS0_528_BUS0, 4);
|
|
CLK_GATE(BUS0_GATE_ACLK_LH_DISP00, BUS0_MUX_ACLK_BUS0_528_USER, CG_CTRL_VAL_ACLK_BUS0_528_BUS0, 3);
|
|
CLK_GATE(BUS0_GATE_ACLK_LH_CAM1, BUS0_MUX_ACLK_BUS0_528_USER, CG_CTRL_VAL_ACLK_BUS0_528_BUS0, 2);
|
|
CLK_GATE(BUS0_GATE_ACLK_LH_CAM0, BUS0_MUX_ACLK_BUS0_528_USER, CG_CTRL_VAL_ACLK_BUS0_528_BUS0, 1);
|
|
CLK_GATE(BUS0_GATE_ACLK_TREX_BUS0, BUS0_MUX_ACLK_BUS0_528_USER, CG_CTRL_VAL_ACLK_BUS0_528_BUS0, 0);
|
|
CLK_GATE(BUS0_GATE_ACLK_LH_FSYS1, BUS0_MUX_ACLK_BUS0_200_USER, CG_CTRL_VAL_ACLK_BUS0_200_BUS0, 0);
|
|
CLK_GATE(BUS0_GATE_PCLK_CMU_BUS0, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 16);
|
|
CLK_GATE(BUS0_GATE_PCLK_TREX_BUS0, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 15);
|
|
CLK_GATE(BUS0_GATE_PCLK_PMU_BUS0, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 14);
|
|
CLK_GATE(BUS0_GATE_PCLK_SYSREG_BUS0, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 13);
|
|
CLK_GATE(BUS0_GATE_PCLK_LH_FSYS1SFRX, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 12);
|
|
CLK_GATE(BUS0_GATE_PCLK_LH_PERIC1P, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 11);
|
|
CLK_GATE(BUS0_GATE_PCLK_LH_PERIC0P, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 10);
|
|
CLK_GATE(BUS0_GATE_PCLK_LH_PERISFRX, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 9);
|
|
CLK_GATE(BUS0_GATE_PCLK_LH_DISP1SFRX, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 8);
|
|
CLK_GATE(BUS0_GATE_PCLK_LH_DISP0SFRX, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 7);
|
|
CLK_GATE(BUS0_GATE_PCLK_LH_ISPHX, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 6);
|
|
CLK_GATE(BUS0_GATE_PCLK_LH_IS0X, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 5);
|
|
CLK_GATE(BUS0_GATE_PCLK_AXI2APB_2MB_BUS0_TP, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 4);
|
|
CLK_GATE(BUS0_GATE_PCLK_AHB2APB_BUS0P, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 3);
|
|
CLK_GATE(BUS0_GATE_PCLK_AXI2APB_2MB_BUS0_TD, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 2);
|
|
CLK_GATE(BUS0_GATE_PCLK_TREX_P_BUS0, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 1);
|
|
CLK_GATE(BUS0_GATE_ACLK_TREX_P_BUS0, BUS0_MUX_PCLK_BUS0_132_USER, CG_CTRL_VAL_PCLK_BUS0_132_BUS0, 0);
|
|
CLK_GATE(BUS1_GATE_ACLK_LH_MSCL1, BUS1_MUX_ACLK_BUS1_528_USER, CG_CTRL_VAL_ACLK_BUS1_528_BUS1, 5);
|
|
CLK_GATE(BUS1_GATE_ACLK_LH_MSCL0, BUS1_MUX_ACLK_BUS1_528_USER, CG_CTRL_VAL_ACLK_BUS1_528_BUS1, 4);
|
|
CLK_GATE(BUS1_GATE_ACLK_LH_MFC1, BUS1_MUX_ACLK_BUS1_528_USER, CG_CTRL_VAL_ACLK_BUS1_528_BUS1, 3);
|
|
CLK_GATE(BUS1_GATE_ACLK_LH_MFC0, BUS1_MUX_ACLK_BUS1_528_USER, CG_CTRL_VAL_ACLK_BUS1_528_BUS1, 2);
|
|
CLK_GATE(BUS1_GATE_ACLK_LH_FSYS0, BUS1_MUX_ACLK_BUS1_528_USER, CG_CTRL_VAL_ACLK_BUS1_528_BUS1, 1);
|
|
CLK_GATE(BUS1_GATE_ACLK_TREX_BUS1, BUS1_MUX_ACLK_BUS1_528_USER, CG_CTRL_VAL_ACLK_BUS1_528_BUS1, 0);
|
|
CLK_GATE(BUS1_GATE_PCLK_CMU_BUS1, BUS1_MUX_PCLK_BUS1_132_USER, CG_CTRL_VAL_PCLK_BUS1_132_BUS1, 11);
|
|
CLK_GATE(BUS1_GATE_PCLK_TREX_BUS1, BUS1_MUX_PCLK_BUS1_132_USER, CG_CTRL_VAL_PCLK_BUS1_132_BUS1, 10);
|
|
CLK_GATE(BUS1_GATE_PCLK_SYSREG_BUS1, BUS1_MUX_PCLK_BUS1_132_USER, CG_CTRL_VAL_PCLK_BUS1_132_BUS1, 9);
|
|
CLK_GATE(BUS1_GATE_PCLK_PMU_BUS1, BUS1_MUX_PCLK_BUS1_132_USER, CG_CTRL_VAL_PCLK_BUS1_132_BUS1, 8);
|
|
CLK_GATE(BUS1_GATE_PCLK_LH_MSCLSFRX, BUS1_MUX_PCLK_BUS1_132_USER, CG_CTRL_VAL_PCLK_BUS1_132_BUS1, 7);
|
|
CLK_GATE(BUS1_GATE_PCLK_LH_MFCP, BUS1_MUX_PCLK_BUS1_132_USER, CG_CTRL_VAL_PCLK_BUS1_132_BUS1, 6);
|
|
CLK_GATE(BUS1_GATE_PCLK_LH_FSYS0SFRX, BUS1_MUX_PCLK_BUS1_132_USER, CG_CTRL_VAL_PCLK_BUS1_132_BUS1, 5);
|
|
CLK_GATE(BUS1_GATE_PCLK_AHB2APB_BUS1P, BUS1_MUX_PCLK_BUS1_132_USER, CG_CTRL_VAL_PCLK_BUS1_132_BUS1, 4);
|
|
CLK_GATE(BUS1_GATE_PCLK_AXI2APB_2MB_BUS1_TP, BUS1_MUX_PCLK_BUS1_132_USER, CG_CTRL_VAL_PCLK_BUS1_132_BUS1, 3);
|
|
CLK_GATE(BUS1_GATE_PCLK_AXI2APB_2MB_BUS1_TD, BUS1_MUX_PCLK_BUS1_132_USER, CG_CTRL_VAL_PCLK_BUS1_132_BUS1, 2);
|
|
CLK_GATE(BUS1_GATE_PCLK_TREX_P_BUS1, BUS1_MUX_PCLK_BUS1_132_USER, CG_CTRL_VAL_PCLK_BUS1_132_BUS1, 1);
|
|
CLK_GATE(BUS1_GATE_ACLK_TREX_P_BUS1, BUS1_MUX_PCLK_BUS1_132_USER, CG_CTRL_VAL_PCLK_BUS1_132_BUS1, 0);
|
|
CLK_GATE(CAM0_GATE_ACLK_BNS, CAM0_MUX_ACLK_CAM0_CSIS0_414_USER, CLK_ENABLE_ACLK_CAM0_CSIS0_414, 2);
|
|
CLK_GATE(CAM0_GATE_ACLK_PXL_ASBS_CSIS2_int, CAM0_MUX_ACLK_CAM0_CSIS0_414_USER, CLK_ENABLE_ACLK_CAM0_CSIS0_414, 1);
|
|
CLK_GATE(CAM0_GATE_ACLK_CSIS0, CAM0_MUX_ACLK_CAM0_CSIS0_414_USER, CLK_ENABLE_ACLK_CAM0_CSIS0_414, 0);
|
|
CLK_GATE(CAM0_GATE_PCLK_BNS, CAM0_DIV_PCLK_CAM0_CSIS0_207, CLK_ENABLE_PCLK_CAM0_CSIS0_207, 0);
|
|
CLK_GATE(CAM0_GATE_ACLK_CSIS1, CAM0_MUX_ACLK_CAM0_CSIS1_168_USER, CLK_ENABLE_ACLK_CAM0_CSIS1_168_CAM0, 0);
|
|
CLK_GATE(CAM0_GATE_ACLK_CSIS2, CAM0_MUX_ACLK_CAM0_CSIS2_234_USER, CLK_ENABLE_ACLK_CAM0_CSIS2_234_CAM0, 0);
|
|
CLK_GATE(CAM0_GATE_ACLK_CSIS3, CAM0_MUX_ACLK_CAM0_CSIS3_132_USER, CLK_ENABLE_ACLK_CAM0_CSIS3_132_CAM0, 0);
|
|
CLK_GATE(CAM0_GATE_ACLK_3AA0, CAM0_MUX_ACLK_CAM0_3AA0_414_USER, CLK_ENABLE_ACLK_CAM0_3AA0_414_CAM0, 0);
|
|
CLK_GATE(CAM0_GATE_PCLK_3AA0, CAM0_DIV_PCLK_CAM0_3AA0_207, CLK_ENABLE_PCLK_CAM0_3AA0_207, 0);
|
|
CLK_GATE(CAM0_GATE_ACLK_3AA1, CAM0_MUX_ACLK_CAM0_3AA1_414_USER, CLK_ENABLE_ACLK_CAM0_3AA1_414_CAM0, 0);
|
|
CLK_GATE(CAM0_GATE_PCLK_3AA1, CAM0_DIV_PCLK_CAM0_3AA1_207, CLK_ENABLE_PCLK_CAM0_3AA1_207, 0);
|
|
CLK_GATE(CAM0_GATE_ACLK_SFW110_IS_A, CAM0_MUX_ACLK_CAM0_TREX_528_USER, CLK_ENABLE_ACLK_CAM0_TREX_528_CAM0, 3);
|
|
CLK_GATE(CAM0_GATE_ACLK_SysMMU6_IS_A, CAM0_MUX_ACLK_CAM0_TREX_528_USER, CLK_ENABLE_ACLK_CAM0_TREX_528_CAM0, 2);
|
|
CLK_GATE(CAM0_GATE_ACLK_TREX_A_5x1_IS_A, CAM0_MUX_ACLK_CAM0_TREX_528_USER, CLK_ENABLE_ACLK_CAM0_TREX_528_CAM0, 1);
|
|
CLK_GATE(CAM0_GATE_ACLK_LH_ASYNC_SI_CAM0, CAM0_MUX_ACLK_CAM0_TREX_528_USER, CLK_ENABLE_ACLK_CAM0_TREX_528_CAM0, 0);
|
|
CLK_GATE(CAM0_GATE_PCLK_PMU_CAM0, CAM0_DIV_PCLK_CAM0_TREX_264, CLK_ENABLE_PCLK_CAM0_TREX_264, 6);
|
|
CLK_GATE(CAM0_GATE_PCLK_SYSREG_CAM0, CAM0_DIV_PCLK_CAM0_TREX_264, CLK_ENABLE_PCLK_CAM0_TREX_264, 5);
|
|
CLK_GATE(CAM0_GATE_ACLK_LH_ASYNC_MI_CAM0, CAM0_DIV_PCLK_CAM0_TREX_264, CLK_ENABLE_PCLK_CAM0_TREX_264, 4);
|
|
CLK_GATE(CAM0_GATE_ACLK_XIUASYNC_MI_CAM0, CAM0_DIV_PCLK_CAM0_TREX_264, CLK_ENABLE_PCLK_CAM0_TREX_264, 3);
|
|
CLK_GATE(CAM0_GATE_PCLK_CAM0, CAM0_DIV_PCLK_CAM0_TREX_264, CLK_ENABLE_PCLK_CAM0_TREX_264, 2);
|
|
CLK_GATE(CAM0_GATE_PCLK_CSIS1, CAM0_DIV_PCLK_CAM0_TREX_264, CLK_ENABLE_PCLK_CAM0_TREX_264, 1);
|
|
CLK_GATE(CAM0_GATE_PCLK_CSIS0, CAM0_DIV_PCLK_CAM0_TREX_264, CLK_ENABLE_PCLK_CAM0_TREX_264, 0);
|
|
CLK_GATE(CAM0_GATE_PCLK_XIUASYNC_MI_CAM0, CAM0_DIV_PCLK_CAM0_TREX_132, CLK_ENABLE_PCLK_CAM0_TREX_132, 3);
|
|
CLK_GATE(CAM0_GATE_PCLK_TREX_A_5x1_IS_A, CAM0_DIV_PCLK_CAM0_TREX_264, CLK_ENABLE_PCLK_CAM0_TREX_264, 7);
|
|
CLK_GATE(CAM0_GATE_PCLK_SysMMU6_IS_A, CAM0_DIV_PCLK_CAM0_TREX_132, CLK_ENABLE_PCLK_CAM0_TREX_132, 1);
|
|
CLK_GATE(CAM0_GATE_PCLK_SFW110_IS_A_IS_A, CAM0_DIV_PCLK_CAM0_TREX_132, CLK_ENABLE_PCLK_CAM0_TREX_132, 0);
|
|
CLK_GATE(CAM0_GATE_SCLK_PROMISE_CAM0, TOP_GATE_SCLK_PROMISE_DISP, CLK_ENABLE_SCLK_PROMISE_CAM0, 0);
|
|
CLK_GATE(CAM0_GATE_PHYCLK_HS0_CSIS0_RX_BYTE, CAM0_MUX_PHYCLK_RXBYTECLKHS0_CSIS0_USER, CLK_ENABLE_PHYCLK_HS0_CSIS0_RX_BYTE, 0);
|
|
CLK_GATE(CAM0_GATE_PHYCLK_HS1_CSIS0_RX_BYTE, CAM0_MUX_PHYCLK_RXBYTECLKHS1_CSIS0_USER, CLK_ENABLE_PHYCLK_HS1_CSIS0_RX_BYTE, 0);
|
|
CLK_GATE(CAM0_GATE_PHYCLK_HS2_CSIS0_RX_BYTE, CAM0_MUX_PHYCLK_RXBYTECLKHS2_CSIS0_USER, CLK_ENABLE_PHYCLK_HS2_CSIS0_RX_BYTE, 0);
|
|
CLK_GATE(CAM0_GATE_PHYCLK_HS3_CSIS0_RX_BYTE, CAM0_MUX_PHYCLK_RXBYTECLKHS3_CSIS0_USER, CLK_ENABLE_PHYCLK_HS3_CSIS0_RX_BYTE, 0);
|
|
CLK_GATE(CAM0_GATE_PHYCLK_HS0_CSIS1_RX_BYTE, CAM0_MUX_PHYCLK_RXBYTECLKHS0_CSIS1_USER, CLK_ENABLE_PHYCLK_HS0_CSIS1_RX_BYTE, 0);
|
|
CLK_GATE(CAM0_GATE_PHYCLK_HS1_CSIS1_RX_BYTE, CAM0_MUX_PHYCLK_RXBYTECLKHS1_CSIS1_USER, CLK_ENABLE_PHYCLK_HS1_CSIS1_RX_BYTE, 0);
|
|
CLK_GATE(CAM0_GATE_PCLK_HPM_APBIF_CAM0, CAM0_DIV_PCLK_CAM0_TREX_264, CLK_ENABLE_PCLK_HPM_APBIF_CAM0, 0);
|
|
CLK_GATE(CAM0_LOCAL_GATE_ACLK_BNS, CAM0_GATE_ACLK_BNS, CLK_ENABLE_ACLK_CAM0_CSIS0_414_LOCAL, 2);
|
|
CLK_GATE(CAM0_LOCAL_GATE_ACLK_PXL_ASBS_CSIS2_int, CAM0_GATE_ACLK_PXL_ASBS_CSIS2_int, CLK_ENABLE_ACLK_CAM0_CSIS0_414_LOCAL, 1);
|
|
CLK_GATE(CAM0_LOCAL_GATE_ACLK_CSIS0, CAM0_GATE_ACLK_CSIS0, CLK_ENABLE_ACLK_CAM0_CSIS0_414_LOCAL, 0);
|
|
CLK_GATE(CAM0_LOCAL_GATE_PCLK_BNS, CAM0_GATE_PCLK_BNS, CLK_ENABLE_PCLK_CAM0_CSIS0_207_LOCAL, 0);
|
|
CLK_GATE(CAM0_LOCAL_GATE_ACLK_CSIS1, CAM0_GATE_ACLK_CSIS1, CLK_ENABLE_ACLK_CAM0_CSIS1_168_LOCAL, 0);
|
|
CLK_GATE(CAM0_LOCAL_GATE_ACLK_CSIS2, CAM0_GATE_ACLK_CSIS2, CLK_ENABLE_ACLK_CAM0_CSIS2_234_LOCAL, 0);
|
|
CLK_GATE(CAM0_LOCAL_GATE_ACLK_CSIS3, CAM0_GATE_ACLK_CSIS3, CLK_ENABLE_ACLK_CAM0_CSIS3_132_LOCAL, 0);
|
|
CLK_GATE(CAM0_LOCAL_GATE_ACLK_3AA0, CAM0_GATE_ACLK_3AA0, CLK_ENABLE_ACLK_CAM0_3AA0_414_LOCAL, 0);
|
|
CLK_GATE(CAM0_LOCAL_GATE_PCLK_3AA0, CAM0_GATE_PCLK_3AA0, CLK_ENABLE_PCLK_CAM0_3AA0_207_LOCAL, 0);
|
|
CLK_GATE(CAM0_LOCAL_GATE_ACLK_3AA1, CAM0_GATE_ACLK_3AA1, CLK_ENABLE_ACLK_CAM0_3AA1_414_LOCAL, 0);
|
|
CLK_GATE(CAM0_LOCAL_GATE_PCLK_3AA1, CAM0_GATE_PCLK_3AA1, CLK_ENABLE_PCLK_CAM0_3AA1_207_LOCAL, 0);
|
|
CLK_GATE(CAM0_LOCAL_GATE_PCLK_CSIS1, CAM0_GATE_PCLK_CSIS1, CLK_ENABLE_PCLK_CAM0_TREX_264_LOCAL, 1);
|
|
CLK_GATE(CAM0_LOCAL_GATE_PCLK_CSIS0, CAM0_GATE_PCLK_CSIS0, CLK_ENABLE_PCLK_CAM0_TREX_264_LOCAL, 0);
|
|
CLK_GATE(CAM1_GATE_ACLK_ARM, CAM1_MUX_ACLK_CAM1_ARM_672_USER, CLK_ENABLE_ACLK_CAM1_ARM_672_CAM1, 0);
|
|
CLK_GATE(CAM1_GATE_PCLK_ARM, CAM1_DIV_PCLK_CAM1_ARM_168, CLK_ENABLE_PCLK_CAM1_ARM_168, 0);
|
|
CLK_GATE(CAM1_GATE_ACLK_SMMU_VRA, CAM1_MUX_ACLK_CAM1_TREX_VRA_528_USER, CLK_ENABLE_ACLK_CAM1_TREX_VRA_528_CAM1, 1);
|
|
CLK_GATE(CAM1_GATE_ACLK_VRA, CAM1_MUX_ACLK_CAM1_TREX_VRA_528_USER, CLK_ENABLE_ACLK_CAM1_TREX_VRA_528_CAM1, 0);
|
|
CLK_GATE(CAM1_GATE_PCLK_VRA, CAM1_DIV_PCLK_CAM1_TREX_VRA_264, CLK_ENABLE_PCLK_CAM1_TREX_VRA_264, 0);
|
|
CLK_GATE(CAM1_GATE_ACLK_LH_SI, CAM1_MUX_ACLK_CAM1_TREX_B_528_USER, CLK_ENABLE_ACLK_CAM1_TREX_B_528_CAM1, 7);
|
|
CLK_GATE(CAM1_GATE_ACLK_TREX_CAM1, CAM1_MUX_ACLK_CAM1_TREX_B_528_USER, CLK_ENABLE_ACLK_CAM1_TREX_B_528_CAM1, 6);
|
|
CLK_GATE(CAM1_GATE_ACLK_XIU_from_ISP1, CAM1_MUX_ACLK_CAM1_TREX_B_528_USER, CLK_ENABLE_ACLK_CAM1_TREX_B_528_CAM1, 5);
|
|
CLK_GATE(CAM1_GATE_ACLK_SMMU_IS_B, CAM1_MUX_ACLK_CAM1_TREX_B_528_USER, CLK_ENABLE_ACLK_CAM1_TREX_B_528_CAM1, 4);
|
|
CLK_GATE(CAM1_GATE_ACLK_SFW, CAM1_MUX_ACLK_CAM1_TREX_B_528_USER, CLK_ENABLE_ACLK_CAM1_TREX_B_528_CAM1, 3);
|
|
CLK_GATE(CAM1_GATE_ACLK_ASYNC_CA7_TO_DRAM, CAM1_MUX_ACLK_CAM1_TREX_B_528_USER, CLK_ENABLE_ACLK_CAM1_TREX_B_528_CAM1, 2);
|
|
CLK_GATE(CAM1_GATE_ACLK_SMMU_ISPCPU, CAM1_MUX_ACLK_CAM1_TREX_B_528_USER, CLK_ENABLE_ACLK_CAM1_TREX_B_528_CAM1, 1);
|
|
CLK_GATE(CAM1_GATE_ACLK_TREX_B, CAM1_MUX_ACLK_CAM1_TREX_B_528_USER, CLK_ENABLE_ACLK_CAM1_TREX_B_528_CAM1, 0);
|
|
CLK_GATE(CAM1_GATE_ACLK_LH_MI, CAM1_MUX_ACLK_CAM1_BUS_264_USER, CLK_ENABLE_ACLK_CAM1_BUS_264_CAM1, 6);
|
|
CLK_GATE(CAM1_GATE_ACLK_PERI, CAM1_MUX_ACLK_CAM1_BUS_264_USER, CLK_ENABLE_ACLK_CAM1_BUS_264_CAM1, 5);
|
|
CLK_GATE(CAM1_GATE_PCLK_CSIS3, CAM1_MUX_ACLK_CAM1_BUS_264_USER, CLK_ENABLE_ACLK_CAM1_BUS_264_CAM1, 4);
|
|
CLK_GATE(CAM1_GATE_PCLK_CSIS2, CAM1_MUX_ACLK_CAM1_BUS_264_USER, CLK_ENABLE_ACLK_CAM1_BUS_264_CAM1, 3);
|
|
CLK_GATE(CAM1_GATE_ACLK_XIU_to_CAM0, CAM1_MUX_ACLK_CAM1_BUS_264_USER, CLK_ENABLE_ACLK_CAM1_BUS_264_CAM1, 2);
|
|
CLK_GATE(CAM1_GATE_ACLK_XIU_to_ISP1, CAM1_MUX_ACLK_CAM1_BUS_264_USER, CLK_ENABLE_ACLK_CAM1_BUS_264_CAM1, 1);
|
|
CLK_GATE(CAM1_GATE_ACLK_XIU_to_ISP0, CAM1_MUX_ACLK_CAM1_BUS_264_USER, CLK_ENABLE_ACLK_CAM1_BUS_264_CAM1, 0);
|
|
CLK_GATE(CAM1_GATE_PCLK_CMU_LOCAL, CAM1_DIV_PCLK_CAM1_BUS_132, CLK_ENABLE_PCLK_CAM1_BUS_132, 10);
|
|
CLK_GATE(CAM1_GATE_PCLK_SYSREG_CAM1, CAM1_DIV_PCLK_CAM1_BUS_132, CLK_ENABLE_PCLK_CAM1_BUS_132, 9);
|
|
CLK_GATE(CAM1_GATE_PCLK_PMU_CAM1, CAM1_DIV_PCLK_CAM1_BUS_132, CLK_ENABLE_PCLK_CAM1_BUS_132, 8);
|
|
CLK_GATE(CAM1_GATE_PCLK_TREX_CAM1, CAM1_DIV_PCLK_CAM1_BUS_132, CLK_ENABLE_PCLK_CAM1_BUS_132, 7);
|
|
CLK_GATE(CAM1_GATE_PCLK_XIU_from_ISP1, CAM1_DIV_PCLK_CAM1_BUS_132, CLK_ENABLE_PCLK_CAM1_BUS_132, 6);
|
|
CLK_GATE(CAM1_GATE_PCLK_PERI, CAM1_DIV_PCLK_CAM1_BUS_132, CLK_ENABLE_PCLK_CAM1_BUS_132, 5);
|
|
CLK_GATE(CAM1_GATE_PCLK_SMMU_ISPCPU, CAM1_DIV_PCLK_CAM1_BUS_132, CLK_ENABLE_PCLK_CAM1_BUS_132, 4);
|
|
CLK_GATE(CAM1_GATE_PCLK_SMMU_VRA, CAM1_DIV_PCLK_CAM1_BUS_132, CLK_ENABLE_PCLK_CAM1_BUS_132, 3);
|
|
CLK_GATE(CAM1_GATE_PCLK_SMMU_IS_B, CAM1_DIV_PCLK_CAM1_BUS_132, CLK_ENABLE_PCLK_CAM1_BUS_132, 2);
|
|
CLK_GATE(CAM1_GATE_PCLK_SFW, CAM1_DIV_PCLK_CAM1_BUS_132, CLK_ENABLE_PCLK_CAM1_BUS_132, 1);
|
|
CLK_GATE(CAM1_GATE_PCLK_TREX_B, CAM1_DIV_PCLK_CAM1_BUS_132, CLK_ENABLE_PCLK_CAM1_BUS_132, 0);
|
|
CLK_GATE(CAM1_GATE_PCLK_WDT, CAM1_MUX_ACLK_CAM1_PERI_84_USER, CLK_ENABLE_PCLK_CAM1_PERI_84, 11);
|
|
CLK_GATE(CAM1_GATE_PCLK_UART, CAM1_MUX_ACLK_CAM1_PERI_84_USER, CLK_ENABLE_PCLK_CAM1_PERI_84, 10);
|
|
CLK_GATE(CAM1_GATE_PCLK_SPI1, CAM1_MUX_ACLK_CAM1_PERI_84_USER, CLK_ENABLE_PCLK_CAM1_PERI_84, 9);
|
|
CLK_GATE(CAM1_GATE_PCLK_SPI0, CAM1_MUX_ACLK_CAM1_PERI_84_USER, CLK_ENABLE_PCLK_CAM1_PERI_84, 8);
|
|
CLK_GATE(CAM1_GATE_PCLK_PWM, CAM1_MUX_ACLK_CAM1_PERI_84_USER, CLK_ENABLE_PCLK_CAM1_PERI_84, 7);
|
|
CLK_GATE(CAM1_GATE_PCLK_MCUCTL, CAM1_MUX_ACLK_CAM1_PERI_84_USER, CLK_ENABLE_PCLK_CAM1_PERI_84, 6);
|
|
CLK_GATE(CAM1_GATE_PCLK_I2C3, CAM1_MUX_ACLK_CAM1_PERI_84_USER, CLK_ENABLE_PCLK_CAM1_PERI_84, 5);
|
|
CLK_GATE(CAM1_GATE_PCLK_I2C2, CAM1_MUX_ACLK_CAM1_PERI_84_USER, CLK_ENABLE_PCLK_CAM1_PERI_84, 4);
|
|
CLK_GATE(CAM1_GATE_PCLK_I2C1, CAM1_MUX_ACLK_CAM1_PERI_84_USER, CLK_ENABLE_PCLK_CAM1_PERI_84, 3);
|
|
CLK_GATE(CAM1_GATE_PCLK_I2C0, CAM1_MUX_ACLK_CAM1_PERI_84_USER, CLK_ENABLE_PCLK_CAM1_PERI_84, 2);
|
|
CLK_GATE(CAM1_GATE_ACLK_PDMA, CAM1_MUX_ACLK_CAM1_PERI_84_USER, CLK_ENABLE_PCLK_CAM1_PERI_84, 1);
|
|
CLK_GATE(CAM1_GATE_ACLK_BRIDGE_PERI, CAM1_MUX_ACLK_CAM1_PERI_84_USER, CLK_ENABLE_PCLK_CAM1_PERI_84, 0);
|
|
CLK_GATE(CAM1_GATE_ACLK_CSIS2, CAM1_MUX_ACLK_CAM1_CSIS2_414_USER, CLK_ENABLE_ACLK_CAM1_CSIS2_414_CAM1, 0);
|
|
CLK_GATE(CAM1_GATE_ACLK_CSIS3, CAM1_MUX_ACLK_CAM1_CSIS3_132_USER, CLK_ENABLE_ACLK_CAM1_CSIS3_132_CAM1, 0);
|
|
CLK_GATE(CAM1_GATE_ACLK_SMMU_MC_SC, CAM1_MUX_ACLK_CAM1_SCL_566_USER, CLK_ENABLE_ACLK_CAM1_SCL_566_CAM1, 1);
|
|
CLK_GATE(CAM1_GATE_ACLK_MC_SC, CAM1_MUX_ACLK_CAM1_SCL_566_USER, CLK_ENABLE_ACLK_CAM1_SCL_566_CAM1, 0);
|
|
CLK_GATE(CAM1_GATE_PCLK_SMMU_MC_SC, CAM1_DIV_PCLK_CAM1_BUS_132, CLK_ENABLE_PCLK_CAM1_MCS_132, 0);
|
|
CLK_GATE(CAM1_GATE_SCLK_ISP_PERI_IS_B_SPI0_EXT_CLK_ISP, CAM1_MUX_SCLK_CAM1_ISP_SPI0_USER, CLK_ENABLE_SCLK_CAM1_ISP_SPI0_CAM1, 0);
|
|
CLK_GATE(CAM1_GATE_SCLK_ISP_PERI_IS_B_SPI1_EXT_CLK_ISP, CAM1_MUX_SCLK_CAM1_ISP_SPI1_USER, CLK_ENABLE_SCLK_CAM1_ISP_SPI1_CAM1, 0);
|
|
CLK_GATE(CAM1_GATE_SCLK_ISP_PERI_IS_B_UART_EXT_CLK_ISP, CAM1_MUX_SCLK_CAM1_ISP_UART_USER, CLK_ENABLE_SCLK_CAM1_ISP_UART_CAM1, 0);
|
|
CLK_GATE(CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C3_ISP, OSCCLK, CLK_ENABLE_SCLK_ISP_PERI_IS_B, 4);
|
|
CLK_GATE(CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C2_ISP, OSCCLK, CLK_ENABLE_SCLK_ISP_PERI_IS_B, 3);
|
|
CLK_GATE(CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C1_ISP, OSCCLK, CLK_ENABLE_SCLK_ISP_PERI_IS_B, 2);
|
|
CLK_GATE(CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C0_ISP, OSCCLK, CLK_ENABLE_SCLK_ISP_PERI_IS_B, 1);
|
|
CLK_GATE(CAM1_GATE_SCLK_ISP_PERI_IS_B_PWM_ISP, OSCCLK, CLK_ENABLE_SCLK_ISP_PERI_IS_B, 0);
|
|
CLK_GATE(CAM1_GATE_PHYCLK_HS0_CSIS2_RX_BYTE, CAM1_MUX_PHYCLK_RXBYTECLKHS0_CSIS2_USER, CLK_ENABLE_PHYCLK_HS0_CSIS2_RX_BYTE, 0);
|
|
CLK_GATE(CAM1_GATE_PHYCLK_HS1_CSIS2_RX_BYTE, CAM1_MUX_PHYCLK_RXBYTECLKHS1_CSIS2_USER, CLK_ENABLE_PHYCLK_HS1_CSIS2_RX_BYTE, 0);
|
|
CLK_GATE(CAM1_GATE_PHYCLK_HS2_CSIS2_RX_BYTE, CAM1_MUX_PHYCLK_RXBYTECLKHS2_CSIS2_USER, CLK_ENABLE_PHYCLK_HS2_CSIS2_RX_BYTE, 0);
|
|
CLK_GATE(CAM1_GATE_PHYCLK_HS3_CSIS2_RX_BYTE, CAM1_MUX_PHYCLK_RXBYTECLKHS3_CSIS2_USER, CLK_ENABLE_PHYCLK_HS3_CSIS2_RX_BYTE, 0);
|
|
CLK_GATE(CAM1_GATE_PHYCLK_HS0_CSIS3_RX_BYTE, CAM1_MUX_PHYCLK_RXBYTECLKHS0_CSIS3_USER, CLK_ENABLE_PHYCLK_HS0_CSIS3_RX_BYTE, 0);
|
|
CLK_GATE(CAM1_LOCAL_GATE_ACLK_VRA, CAM1_GATE_ACLK_VRA, CLK_ENABLE_ACLK_CAM1_TREX_VRA_528_LOCAL, 0);
|
|
CLK_GATE(CAM1_LOCAL_GATE_PCLK_VRA, CAM1_GATE_PCLK_VRA, CLK_ENABLE_PCLK_CAM1_TREX_VRA_264_LOCAL, 0);
|
|
CLK_GATE(CAM1_LOCAL_GATE_PCLK_CSIS3, CAM1_GATE_PCLK_CSIS3, CLK_ENABLE_ACLK_CAM1_BUS_264_LOCAL, 4);
|
|
CLK_GATE(CAM1_LOCAL_GATE_PCLK_CSIS2, CAM1_GATE_PCLK_CSIS2, CLK_ENABLE_ACLK_CAM1_BUS_264_LOCAL, 3);
|
|
CLK_GATE(CAM1_LOCAL_GATE_PCLK_WDT, CAM1_GATE_PCLK_WDT, CLK_ENABLE_PCLK_CAM1_PERI_84_LOCAL, 11);
|
|
CLK_GATE(CAM1_LOCAL_GATE_PCLK_UART, CAM1_GATE_PCLK_UART, CLK_ENABLE_PCLK_CAM1_PERI_84_LOCAL, 10);
|
|
CLK_GATE(CAM1_LOCAL_GATE_PCLK_SPI1, CAM1_GATE_PCLK_SPI1, CLK_ENABLE_PCLK_CAM1_PERI_84_LOCAL, 9);
|
|
CLK_GATE(CAM1_LOCAL_GATE_PCLK_SPI0, CAM1_GATE_PCLK_SPI0, CLK_ENABLE_PCLK_CAM1_PERI_84_LOCAL, 8);
|
|
CLK_GATE(CAM1_LOCAL_GATE_PCLK_PWM, CAM1_GATE_PCLK_PWM, CLK_ENABLE_PCLK_CAM1_PERI_84_LOCAL, 7);
|
|
CLK_GATE(CAM1_LOCAL_GATE_PCLK_MCUCTL, CAM1_GATE_PCLK_MCUCTL, CLK_ENABLE_PCLK_CAM1_PERI_84_LOCAL, 6);
|
|
CLK_GATE(CAM1_LOCAL_GATE_PCLK_I2C3, CAM1_GATE_PCLK_I2C3, CLK_ENABLE_PCLK_CAM1_PERI_84_LOCAL, 5);
|
|
CLK_GATE(CAM1_LOCAL_GATE_PCLK_I2C2, CAM1_GATE_PCLK_I2C2, CLK_ENABLE_PCLK_CAM1_PERI_84_LOCAL, 4);
|
|
CLK_GATE(CAM1_LOCAL_GATE_PCLK_I2C1, CAM1_GATE_PCLK_I2C1, CLK_ENABLE_PCLK_CAM1_PERI_84_LOCAL, 3);
|
|
CLK_GATE(CAM1_LOCAL_GATE_PCLK_I2C0, CAM1_GATE_PCLK_I2C0, CLK_ENABLE_PCLK_CAM1_PERI_84_LOCAL, 2);
|
|
CLK_GATE(CAM1_LOCAL_GATE_ACLK_PDMA, CAM1_GATE_ACLK_PDMA, CLK_ENABLE_PCLK_CAM1_PERI_84_LOCAL, 1);
|
|
CLK_GATE(CAM1_LOCAL_GATE_ACLK_CSIS2, CAM1_GATE_ACLK_CSIS2, CLK_ENABLE_ACLK_CAM1_CSIS2_414_LOCAL, 0);
|
|
CLK_GATE(CAM1_LOCAL_GATE_ACLK_CSIS3, CAM1_GATE_ACLK_CSIS3, CLK_ENABLE_ACLK_CAM1_CSIS3_132_LOCAL, 0);
|
|
CLK_GATE(CAM1_LOCAL_GATE_ACLK_MC_SC, CAM1_GATE_ACLK_MC_SC, CLK_ENABLE_ACLK_CAM1_SCL_566_LOCAL, 0);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_AS_SI_IRPM, CCORE_MUX_ACLK_CCORE_800_USER, CG_CTRL_VAL_ACLK_CCORE0, 11);
|
|
CLK_GATE(CCORE_GATE_ACLK_MPACEBRIDGE, CCORE_MUX_ACLK_CCORE_800_USER, CG_CTRL_VAL_ACLK_CCORE0, 10);
|
|
CLK_GATE(CCORE_GATE_ACLK_PULSE2HS, CCORE_MUX_ACLK_CCORE_800_USER, CG_CTRL_VAL_ACLK_CCORE0, 9);
|
|
CLK_GATE(CCORE_GATE_ACLK_DBG_LH_MI_MIF_CCORE, CCORE_MUX_ACLK_CCORE_800_USER, CG_CTRL_VAL_ACLK_CCORE0, 8);
|
|
CLK_GATE(CCORE_GATE_ACLK_SCI_PPC_WRAPPER, CCORE_MUX_ACLK_CCORE_800_USER, CG_CTRL_VAL_ACLK_CCORE0, 7);
|
|
CLK_GATE(CCORE_GATE_ACLK_ACE_AS_MI_APL_CCORE, CCORE_MUX_ACLK_CCORE_800_USER, CG_CTRL_VAL_ACLK_CCORE0, 6);
|
|
CLK_GATE(CCORE_GATE_ACLK_MPACE_SI, CCORE_MUX_ACLK_CCORE_800_USER, CG_CTRL_VAL_ACLK_CCORE0, 5);
|
|
CLK_GATE(CCORE_GATE_ACLK_CPACE_MI, CCORE_MUX_ACLK_CCORE_800_USER, CG_CTRL_VAL_ACLK_CCORE0, 4);
|
|
CLK_GATE(CCORE_GATE_ACLK_ATB_SI_CCOREBDU_MNGSCS, CCORE_MUX_ACLK_CCORE_800_USER, CG_CTRL_VAL_ACLK_CCORE0, 3);
|
|
CLK_GATE(CCORE_GATE_ACLK_BDU, CCORE_MUX_ACLK_CCORE_800_USER, CG_CTRL_VAL_ACLK_CCORE0, 2);
|
|
CLK_GATE(CCORE_GATE_ACLK_TREX_CCORE_SCI, CCORE_MUX_ACLK_CCORE_800_USER, CG_CTRL_VAL_ACLK_CCORE0, 1);
|
|
CLK_GATE(CCORE_GATE_ACLK_SCI, CCORE_MUX_ACLK_CCORE_800_USER, CG_CTRL_VAL_ACLK_CCORE0, 0);
|
|
CLK_GATE(CCORE_GATE_ACLK_CLEANY_CPPERI, CCORE_MUX_ACLK_CCORE_264_USER, CG_CTRL_VAL_ACLK_CCORE1, 9);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_US_CPPERI, CCORE_MUX_ACLK_CCORE_264_USER, CG_CTRL_VAL_ACLK_CCORE1, 8);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_LH_MI_CPPERI_CCORE, CCORE_MUX_ACLK_CCORE_264_USER, CG_CTRL_VAL_ACLK_CCORE1, 7);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_LH_SI_CCORESFRX_IMEMX, CCORE_MUX_ACLK_CCORE_264_USER, CG_CTRL_VAL_ACLK_CCORE1, 6);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_LH_MI_G3DXIRAM_CCORESFR, CCORE_MUX_ACLK_CCORE_264_USER, CG_CTRL_VAL_ACLK_CCORE1, 5);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_DS_IRPM, CCORE_MUX_ACLK_CCORE_264_USER, CG_CTRL_VAL_ACLK_CCORE1, 4);
|
|
CLK_GATE(CCORE_GATE_ACLK_XIU_CCORESFRX, CCORE_MUX_ACLK_CCORE_264_USER, CG_CTRL_VAL_ACLK_CCORE1, 3);
|
|
CLK_GATE(CCORE_GATE_ACLK_TREX_P_CCORE_BUS, CCORE_MUX_ACLK_CCORE_264_USER, CG_CTRL_VAL_ACLK_CCORE1, 2);
|
|
CLK_GATE(CCORE_GATE_ACLK_TREX_CCORE_PERI, CCORE_MUX_ACLK_CCORE_264_USER, CG_CTRL_VAL_ACLK_CCORE1, 1);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_AS_MI_IRPM, CCORE_MUX_ACLK_CCORE_264_USER, CG_CTRL_VAL_ACLK_CCORE1, 0);
|
|
CLK_GATE(CCORE_GATE_ACLK_TREX_CCORE_G3D, CCORE_MUX_ACLK_CCORE_G3D_800_USER, CG_CTRL_VAL_ACLK_CCORE2, 2);
|
|
CLK_GATE(CCORE_GATE_ACLK_ACEL_LH_MI_G3DX1_CCORETD, CCORE_MUX_ACLK_CCORE_G3D_800_USER, CG_CTRL_VAL_ACLK_CCORE2, 1);
|
|
CLK_GATE(CCORE_GATE_ACLK_ACEL_LH_MI_G3DX0_CCORETD, CCORE_MUX_ACLK_CCORE_G3D_800_USER, CG_CTRL_VAL_ACLK_CCORE2, 0);
|
|
CLK_GATE(CCORE_GATE_ACLK_ATB_APL_MNGS, CCORE_MUX_ACLK_CCORE_528_USER, CG_CTRL_VAL_ACLK_CCORE3, 7);
|
|
CLK_GATE(CCORE_GATE_ACLK_XIU_CPX, CCORE_MUX_ACLK_CCORE_528_USER, CG_CTRL_VAL_ACLK_CCORE3, 6);
|
|
CLK_GATE(CCORE_GATE_ACLK_CLEANY_CPDATA, CCORE_MUX_ACLK_CCORE_528_USER, CG_CTRL_VAL_ACLK_CCORE3, 5);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_LH_MI_CPDATA_CCORE, CCORE_MUX_ACLK_CCORE_528_USER, CG_CTRL_VAL_ACLK_CCORE3, 4);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_LH_MI_IMEMX_CCORETD, CCORE_MUX_ACLK_CCORE_528_USER, CG_CTRL_VAL_ACLK_CCORE3, 3);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_LH_MI_AUDX_CCORETD, CCORE_MUX_ACLK_CCORE_528_USER, CG_CTRL_VAL_ACLK_CCORE3, 2);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_AS_MI_MNGSCS_CCORETD, CCORE_MUX_ACLK_CCORE_528_USER, CG_CTRL_VAL_ACLK_CCORE3, 1);
|
|
CLK_GATE(CCORE_GATE_ACLK_TREX_CCORE, CCORE_MUX_ACLK_CCORE_528_USER, CG_CTRL_VAL_ACLK_CCORE3, 0);
|
|
CLK_GATE(CCORE_GATE_PCLK_CMU, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 30);
|
|
CLK_GATE(CCORE_GATE_PCLK_HPM_APBIF, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 29);
|
|
CLK_GATE(CCORE_GATE_PCLK_SCI, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 28);
|
|
CLK_GATE(CCORE_GATE_PCLK_GPIO_CCORE, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 27);
|
|
CLK_GATE(CCORE_GATE_PCLK_S_MAILBOX, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 26);
|
|
CLK_GATE(CCORE_GATE_PCLK_MAILBOX, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 25);
|
|
CLK_GATE(CCORE_GATE_PCLK_SYSREG_CCORE, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 24);
|
|
CLK_GATE(CCORE_GATE_PCLK_GPIO_APBIF_ALIVE, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 23);
|
|
CLK_GATE(CCORE_GATE_PCLK_SCI_PPC_WRAPPER, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 22);
|
|
CLK_GATE(CCORE_GATE_PCLK_VT_MON_APB, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 21);
|
|
CLK_GATE(CCORE_GATE_PCLK_PMU_CCORE, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 20);
|
|
CLK_GATE(CCORE_GATE_PCLK_PMU_APBIF, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 19);
|
|
CLK_GATE(CCORE_GATE_PCLK_CMU_TOPC_APBIF, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 18);
|
|
CLK_GATE(CCORE_GATE_PCLK_AXI2APB_CORESIGHT, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 17);
|
|
CLK_GATE(CCORE_GATE_PCLK_AXI2APB_TREX_P_CCORE, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 16);
|
|
CLK_GATE(CCORE_GATE_PCLK_AXI2APB_TREX_CCORE, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 15);
|
|
CLK_GATE(CCORE_GATE_PCLK_AXI2APB_CCORE, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 14);
|
|
CLK_GATE(CCORE_GATE_PCLK_TREX_P_CCORE, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 13);
|
|
CLK_GATE(CCORE_GATE_PCLK_TREX_CCORE, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 12);
|
|
CLK_GATE(CCORE_GATE_PCLK_BDU, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 11);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF3P, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 10);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF2P, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 9);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF1P, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 8);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF0P, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 7);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_G3DP, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 6);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_AUDX, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 5);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_AS_SI_CCORETP_APL, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 4);
|
|
CLK_GATE(CCORE_GATE_ACLK_AXI_AS_SI_CCORETP_MNGS, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 3);
|
|
CLK_GATE(CCORE_GATE_ACLK_APB_AS_MI_CCORETP_MNGSCS, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 2);
|
|
CLK_GATE(CCORE_GATE_ACLK_APB_AS_MI_MNGSCS_CCOREBDU, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 1);
|
|
CLK_GATE(CCORE_GATE_ACLK_TREX_P_CCORE, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE4, 0);
|
|
CLK_GATE(CCORE_GATE_PCLK_APBASYNC_BAT_AP, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE_AP, 0);
|
|
CLK_GATE(CCORE_GATE_PCLK_APBASYNC_BAT_CP, CCORE_MUX_ACLK_CCORE_132_USER, CG_CTRL_VAL_ACLK_CCORE_CP, 0);
|
|
CLK_GATE(CCORE_GATE_PCLK_HSI2C_BAT_AP, CCORE_MUX_PCLK_CCORE_66_USER, CG_CTRL_VAL_PCLK_CCORE_AP, 1);
|
|
CLK_GATE(CCORE_GATE_PCLK_HSI2C, CCORE_MUX_PCLK_CCORE_66_USER, CG_CTRL_VAL_PCLK_CCORE_AP, 0);
|
|
CLK_GATE(CCORE_GATE_PCLK_HSI2C_BAT_CP, CCORE_MUX_PCLK_CCORE_66_USER, CG_CTRL_VAL_PCLK_CCORE_CP, 1);
|
|
CLK_GATE(CCORE_GATE_PCLK_HSI2C_CP, CCORE_MUX_PCLK_CCORE_66_USER, CG_CTRL_VAL_PCLK_CCORE_CP, 0);
|
|
CLK_GATE(CCORE_GATE_SCLK_PROMISE, CCORE_DIV_SCLK_HPM_CCORE, CG_CTRL_VAL_SCLK_HPM_CCORE, 0);
|
|
CLK_GATE(DISP0_GATE_ACLK_PPMU_DISP0_0, DISP0_MUX_ACLK_DISP0_0_400_USER, CG_CTRL_VAL_ACLK_DISP0_0_400, 5);
|
|
CLK_GATE(DISP0_GATE_ACLK_SMMU_DISP0_0, DISP0_MUX_ACLK_DISP0_0_400_USER, CG_CTRL_VAL_ACLK_DISP0_0_400, 3);
|
|
CLK_GATE(DISP0_GATE_ACLK_XIU_DISP0_0, DISP0_MUX_ACLK_DISP0_0_400_USER, CG_CTRL_VAL_ACLK_DISP0_0_400, 2);
|
|
CLK_GATE(DISP0_GATE_ACLK_LH_ASYNC_SI_R_TOP_DISP, DISP0_MUX_ACLK_DISP0_0_400_USER, CG_CTRL_VAL_ACLK_DISP0_0_400, 1);
|
|
CLK_GATE(DISP0_GATE_ACLK_VPP0_ACLK_0, DISP0_MUX_ACLK_DISP0_0_400_USER, CG_CTRL_VAL_ACLK_DISP0_0_400, 0);
|
|
CLK_GATE(DISP0_GATE_ACLK_PPMU_DISP0_1, DISP0_MUX_ACLK_DISP0_1_400, CG_CTRL_VAL_ACLK_DISP0_1_400, 5);
|
|
CLK_GATE(DISP0_GATE_ACLK_SMMU_DISP0_1, DISP0_MUX_ACLK_DISP0_1_400, CG_CTRL_VAL_ACLK_DISP0_1_400, 3);
|
|
CLK_GATE(DISP0_GATE_ACLK_XIU_DISP0_1, DISP0_MUX_ACLK_DISP0_1_400, CG_CTRL_VAL_ACLK_DISP0_1_400, 2);
|
|
CLK_GATE(DISP0_GATE_ACLK_LH_ASYNC_SI_TOP_DISP, DISP0_MUX_ACLK_DISP0_1_400, CG_CTRL_VAL_ACLK_DISP0_1_400, 1);
|
|
CLK_GATE(DISP0_GATE_ACLK_VPP0_ACLK_1, DISP0_MUX_ACLK_DISP0_1_400, CG_CTRL_VAL_ACLK_DISP0_1_400, 0);
|
|
CLK_GATE(DISP0_GATE_ACLK_SFW_DISP0_0, DISP0_MUX_ACLK_DISP0_0_400_USER, CG_CTRL_VAL_ACLK_DISP0_0_400_SECURE_SFW_DISP0_0, 0);
|
|
CLK_GATE(DISP0_GATE_ACLK_SFW_DISP0_1, DISP0_MUX_ACLK_DISP0_1_400, CG_CTRL_VAL_ACLK_DISP0_1_400_SECURE_SFW_DISP0_1, 0);
|
|
CLK_GATE(DISP0_GATE_PCLK_VPP0_1, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 19);
|
|
CLK_GATE(DISP0_GATE_PCLK_SMMU_DISP0_1, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 18);
|
|
CLK_GATE(DISP0_GATE_PCLK_SMMU_DISP0_0, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 17);
|
|
CLK_GATE(DISP0_GATE_PCLK_PPMU_DISP0_1, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 16);
|
|
CLK_GATE(DISP0_GATE_PCLK_PPMU_DISP0_0, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 15);
|
|
CLK_GATE(DISP0_GATE_PCLK_HDMI_PHY, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 14);
|
|
CLK_GATE(DISP0_GATE_PCLK_DISP0_MUX, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 13);
|
|
CLK_GATE(DISP0_GATE_PCLK_DP, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 12);
|
|
CLK_GATE(DISP0_GATE_PCLK_HDMI_AUDIO, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 11);
|
|
CLK_GATE(DISP0_GATE_PCLK_HDMI, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 10);
|
|
CLK_GATE(DISP0_GATE_PCLK_DSIM2, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 9);
|
|
CLK_GATE(DISP0_GATE_PCLK_DSIM1, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 8);
|
|
CLK_GATE(DISP0_GATE_PCLK_DSIM0, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 7);
|
|
CLK_GATE(DISP0_GATE_PCLK_SYSREG_DISP0, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 6);
|
|
CLK_GATE(DISP0_GATE_PCLK_PMU_DISP0, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 5);
|
|
CLK_GATE(DISP0_GATE_PCLK_CMU_DISP0, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 4);
|
|
CLK_GATE(DISP0_GATE_ACLK_XIU_DISP0SFRX, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 3);
|
|
CLK_GATE(DISP0_GATE_ACLK_AXI2APB_DISP0_1P, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 2);
|
|
CLK_GATE(DISP0_GATE_ACLK_AXI2APB_DISP0_0P, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 1);
|
|
CLK_GATE(DISP0_GATE_ACLK_AXI_LH_ASYNC_MI_DISP0SFR, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133, 0);
|
|
CLK_GATE(DISP0_GATE_PCLK_HPM_APBIF_DISP0, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133_HPM_APBIF_DISP0, 0);
|
|
CLK_GATE(DISP0_GATE_PCLK_DECON0, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133_SECURE_DECON0, 0);
|
|
CLK_GATE(DISP0_GATE_PCLK_VPP0_0, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133_SECURE_VPP0, 0);
|
|
CLK_GATE(DISP0_GATE_PCLK_SFW_DISP0_0, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133_SECURE_SFW_DISP0_0, 0);
|
|
CLK_GATE(DISP0_GATE_PCLK_SFW_DISP0_1, DISP0_DIV_PCLK_DISP0_0_133, CG_CTRL_VAL_PCLK_DISP0_0_133_SECURE_SFW_DISP0_1, 0);
|
|
CLK_GATE(DISP0_GATE_SCLK_DISP1_400, DISP0_MUX_DISP_PLL, CG_CTRL_VAL_SCLK_DISP1_400, 0);
|
|
CLK_GATE(DISP0_GATE_SCLK_DECON0_ECLK0, DISP0_DIV_SCLK_DECON0_ECLK0, CG_CTRL_VAL_SCLK_DECON0_ECLK0, 0);
|
|
CLK_GATE(DISP0_GATE_SCLK_DECON0_VCLK0, DISP0_DIV_SCLK_DECON0_VCLK0, CG_CTRL_VAL_SCLK_DECON0_VCLK0, 0);
|
|
CLK_GATE(DISP0_GATE_SCLK_DECON0_VCLK1, DISP0_DIV_SCLK_DECON0_VCLK1, CG_CTRL_VAL_SCLK_DECON0_VCLK1, 0);
|
|
CLK_GATE(DISP0_GATE_SCLK_HDMI_AUDIO, DISP0_MUX_SCLK_DISP0_HDMI_AUDIO, CG_CTRL_VAL_SCLK_HDMI_AUDIO, 0);
|
|
CLK_GATE(DISP0_GATE_SCLK_PROMISE_DISP0, TOP_GATE_SCLK_PROMISE_DISP, CG_CTRL_VAL_SCLK_DISP0_PROMISE, 0);
|
|
CLK_GATE(DISP0_GATE_PHYCLK_HDMIPHY_TMDS_20B_CLKO, DISP0_DIV_PHYCLK_HDMIPHY_TMDS_20B_CLKO, CG_CTRL_VAL_PHYCLK_HDMIPHY, 2);
|
|
CLK_GATE(DISP0_GATE_PHYCLK_HDMIPHY_TMDS_10B_CLKO, DISP0_MUX_PHYCLK_HDMIPHY_TMDS_CLKO_USER, CG_CTRL_VAL_PHYCLK_HDMIPHY, 1);
|
|
CLK_GATE(DISP0_GATE_PHYCLK_HDMIPHY_PIXEL_CLKO, DISP0_DIV_PHYCLK_HDMIPHY_PIXEL_CLKO, CG_CTRL_VAL_PHYCLK_HDMIPHY, 0);
|
|
CLK_GATE(DISP0_GATE_PHYCLK_MIPIDPHY0_BITCLKDIV8, DISP0_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, CG_CTRL_VAL_PHYCLK_MIPIDPHY0, 1);
|
|
CLK_GATE(DISP0_GATE_PHYCLK_MIPIDPHY0_RXCLKESC0, DISP0_MUX_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, CG_CTRL_VAL_PHYCLK_MIPIDPHY0, 0);
|
|
CLK_GATE(DISP0_GATE_PHYCLK_MIPIDPHY1_BITCLKDIV8, DISP0_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, CG_CTRL_VAL_PHYCLK_MIPIDPHY1, 1);
|
|
CLK_GATE(DISP0_GATE_PHYCLK_MIPIDPHY1_RXCLKESC0, DISP0_MUX_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, CG_CTRL_VAL_PHYCLK_MIPIDPHY1, 0);
|
|
CLK_GATE(DISP0_GATE_PHYCLK_MIPIDPHY2_BITCLKDIV8, DISP0_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV8_USER, CG_CTRL_VAL_PHYCLK_MIPIDPHY2, 1);
|
|
CLK_GATE(DISP0_GATE_PHYCLK_MIPIDPHY2_RXCLKESC0, DISP0_MUX_PHYCLK_MIPIDPHY2_RXCLKESC0_USER, CG_CTRL_VAL_PHYCLK_MIPIDPHY2, 0);
|
|
CLK_GATE(DISP0_GATE_PHYCLK_DPPHY_CH3_TXD_CLK, DISP0_MUX_PHYCLK_DPPHY_CH3_TXD_CLK_USER, CG_CTRL_VAL_PHYCLK_DPPHY, 3);
|
|
CLK_GATE(DISP0_GATE_PHYCLK_DPPHY_CH2_TXD_CLK, DISP0_MUX_PHYCLK_DPPHY_CH2_TXD_CLK_USER, CG_CTRL_VAL_PHYCLK_DPPHY, 2);
|
|
CLK_GATE(DISP0_GATE_PHYCLK_DPPHY_CH1_TXD_CLK, DISP0_MUX_PHYCLK_DPPHY_CH1_TXD_CLK_USER, CG_CTRL_VAL_PHYCLK_DPPHY, 1);
|
|
CLK_GATE(DISP0_GATE_PHYCLK_DPPHY_CH0_TXD_CLK, DISP0_MUX_PHYCLK_DPPHY_CH0_TXD_CLK_USER, CG_CTRL_VAL_PHYCLK_DPPHY, 0);
|
|
CLK_GATE(DISP0_GATE_OSCCLK_I_MIPI_DPHY_M4S4_M_XI, OSCCLK, CG_CTRL_VAL_OSCCLK, 4);
|
|
CLK_GATE(DISP0_GATE_OSCCLK_I_MIPI_DPHY_M4S0_M_XI, OSCCLK, CG_CTRL_VAL_OSCCLK, 3);
|
|
CLK_GATE(DISP0_GATE_OSCCLK_I_MIPI_DPHY_M1S0_M_XI, OSCCLK, CG_CTRL_VAL_OSCCLK, 2);
|
|
CLK_GATE(DISP0_GATE_OSCCLK_I_DPTX_PHY_I_REF_CLK_24M, OSCCLK, CG_CTRL_VAL_OSCCLK, 1);
|
|
CLK_GATE(DISP0_GATE_OSCCLK_DP_I_CLK_24M, OSCCLK, CG_CTRL_VAL_OSCCLK, 0);
|
|
CLK_GATE(DISP1_GATE_ACLK_XIU_DISP1X0, DISP1_MUX_ACLK_DISP1_0_400_USER, CG_CTRL_VAL_ACLK_DISP1_0_400, 5);
|
|
CLK_GATE(DISP1_GATE_ACLK_AXI_LH_ASYNC_SI_DISP1_0, DISP1_MUX_ACLK_DISP1_0_400_USER, CG_CTRL_VAL_ACLK_DISP1_0_400, 4);
|
|
CLK_GATE(DISP1_GATE_ACLK_PPMU_DISP1_0, DISP1_MUX_ACLK_DISP1_0_400_USER, CG_CTRL_VAL_ACLK_DISP1_0_400, 3);
|
|
CLK_GATE(DISP1_GATE_ACLK_SMMU_DISP1_0, DISP1_MUX_ACLK_DISP1_0_400_USER, CG_CTRL_VAL_ACLK_DISP1_0_400, 1);
|
|
CLK_GATE(DISP1_GATE_ACLK_VPP1_0, DISP1_MUX_ACLK_DISP1_0_400_USER, CG_CTRL_VAL_ACLK_DISP1_0_400, 0);
|
|
CLK_GATE(DISP1_GATE_ACLK_XIU_DISP1X1, DISP1_MUX_ACLK_DISP1_1_400, CG_CTRL_VAL_ACLK_DISP1_1_400, 6);
|
|
CLK_GATE(DISP1_GATE_ACLK_AXI_LH_ASYNC_SI_DISP1_1, DISP1_MUX_ACLK_DISP1_1_400, CG_CTRL_VAL_ACLK_DISP1_1_400, 5);
|
|
CLK_GATE(DISP1_GATE_ACLK_QE_DISP1_WDMA, DISP1_MUX_ACLK_DISP1_1_400, CG_CTRL_VAL_ACLK_DISP1_1_400, 4);
|
|
CLK_GATE(DISP1_GATE_ACLK_PPMU_DISP1_1, DISP1_MUX_ACLK_DISP1_1_400, CG_CTRL_VAL_ACLK_DISP1_1_400, 3);
|
|
CLK_GATE(DISP1_GATE_ACLK_SMMU_DISP1_1, DISP1_MUX_ACLK_DISP1_1_400, CG_CTRL_VAL_ACLK_DISP1_1_400, 1);
|
|
CLK_GATE(DISP1_GATE_ACLK_VPP1_1, DISP1_MUX_ACLK_DISP1_1_400, CG_CTRL_VAL_ACLK_DISP1_1_400, 0);
|
|
CLK_GATE(DISP1_GATE_ACLK_SFW_DISP1_0, DISP1_MUX_ACLK_DISP1_0_400_USER, CG_CTRL_VAL_ACLK_DISP1_0_400_SECURE_SFW_DISP1_0, 0);
|
|
CLK_GATE(DISP1_GATE_ACLK_SFW_DISP1_1, DISP1_MUX_ACLK_DISP1_1_400, CG_CTRL_VAL_ACLK_DISP1_1_400_SECURE_SFW_DISP1_1, 0);
|
|
CLK_GATE(DISP1_GATE_PCLK_VPP1_1, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 15);
|
|
CLK_GATE(DISP1_GATE_PCLK_DECON1_1, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 14);
|
|
CLK_GATE(DISP1_GATE_PCLK_DECON1_0, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 13);
|
|
CLK_GATE(DISP1_GATE_PCLK_QE_DISP1_WDMA, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 12);
|
|
CLK_GATE(DISP1_GATE_PCLK_PPMU_DISP1_1, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 11);
|
|
CLK_GATE(DISP1_GATE_PCLK_PPMU_DISP1_0, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 10);
|
|
CLK_GATE(DISP1_GATE_PCLK_SMMU_DISP1_1, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 9);
|
|
CLK_GATE(DISP1_GATE_PCLK_SMMU_DISP1_0, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 8);
|
|
CLK_GATE(DISP1_GATE_PCLK_SYSREG_DISP1, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 7);
|
|
CLK_GATE(DISP1_GATE_PCLK_PMU_DISP1, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 6);
|
|
CLK_GATE(DISP1_GATE_PCLK_CMU_DISP1, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 5);
|
|
CLK_GATE(DISP1_GATE_PCLK_VPP1_0, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 4);
|
|
CLK_GATE(DISP1_GATE_ACLK_AXI2APB_DISP1_1X, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 3);
|
|
CLK_GATE(DISP1_GATE_ACLK_AXI2APB_DISP1_0X, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 2);
|
|
CLK_GATE(DISP1_GATE_ACLK_XIU_DISP1SFRX, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 1);
|
|
CLK_GATE(DISP1_GATE_ACLK_AXI_LH_ASYNC_MI_DISP1SFR, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133, 0);
|
|
CLK_GATE(DISP1_GATE_PCLK_HPM_APBIF_DISP1, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133_HPM_APBIF_DISP1, 0);
|
|
CLK_GATE(DISP1_GATE_PCLK_SFW_DISP1_0, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133_SECURE_SFW_DISP1_0, 10);
|
|
CLK_GATE(DISP1_GATE_PCLK_SFW_DISP1_1, DISP1_DIV_PCLK_DISP1_0_133, CG_CTRL_VAL_PCLK_DISP1_0_133_SECURE_SFW_DISP1_1, 11);
|
|
CLK_GATE(DISP1_GATE_SCLK_DECON1_ECLK_0, DISP1_DIV_SCLK_DECON1_ECLK0, CG_CTRL_VAL_SCLK_DECON1_ECLK_0, 0);
|
|
CLK_GATE(DISP1_GATE_SCLK_DECON1_ECLK_1, DISP1_DIV_SCLK_DECON1_ECLK1, CG_CTRL_VAL_SCLK_DECON1_ECLK_1, 0);
|
|
CLK_GATE(DISP1_GATE_SCLK_PROMISE_DISP1, TOP_GATE_SCLK_PROMISE_DISP, CG_CTRL_VAL_SCLK_DISP1_PROMISE, 0);
|
|
CLK_GATE(FSYS0_GATE_ACLK_AXI2ACEL_FSYS0X, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 31);
|
|
CLK_GATE(FSYS0_GATE_PCLK_CMU_FSYS0, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 30);
|
|
CLK_GATE(FSYS0_GATE_PCLK_GPIO_FSYS0, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 29);
|
|
CLK_GATE(FSYS0_GATE_PCLK_SYSREG_FSYS0, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 28);
|
|
CLK_GATE(FSYS0_GATE_PCLK_PPMU_FSYS0, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 27);
|
|
CLK_GATE(FSYS0_GATE_PCLK_PMU_FSYS0, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 26);
|
|
CLK_GATE(FSYS0_GATE_PCLK_ETR_USB_FSYS0, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 25);
|
|
CLK_GATE(FSYS0_GATE_HCLK_USBHOST20, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 24);
|
|
CLK_GATE(FSYS0_GATE_ACLK_AXI_US_USBHS_FSYS0X, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 21);
|
|
CLK_GATE(FSYS0_GATE_ACLK_ETR_USB_FSYS0, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 20);
|
|
CLK_GATE(FSYS0_GATE_ACLK_UFS_LINK_EMBEDDED, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 19);
|
|
CLK_GATE(FSYS0_GATE_ACLK_USBDRD30, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 18);
|
|
CLK_GATE(FSYS0_GATE_ACLK_MMC0, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 17);
|
|
CLK_GATE(FSYS0_GATE_ACLK_PDMAS, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 16);
|
|
CLK_GATE(FSYS0_GATE_ACLK_PDMA0, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 15);
|
|
CLK_GATE(FSYS0_GATE_ACLK_PPMU_FSYS0, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 14);
|
|
CLK_GATE(FSYS0_GATE_ACLK_XIU_FSYS0SFRX, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 13);
|
|
CLK_GATE(FSYS0_GATE_ACLK_AXI_US_USBDRD30X_FSYS0X, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 12);
|
|
CLK_GATE(FSYS0_GATE_ACLK_AXI_US_PDMAX_FSYS0X, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 11);
|
|
CLK_GATE(FSYS0_GATE_ACLK_AXI2AHB_FSYS0H, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 10);
|
|
CLK_GATE(FSYS0_GATE_ACLK_AXI2AHB_USBDRD30H, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 9);
|
|
CLK_GATE(FSYS0_GATE_ACLK_AXI_LH_ASYNC_MI_ETR_USB_FSYS0, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 8);
|
|
CLK_GATE(FSYS0_GATE_ACLK_XIU_PDMAX, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 7);
|
|
CLK_GATE(FSYS0_GATE_ACLK_XIU_USBX, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 6);
|
|
CLK_GATE(FSYS0_GATE_ACLK_XIU_EMBEDDEDX, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 5);
|
|
CLK_GATE(FSYS0_GATE_ACLK_XIU_FSYS0X, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 4);
|
|
CLK_GATE(FSYS0_GATE_ACLK_AXI2APB_FSYS0P, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 3);
|
|
CLK_GATE(FSYS0_GATE_ACLK_AHB_BRIDGE_FSYS0H, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 2);
|
|
CLK_GATE(FSYS0_GATE_ACLK_AXI_LH_ASYNC_MI_TOP_FSYS0, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 1);
|
|
CLK_GATE(FSYS0_GATE_ACLK_ACEL_LH_ASYNC_SI_TOP_FSYS0, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_ACLK_FSYS0_200, 0);
|
|
CLK_GATE(FSYS0_GATE_PCLK_HPM_APBIF_FSYS0, FSYS0_MUX_ACLK_FSYS0_200_USER, CG_CTRL_VAL_PCLK_HPM_APBIF_FSYS0, 0);
|
|
CLK_GATE(FSYS0_GATE_SCLK_USBDRD30_SUSPEND_CLK, FSYS0_MUX_SCLK_FSYS0_USBDRD30_USER, CG_CTRL_VAL_SCLK_USBDRD30_SUSPEND_CLK, 0);
|
|
CLK_GATE(FSYS0_GATE_SCLK_MMC0, FSYS0_MUX_SCLK_FSYS0_MMC0_USER, CG_CTRL_VAL_SCLK_MMC0, 0);
|
|
CLK_GATE(FSYS0_GATE_SCLK_UFSUNIPRO_EMBEDDED, FSYS0_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_USER, CG_CTRL_VAL_SCLK_UFSUNIPRO_EMBEDDED, 0);
|
|
CLK_GATE(FSYS0_GATE_SCLK_USBDRD30_REF_CLK, FSYS0_MUX_SCLK_FSYS0_USBDRD30_USER, CG_CTRL_VAL_SCLK_USBDRD30_REF_CLK, 0);
|
|
CLK_GATE(FSYS0_GATE_PHYCLK_USBDRD30_UDRD30_PHYCLOCK, FSYS0_MUX_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER, CG_CTRL_VAL_PHYCLK_USBDRD30_UDRD30_PHYCLOCK, 0);
|
|
CLK_GATE(FSYS0_GATE_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK, FSYS0_MUX_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER, CG_CTRL_VAL_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK, 0);
|
|
CLK_GATE(FSYS0_GATE_PHYCLK_UFS_TX0_SYMBOL, FSYS0_MUX_PHYCLK_UFS_TX0_SYMBOL_USER, CG_CTRL_VAL_PHYCLK_UFS_TX0_SYMBOL, 0);
|
|
CLK_GATE(FSYS0_GATE_PHYCLK_UFS_RX0_SYMBOL, FSYS0_MUX_PHYCLK_UFS_RX0_SYMBOL_USER, CG_CTRL_VAL_PHYCLK_UFS_RX0_SYMBOL, 0);
|
|
CLK_GATE(FSYS0_GATE_PHYCLK_USBHOST20_PHYCLOCK, FSYS0_MUX_PHYCLK_USBHOST20_PHYCLOCK_USER, CG_CTRL_VAL_PHYCLK_USBHOST20_PHYCLOCK, 0);
|
|
CLK_GATE(FSYS0_GATE_SCLK_PROMISE_FSYS0, TOP_GATE_SCLK_PROMISE_INT, CG_CTRL_VAL_SCLK_PROMISE_FSYS0, 0);
|
|
CLK_GATE(FSYS0_GATE_SCLK_USBHOST20PHY_REF_CLK, FSYS0_MUX_PHYCLK_USBHOST20PHY_REF_CLK, CG_CTRL_VAL_SCLK_USBHOST20PHY_REF_CLK, 0);
|
|
CLK_GATE(FSYS0_GATE_SCLK_UFSUNIPRO_EMBEDDED_CFG, FSYS0_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_CFG_USER, CG_CTRL_VAL_SCLK_UFSUNIPRO_EMBEDDED_CFG, 0);
|
|
CLK_GATE(FSYS0_GATE_SCLK_USBHOST20_REF_CLK, FSYS0_MUX_SCLK_FSYS0_USBDRD30_USER, CG_CTRL_VAL_SCLK_USBHOST20_REF_CLK, 0);
|
|
CLK_GATE(FSYS1_GATE_ACLK_AXI2ACEL_FSYS1X, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 31);
|
|
CLK_GATE(FSYS1_GATE_PCLK_CMU_FSYS1, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 30);
|
|
CLK_GATE(FSYS1_GATE_ACLK_COMBO_PHY_PCS_PCLK_WIFI1, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 29);
|
|
CLK_GATE(FSYS1_GATE_ACLK_COMBO_PHY_PCS_PCLK_WIFI0, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 28);
|
|
CLK_GATE(FSYS1_GATE_PCLK_PMU_FSYS1, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 26);
|
|
CLK_GATE(FSYS1_GATE_PCLK_PPMU_FSYS1, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 25);
|
|
CLK_GATE(FSYS1_GATE_PCLK_GPIO_FSYS1, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 24);
|
|
CLK_GATE(FSYS1_GATE_PCLK_SYSREG_FSYS1, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 23);
|
|
CLK_GATE(FSYS1_GATE_ACLK_SROMC_FSYS1, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 22);
|
|
CLK_GATE(FSYS1_GATE_PCLK_PCIE_WIFI1, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 21);
|
|
CLK_GATE(FSYS1_GATE_ACLK_PCIE_WIFI1_DBI, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 20);
|
|
CLK_GATE(FSYS1_GATE_ACLK_PCIE_WIFI1_SLV, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 19);
|
|
CLK_GATE(FSYS1_GATE_ACLK_PCIE_WIFI1_MSTR, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 18);
|
|
CLK_GATE(FSYS1_GATE_ACLK_AHB2AXI_PCIE_WIFI1, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 17);
|
|
CLK_GATE(FSYS1_GATE_PCLK_PCIE_WIFI0, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 16);
|
|
CLK_GATE(FSYS1_GATE_ACLK_PCIE_WIFI0_DBI, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 15);
|
|
CLK_GATE(FSYS1_GATE_ACLK_PCIE_WIFI0_SLV, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 14);
|
|
CLK_GATE(FSYS1_GATE_ACLK_PCIE_WIFI0_MSTR, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 13);
|
|
CLK_GATE(FSYS1_GATE_ACLK_AHB2AXI_PCIE_WIFI0, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 12);
|
|
CLK_GATE(FSYS1_GATE_ACLK_PPMU_FSYS1, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 11);
|
|
CLK_GATE(FSYS1_GATE_ACLK_AHB_BRIDGE_FSYS1_S4, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 10);
|
|
CLK_GATE(FSYS1_GATE_ACLK_AXI2AHB_FSYS1_S4, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 9);
|
|
CLK_GATE(FSYS1_GATE_ACLK_AXI2APB_FSYS1_S1, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 8);
|
|
CLK_GATE(FSYS1_GATE_ACLK_AXI2AHB_FSYS1_S0, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 7);
|
|
CLK_GATE(FSYS1_GATE_ACLK_XIU_FSYS1SFRX, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 6);
|
|
CLK_GATE(FSYS1_GATE_ACLK_XIU_SDCARDX, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 5);
|
|
CLK_GATE(FSYS1_GATE_ACLK_XIU_FSYS1X, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 4);
|
|
CLK_GATE(FSYS1_GATE_ACLK_AXI_LH_ASYNC_MI_TOP_FSYS1, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 3);
|
|
CLK_GATE(FSYS1_GATE_ACLK_ACEL_LH_ASYNC_SI_TOP_FSYS1, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 2);
|
|
CLK_GATE(FSYS1_GATE_ACLK_UFS_LINK_SDCARD, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 1);
|
|
CLK_GATE(FSYS1_GATE_ACLK_MMC2, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_ACLK_FSYS1_200, 0);
|
|
CLK_GATE(FSYS1_GATE_PCLK_HPM_APBIF_FSYS1, FSYS1_MUX_ACLK_FSYS1_200_USER, CG_CTRL_VAL_PCLK_HPM_APBIF_FSYS1, 0);
|
|
CLK_GATE(FSYS1_GATE_PCLK_COMBO_PHY_WIFI1, FSYS1_DIV_PCLK_COMBO_PHY_WIFI, CG_CTRL_VAL_PCLK_COMBO_PHY_WIFI, 1);
|
|
CLK_GATE(FSYS1_GATE_PCLK_COMBO_PHY_WIFI0, FSYS1_DIV_PCLK_COMBO_PHY_WIFI, CG_CTRL_VAL_PCLK_COMBO_PHY_WIFI, 0);
|
|
CLK_GATE(FSYS1_GATE_SCLK_MMC2, FSYS1_MUX_SCLK_FSYS1_MMC2_USER, CG_CTRL_VAL_SCLK_MMC2, 0);
|
|
CLK_GATE(FSYS1_GATE_SCLK_UFSUNIPRO_SDCARD, FSYS1_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_USER, CG_CTRL_VAL_SCLK_UFSUNIPRO_SDCARD, 0);
|
|
CLK_GATE(FSYS1_GATE_SCLK_UFSUNIPRO_SDCARD_CFG, FSYS1_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_CFG_USER, CG_CTRL_VAL_SCLK_UFSUNIPRO_SDCARD_CFG, 0);
|
|
CLK_GATE(FSYS1_GATE_SCLK_PCIE_LINK_WIFI0, OSCCLK, CG_CTRL_VAL_SCLK_PCIE_LINK_WIFI0, 0);
|
|
CLK_GATE(FSYS1_GATE_SCLK_PCIE_LINK_WIFI1, OSCCLK, CG_CTRL_VAL_SCLK_PCIE_LINK_WIFI1, 0);
|
|
CLK_GATE(FSYS1_GATE_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL, FSYS1_MUX_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_USER, CG_CTRL_VAL_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL, 0);
|
|
CLK_GATE(FSYS1_GATE_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL, FSYS1_MUX_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_USER, CG_CTRL_VAL_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL, 0);
|
|
CLK_GATE(FSYS1_GATE_PHYCLK_PCIE_WIFI0_TX0, FSYS1_MUX_PHYCLK_PCIE_WIFI0_TX0_USER, CG_CTRL_VAL_PHYCLK_PCIE_WIFI0_TX0, 0);
|
|
CLK_GATE(FSYS1_GATE_PHYCLK_PCIE_WIFI0_RX0, FSYS1_MUX_PHYCLK_PCIE_WIFI0_RX0_USER, CG_CTRL_VAL_PHYCLK_PCIE_WIFI0_RX0, 0);
|
|
CLK_GATE(FSYS1_GATE_PHYCLK_PCIE_WIFI1_TX0, FSYS1_MUX_PHYCLK_PCIE_WIFI1_TX0_USER, CG_CTRL_VAL_PHYCLK_PCIE_WIFI1_TX0, 0);
|
|
CLK_GATE(FSYS1_GATE_PHYCLK_PCIE_WIFI1_RX0, FSYS1_MUX_PHYCLK_PCIE_WIFI1_RX0_USER, CG_CTRL_VAL_PHYCLK_PCIE_WIFI1_RX0, 0);
|
|
CLK_GATE(FSYS1_GATE_PHYCLK_PCIE_WIFI0_DIG_REFCLK, FSYS1_MUX_PHYCLK_PCIE_WIFI0_DIG_REFCLK_USER, CG_CTRL_VAL_PHYCLK_PCIE_WIFI0_DIG_REFCLK, 0);
|
|
CLK_GATE(FSYS1_GATE_PHYCLK_PCIE_WIFI1_DIG_REFCLK, FSYS1_MUX_PHYCLK_PCIE_WIFI1_DIG_REFCLK_USER, CG_CTRL_VAL_PHYCLK_PCIE_WIFI1_DIG_REFCLK, 0);
|
|
CLK_GATE(FSYS1_GATE_SCLK_PROMISE_FSYS1, TOP_GATE_SCLK_PROMISE_INT, CG_CTRL_VAL_SCLK_PROMISE_FSYS1, 0);
|
|
CLK_GATE(G3D_GATE_ACLK_G3D, G3D_DIV_ACLK_G3D, CLK_ENABLE_ACLK_G3D, 0);
|
|
CLK_GATE(G3D_GATE_ACLK_GRAY_DEC, G3D_DIV_ACLK_G3D, CLK_ENABLE_ACLK_G3D_BUS, 10);
|
|
CLK_GATE(G3D_GATE_ACLK_SFW100_ACEL_G3D1, G3D_DIV_ACLK_G3D, CLK_ENABLE_ACLK_G3D_BUS, 9);
|
|
CLK_GATE(G3D_GATE_ACLK_SFW100_ACEL_G3D0, G3D_DIV_ACLK_G3D, CLK_ENABLE_ACLK_G3D_BUS, 8);
|
|
CLK_GATE(G3D_GATE_ACLK_XIU_G3D, G3D_DIV_ACLK_G3D, CLK_ENABLE_ACLK_G3D_BUS, 7);
|
|
CLK_GATE(G3D_GATE_ACLK_PPMU_G3D1, G3D_DIV_ACLK_G3D, CLK_ENABLE_ACLK_G3D_BUS, 6);
|
|
CLK_GATE(G3D_GATE_ACLK_PPMU_G3D0, G3D_DIV_ACLK_G3D, CLK_ENABLE_ACLK_G3D_BUS, 5);
|
|
CLK_GATE(G3D_GATE_ACLK_ASYNCAPBM_G3D, G3D_DIV_ACLK_G3D, CLK_ENABLE_ACLK_G3D_BUS, 4);
|
|
CLK_GATE(G3D_GATE_ACLK_ASYNCAXI_G3D, G3D_DIV_ACLK_G3D, CLK_ENABLE_ACLK_G3D_BUS, 3);
|
|
CLK_GATE(G3D_GATE_ACLK_AXI_DS_G3D, G3D_DIV_ACLK_G3D, CLK_ENABLE_ACLK_G3D_BUS, 2);
|
|
CLK_GATE(G3D_GATE_ACLK_ACEL_LH_ASYNC_SI_G3D1, G3D_DIV_ACLK_G3D, CLK_ENABLE_ACLK_G3D_BUS, 1);
|
|
CLK_GATE(G3D_GATE_ACLK_ACEL_LH_ASYNC_SI_G3D0, G3D_DIV_ACLK_G3D, CLK_ENABLE_ACLK_G3D_BUS, 0);
|
|
CLK_GATE(G3D_GATE_PCLK_SFW100_ACEL_G3D1, G3D_DIV_PCLK_G3D, CLK_ENABLE_PCLK_G3D, 9);
|
|
CLK_GATE(G3D_GATE_PCLK_SFW100_ACEL_G3D0, G3D_DIV_PCLK_G3D, CLK_ENABLE_PCLK_G3D, 8);
|
|
CLK_GATE(G3D_GATE_PCLK_HPM_G3D, G3D_DIV_PCLK_G3D, CLK_ENABLE_PCLK_G3D, 7);
|
|
CLK_GATE(G3D_GATE_PCLK_PPMU_G3D1, G3D_DIV_PCLK_G3D, CLK_ENABLE_PCLK_G3D, 6);
|
|
CLK_GATE(G3D_GATE_PCLK_PPMU_G3D0, G3D_DIV_PCLK_G3D, CLK_ENABLE_PCLK_G3D, 5);
|
|
CLK_GATE(G3D_GATE_PCLK_PMU_G3D, G3D_DIV_PCLK_G3D, CLK_ENABLE_PCLK_G3D, 4);
|
|
CLK_GATE(G3D_GATE_ACLK_ASYNCAPBS_G3D, G3D_DIV_PCLK_G3D, CLK_ENABLE_PCLK_G3D, 3);
|
|
CLK_GATE(G3D_GATE_PCLK_SYSREG_G3D, G3D_DIV_PCLK_G3D, CLK_ENABLE_PCLK_G3D, 2);
|
|
CLK_GATE(G3D_GATE_ACLK_AXI2APB_G3DP, G3D_DIV_PCLK_G3D, CLK_ENABLE_PCLK_G3D, 1);
|
|
CLK_GATE(G3D_GATE_ACLK_AXI_LH_ASYNC_MI_G3DP, G3D_DIV_PCLK_G3D, CLK_ENABLE_PCLK_G3D, 0);
|
|
CLK_GATE(G3D_GATE_SCLK_HPM2_G3D, G3D_DIV_SCLK_HPM_G3D, CLK_ENABLE_SCLK_HPM_G3D, 2);
|
|
CLK_GATE(G3D_GATE_SCLK_HPM1_G3D, G3D_DIV_SCLK_HPM_G3D, CLK_ENABLE_SCLK_HPM_G3D, 1);
|
|
CLK_GATE(G3D_GATE_SCLK_HPM0_G3D, G3D_DIV_SCLK_HPM_G3D, CLK_ENABLE_SCLK_HPM_G3D, 0);
|
|
CLK_GATE(G3D_GATE_SCLK_AXI_LH_ASYNC_SI_G3DIRAM, G3D_DIV_SCLK_ATE_G3D, CLK_ENABLE_SCLK_ATE_G3D, 1);
|
|
CLK_GATE(G3D_GATE_SCLK_ASYNCAXI_G3D, G3D_DIV_SCLK_ATE_G3D, CLK_ENABLE_SCLK_ATE_G3D, 0);
|
|
CLK_GATE(IMEM_GATE_ACLK_MC, IMEM_MUX_ACLK_IMEM_266_USER, CG_CTRL_VAL_ACLK_IMEM_266, 7);
|
|
CLK_GATE(IMEM_GATE_ACLK_XIU_3X1_SSS, IMEM_MUX_ACLK_IMEM_266_USER, CG_CTRL_VAL_ACLK_IMEM_266, 6);
|
|
CLK_GATE(IMEM_GATE_ACLK_AXI_US_APM, IMEM_MUX_ACLK_IMEM_266_USER, CG_CTRL_VAL_ACLK_IMEM_266, 5);
|
|
CLK_GATE(IMEM_GATE_ACLK_ASYNCAHBMSTM_APM, IMEM_MUX_ACLK_IMEM_266_USER, CG_CTRL_VAL_ACLK_IMEM_266, 4);
|
|
CLK_GATE(IMEM_GATE_ACLK_ASYNCAHBM_SSS_ATLAS, IMEM_MUX_ACLK_IMEM_266_USER, CG_CTRL_VAL_ACLK_IMEM_266, 3);
|
|
CLK_GATE(IMEM_GATE_ACLK_LH_ASYNC_SI_IMEM, IMEM_MUX_ACLK_IMEM_266_USER, CG_CTRL_VAL_ACLK_IMEM_266, 2);
|
|
CLK_GATE(IMEM_GATE_ACLK_PPMU_SSSX, IMEM_MUX_ACLK_IMEM_266_USER, CG_CTRL_VAL_ACLK_IMEM_266, 1);
|
|
CLK_GATE(IMEM_GATE_ACLK_XIU_IMEMX, IMEM_MUX_ACLK_IMEM_266_USER, CG_CTRL_VAL_ACLK_IMEM_266, 0);
|
|
CLK_GATE(IMEM_GATE_ACLK_SSS, IMEM_MUX_ACLK_IMEM_266_USER, CG_CTRL_VAL_ACLK_IMEM_266_SECURE_SSS, 0);
|
|
CLK_GATE(IMEM_GATE_ACLK_RTIC, IMEM_MUX_ACLK_IMEM_266_USER, CG_CTRL_VAL_ACLK_IMEM_266_SECURE_RTIC, 0);
|
|
CLK_GATE(IMEM_GATE_PCLK_CMU_IMEM, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 16);
|
|
CLK_GATE(IMEM_GATE_PCLK_SYSREG_IMEM, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 15);
|
|
CLK_GATE(IMEM_GATE_PCLK_MC, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 14);
|
|
CLK_GATE(IMEM_GATE_PCLK_PPMU_SSSX, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 12);
|
|
CLK_GATE(IMEM_GATE_PCLK_PMU_IMEM, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 11);
|
|
CLK_GATE(IMEM_GATE_ACLK_ASYNCAHBSS_APM, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 10);
|
|
CLK_GATE(IMEM_GATE_ACLK_AXI2AHB_APM, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 9);
|
|
CLK_GATE(IMEM_GATE_ACLK_INT_MEM_ALV, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 8);
|
|
CLK_GATE(IMEM_GATE_ACLK_INT_MEM, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 7);
|
|
CLK_GATE(IMEM_GATE_ACLK_AXIDS_PIMEMX_IMEM, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 6);
|
|
CLK_GATE(IMEM_GATE_ACLK_AXILHASYNCM_PIMEMX, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 5);
|
|
CLK_GATE(IMEM_GATE_ACLK_AXI2APB_IMEM_1, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 4);
|
|
CLK_GATE(IMEM_GATE_ACLK_AXI2APB_IMEM_0, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 3);
|
|
CLK_GATE(IMEM_GATE_ACLK_XIU_PIMEMX1, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 2);
|
|
CLK_GATE(IMEM_GATE_ACLK_XIU_PIMEMX0, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 1);
|
|
CLK_GATE(IMEM_GATE_ACLK_GIC, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_ACLK_IMEM_200, 0);
|
|
CLK_GATE(IMEM_GATE_PCLK_SSS, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_PCLK_IMEM_200_SECURE_SSS, 0);
|
|
CLK_GATE(IMEM_GATE_PCLK_RTIC, IMEM_MUX_ACLK_IMEM_200_USER, CG_CTRL_VAL_PCLK_IMEM_200_SECURE_RTIC, 0);
|
|
CLK_GATE(IMEM_GATE_ACLK_ASYNCAHBSM_APM, IMEM_MUX_ACLK_IMEM_100_USER, CG_CTRL_VAL_ACLK_IMEM_100, 2);
|
|
CLK_GATE(IMEM_GATE_ACLK_AHB2AXI_APM, IMEM_MUX_ACLK_IMEM_100_USER, CG_CTRL_VAL_ACLK_IMEM_266, 9);
|
|
CLK_GATE(IMEM_GATE_ACLK_ASYNCAHBMSTS_APM, IMEM_MUX_ACLK_IMEM_100_USER, CG_CTRL_VAL_ACLK_IMEM_100, 0);
|
|
CLK_GATE(IMEM_GATE_ACLK_CM3_APM, IMEM_MUX_ACLK_IMEM_100_USER, CG_CTRL_VAL_ACLK_IMEM_100_SECURE_CM3_APM, 0);
|
|
CLK_GATE(IMEM_GATE_ACLK_AHB_BUSMATRIX_APM, IMEM_MUX_ACLK_IMEM_100_USER, CG_CTRL_VAL_ACLK_IMEM_100_SECURE_AHB_BUSMATRIX_APM, 0);
|
|
CLK_GATE(IMEM_GATE_SCLK_CM3_APM, IMEM_MUX_ACLK_IMEM_100_USER, CG_CTRL_VAL_ACLK_IMEM_100_SECURE_CM3_APM, 0);
|
|
CLK_GATE(IMEM_GATE_ACLK_APM, IMEM_MUX_ACLK_IMEM_100_USER, CG_CTRL_VAL_ACLK_IMEM_100_SECURE_APM, 0);
|
|
CLK_GATE(ISP0_GATE_ACLK_FIMC_ISP0, ISP0_MUX_ACLK_ISP0_528_USER, CLK_ENABLE_ACLK_ISP0, 0);
|
|
CLK_GATE(ISP0_GATE_PCLK_FIMC_ISP0, ISP0_DIV_PCLK_ISP0, CLK_ENABLE_PCLK_ISP0, 0);
|
|
CLK_GATE(ISP0_GATE_ACLK_FIMC_TPU, ISP0_MUX_ACLK_ISP0_TPU_400_USER, CLK_ENABLE_ACLK_ISP0_TPU, 0);
|
|
CLK_GATE(ISP0_GATE_PCLK_FIMC_TPU, ISP0_DIV_PCLK_ISP0_TPU, CLK_ENABLE_PCLK_ISP0_TPU, 0);
|
|
CLK_GATE(ISP0_GATE_ACLK_SysMMU601, ISP0_MUX_ACLK_ISP0_TREX_528_USER, CLK_ENABLE_ACLK_ISP0_TREX, 2);
|
|
CLK_GATE(ISP0_GATE_CLK_C_TREX_C, ISP0_MUX_ACLK_ISP0_TREX_528_USER, CLK_ENABLE_ACLK_ISP0_TREX, 1);
|
|
CLK_GATE(ISP0_GATE_CLK_AXI_LH_ASYNC_SI_TOP_ISP0, ISP0_MUX_ACLK_ISP0_TREX_528_USER, CLK_ENABLE_ACLK_ISP0_TREX, 0);
|
|
CLK_GATE(ISP0_GATE_PCLK_SYSREG_ISP0, ISP0_DIV_PCLK_ISP0_TREX_264, CLK_ENABLE_PCLK_TREX_264, 3);
|
|
CLK_GATE(ISP0_GATE_PCLK_PMU_ISP0, ISP0_DIV_PCLK_ISP0_TREX_264, CLK_ENABLE_PCLK_TREX_264, 2);
|
|
CLK_GATE(ISP0_GATE_ACLK_XIU_N_ASYNC_MI, ISP0_DIV_PCLK_ISP0_TREX_264, CLK_ENABLE_PCLK_TREX_264, 1);
|
|
CLK_GATE(ISP0_GATE_PCLK_ISP0, ISP0_DIV_PCLK_ISP0_TREX_264, CLK_ENABLE_PCLK_TREX_264, 0);
|
|
CLK_GATE(ISP0_GATE_PCLK_HPM_APBIF_ISP0, ISP0_DIV_PCLK_ISP0_TREX_264, CLK_ENABLE_PCLK_HPM_APBIF_ISP0, 0);
|
|
CLK_GATE(ISP0_GATE_PCLK_SysMMU601, ISP0_DIV_PCLK_ISP0_TREX_132, CLK_ENABLE_PCLK_TREX_132, 1);
|
|
CLK_GATE(ISP0_GATE_PCLK_TREX_C, ISP0_DIV_PCLK_ISP0_TREX_132, CLK_ENABLE_PCLK_TREX_132, 0);
|
|
CLK_GATE(ISP0_GATE_SCLK_PROMISE_ISP0, TOP_GATE_SCLK_PROMISE_INT, CLK_ENABLE_SCLK_PROMISE_ISP0, 0);
|
|
CLK_GATE(ISP0_GATE_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D, ISP0_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_USER, CLK_ENABLE_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D, 0);
|
|
CLK_GATE(ISP0_LOCAL_GATE_ACLK_FIMC_ISP0, ISP0_GATE_ACLK_FIMC_ISP0, CLK_ENABLE_ACLK_ISP0_LOCAL, 0);
|
|
CLK_GATE(ISP0_LOCAL_GATE_PCLK_FIMC_ISP0, ISP0_GATE_PCLK_FIMC_ISP0, CLK_ENABLE_PCLK_ISP0_LOCAL, 0);
|
|
CLK_GATE(ISP0_LOCAL_GATE_ACLK_FIMC_TPU, ISP0_GATE_ACLK_FIMC_TPU, CLK_ENABLE_ACLK_ISP0_TPU_LOCAL, 0);
|
|
CLK_GATE(ISP0_LOCAL_GATE_PCLK_FIMC_TPU, ISP0_GATE_PCLK_FIMC_TPU, CLK_ENABLE_PCLK_ISP0_TPU_LOCAL, 0);
|
|
CLK_GATE(ISP0_LOCAL_GATE_CLK_C_TREX_C, ISP0_GATE_CLK_C_TREX_C, CLK_ENABLE_ACLK_ISP0_TREX_LOCAL, 1);
|
|
CLK_GATE(ISP0_LOCAL_GATE_PCLK_TREX_C, ISP0_GATE_PCLK_TREX_C, CLK_ENABLE_PCLK_TREX_132_LOCAL, 0);
|
|
CLK_GATE(ISP1_GATE_ACLK_XIU_N_ASYNC_SI, ISP1_MUX_ACLK_ISP1_468_USER, CLK_ENABLE_ACLK_ISP1, 1);
|
|
CLK_GATE(ISP1_GATE_ACLK_FIMC_ISP1, ISP1_MUX_ACLK_ISP1_468_USER, CLK_ENABLE_ACLK_ISP1, 0);
|
|
CLK_GATE(ISP1_GATE_PCLK_SYSREG_ISP1, ISP1_DIV_PCLK_ISP1_234, CLK_ENABLE_PCLK_ISP1_234, 4);
|
|
CLK_GATE(ISP1_GATE_PCLK_PMU_ISP1, ISP1_DIV_PCLK_ISP1_234, CLK_ENABLE_PCLK_ISP1_234, 3);
|
|
CLK_GATE(ISP1_GATE_ACLK_AXI2APB_BRIDGE_IS2P, ISP1_DIV_PCLK_ISP1_234, CLK_ENABLE_PCLK_ISP1_234, 2);
|
|
CLK_GATE(ISP1_GATE_ACLK_XIU_N_ASYNC_MI, ISP1_DIV_PCLK_ISP1_234, CLK_ENABLE_PCLK_ISP1_234, 1);
|
|
CLK_GATE(ISP1_GATE_PCLK_FIMC_ISP1, ISP1_DIV_PCLK_ISP1_234, CLK_ENABLE_PCLK_ISP1_234, 0);
|
|
CLK_GATE(ISP1_GATE_PCLK_HPM_APBIF_ISP1, ISP1_DIV_PCLK_ISP1_234, CLK_ENABLE_PCLK_HPM_APBIF_ISP1, 0);
|
|
CLK_GATE(ISP1_GATE_SCLK_PROMISE_ISP1, TOP_GATE_SCLK_PROMISE_INT, CLK_ENABLE_SCLK_PROMISE_ISP1, 0);
|
|
CLK_GATE(ISP1_LOCAL_GATE_ACLK_FIMC_ISP1, ISP1_GATE_ACLK_FIMC_ISP1, CLK_ENABLE_ACLK_ISP1_LOCAL, 0);
|
|
CLK_GATE(ISP1_LOCAL_GATE_PCLK_FIMC_ISP1, ISP1_GATE_PCLK_FIMC_ISP1, CLK_ENABLE_PCLK_ISP1_234_LOCAL, 0);
|
|
CLK_GATE(MFC_GATE_ACLK_ASYNCAPB_MFC, MFC_MUX_ACLK_MFC_600_USER, CG_CTRL_VAL_ACLK_MFC_600, 7);
|
|
CLK_GATE(MFC_GATE_ACLK_SMMU_MFC_1, MFC_MUX_ACLK_MFC_600_USER, CG_CTRL_VAL_ACLK_MFC_600, 6);
|
|
CLK_GATE(MFC_GATE_ACLK_SMMU_MFC_0, MFC_MUX_ACLK_MFC_600_USER, CG_CTRL_VAL_ACLK_MFC_600, 5);
|
|
CLK_GATE(MFC_GATE_ACLK_MFC, MFC_MUX_ACLK_MFC_600_USER, CG_CTRL_VAL_ACLK_MFC_600, 4);
|
|
CLK_GATE(MFC_GATE_ACLK_PPMU_MFC_1, MFC_MUX_ACLK_MFC_600_USER, CG_CTRL_VAL_ACLK_MFC_600, 3);
|
|
CLK_GATE(MFC_GATE_ACLK_PPMU_MFC_0, MFC_MUX_ACLK_MFC_600_USER, CG_CTRL_VAL_ACLK_MFC_600, 2);
|
|
CLK_GATE(MFC_GATE_ACLK_LH_S_MFC_1, MFC_MUX_ACLK_MFC_600_USER, CG_CTRL_VAL_ACLK_MFC_600, 1);
|
|
CLK_GATE(MFC_GATE_ACLK_LH_S_MFC_0, MFC_MUX_ACLK_MFC_600_USER, CG_CTRL_VAL_ACLK_MFC_600, 0);
|
|
CLK_GATE(MFC_GATE_ACLK_SFW_MFC_0, MFC_MUX_ACLK_MFC_600_USER, CG_CTRL_VAL_ACLK_MFC_600_SECURE_SFW_MFC_0, 0);
|
|
CLK_GATE(MFC_GATE_ACLK_SFW_MFC_1, MFC_MUX_ACLK_MFC_600_USER, CG_CTRL_VAL_ACLK_MFC_600_SECURE_SFW_MFC_1, 0);
|
|
CLK_GATE(MFC_GATE_PCLK_SYSREG_MFC, MFC_DIV_PCLK_MFC_150, CG_CTRL_VAL_PCLK_MFC_150, 9);
|
|
CLK_GATE(MFC_GATE_PCLK_SMMU_MFC_1, MFC_DIV_PCLK_MFC_150, CG_CTRL_VAL_PCLK_MFC_150, 8);
|
|
CLK_GATE(MFC_GATE_PCLK_SMMU_MFC_0, MFC_DIV_PCLK_MFC_150, CG_CTRL_VAL_PCLK_MFC_150, 7);
|
|
CLK_GATE(MFC_GATE_PCLK_PPMU_MFC_1, MFC_DIV_PCLK_MFC_150, CG_CTRL_VAL_PCLK_MFC_150, 6);
|
|
CLK_GATE(MFC_GATE_PCLK_PPMU_MFC_0, MFC_DIV_PCLK_MFC_150, CG_CTRL_VAL_PCLK_MFC_150, 5);
|
|
CLK_GATE(MFC_GATE_PCLK_PMU_MFC, MFC_DIV_PCLK_MFC_150, CG_CTRL_VAL_PCLK_MFC_150, 4);
|
|
CLK_GATE(MFC_GATE_PCLK_CMU_MFC, MFC_DIV_PCLK_MFC_150, CG_CTRL_VAL_PCLK_MFC_150, 3);
|
|
CLK_GATE(MFC_GATE_PCLK_ASYNCAPB_MFC, MFC_DIV_PCLK_MFC_150, CG_CTRL_VAL_PCLK_MFC_150, 2);
|
|
CLK_GATE(MFC_GATE_ACLK_AXI2APB_MFCSFR, MFC_DIV_PCLK_MFC_150, CG_CTRL_VAL_PCLK_MFC_150, 1);
|
|
CLK_GATE(MFC_GATE_ACLK_LH_M_MFC, MFC_DIV_PCLK_MFC_150, CG_CTRL_VAL_PCLK_MFC_150, 0);
|
|
CLK_GATE(MFC_GATE_PCLK_HPM_APBIF_MFC, MFC_DIV_PCLK_MFC_150, CG_CTRL_VAL_PCLK_MFC_150_HPM_APBIF_MFC, 0);
|
|
CLK_GATE(MFC_GATE_PCLK_SFW_MFC_0, MFC_DIV_PCLK_MFC_150, CG_CTRL_VAL_PCLK_MFC_150_SECURE_SFW_MFC_0, 0);
|
|
CLK_GATE(MFC_GATE_PCLK_SFW_MFC_1, MFC_DIV_PCLK_MFC_150, CG_CTRL_VAL_PCLK_MFC_150_SECURE_SFW_MFC_1, 0);
|
|
CLK_GATE(MFC_GATE_SCLK_PROMISE_MFC, TOP_GATE_SCLK_PROMISE_INT, CG_CTRL_VAL_SCLK_MFC_PROMISE, 0);
|
|
CLK_GATE(MIF0_GATE_ACLK_APSCDC, U_DFI_CLK_GEN_MIF0, CLK_ENABLE_ACLK_MIF0, 3);
|
|
CLK_GATE(MIF0_GATE_ACLK_PPC_DEBUG, U_DFI_CLK_GEN_MIF0, CLK_ENABLE_ACLK_MIF0, 2);
|
|
CLK_GATE(MIF0_GATE_ACLK_PPC_DVFS, U_DFI_CLK_GEN_MIF0, CLK_ENABLE_ACLK_MIF0, 1);
|
|
CLK_GATE(MIF0_GATE_ACLK_SMC, U_DFI_CLK_GEN_MIF0, CLK_ENABLE_ACLK_MIF0, 0);
|
|
CLK_GATE(MIF0_GATE_PCLK_SMC1, MIF0_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF0, 9);
|
|
CLK_GATE(MIF0_GATE_PCLK_DMC_MISC, MIF0_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF0, 8);
|
|
CLK_GATE(MIF0_GATE_PCLK_PPC_DEBUG, MIF0_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF0, 7);
|
|
CLK_GATE(MIF0_GATE_PCLK_PPC_DVFS, MIF0_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF0, 6);
|
|
CLK_GATE(MIF0_GATE_PCLK_SYSREG_MIF, MIF0_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF0, 5);
|
|
CLK_GATE(MIF0_GATE_PCLK_HPM, MIF0_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF0, 4);
|
|
CLK_GATE(MIF0_GATE_ACLK_AXI_ASYNC, MIF0_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF0, 3);
|
|
CLK_GATE(MIF0_GATE_PCLK_MIFP, MIF0_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF0, 2);
|
|
CLK_GATE(MIF0_GATE_PCLK_PMU_MIF, MIF0_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF0, 1);
|
|
CLK_GATE(MIF0_GATE_PCLK_LPDDR4PHY, MIF0_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF0, 0);
|
|
CLK_GATE(MIF0_GATE_PCLK_SMC2, MIF0_DIV_PCLK_MIF, CLK_ENABLE_ACLK_MIF0_SECURE_DREX_TZ, 0);
|
|
CLK_GATE(MIF0_GATE_SCLK_PROMISE, MIF0_DIV_SCLK_HPM_MIF, CLK_ENABLE_SCLK_HPM_MIF0, 0);
|
|
CLK_GATE(MIF0_GATE_RCLK_DREX, OSCCLK, CLK_ENABLE_SCLK_RCLK_DREX_MIF0, 0);
|
|
CLK_GATE(MIF1_GATE_ACLK_APSCDC, U_DFI_CLK_GEN_MIF1, CLK_ENABLE_ACLK_MIF1, 3);
|
|
CLK_GATE(MIF1_GATE_ACLK_PPC_DEBUG, U_DFI_CLK_GEN_MIF1, CLK_ENABLE_ACLK_MIF1, 2);
|
|
CLK_GATE(MIF1_GATE_ACLK_PPC_DVFS, U_DFI_CLK_GEN_MIF1, CLK_ENABLE_ACLK_MIF1, 1);
|
|
CLK_GATE(MIF1_GATE_ACLK_SMC, U_DFI_CLK_GEN_MIF1, CLK_ENABLE_ACLK_MIF1, 0);
|
|
CLK_GATE(MIF1_GATE_PCLK_SMC1, MIF1_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF1, 9);
|
|
CLK_GATE(MIF1_GATE_PCLK_DMC_MISC, MIF1_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF1, 8);
|
|
CLK_GATE(MIF1_GATE_PCLK_PPC_DEBUG, MIF1_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF1, 7);
|
|
CLK_GATE(MIF1_GATE_PCLK_PPC_DVFS, MIF1_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF1, 6);
|
|
CLK_GATE(MIF1_GATE_PCLK_SYSREG_MIF, MIF1_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF1, 5);
|
|
CLK_GATE(MIF1_GATE_PCLK_HPM, MIF1_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF1, 4);
|
|
CLK_GATE(MIF1_GATE_ACLK_AXI_ASYNC, MIF1_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF1, 3);
|
|
CLK_GATE(MIF1_GATE_PCLK_MIFP, MIF1_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF1, 2);
|
|
CLK_GATE(MIF1_GATE_PCLK_PMU_MIF, MIF1_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF1, 1);
|
|
CLK_GATE(MIF1_GATE_PCLK_LPDDR4PHY, MIF1_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF1, 0);
|
|
CLK_GATE(MIF1_GATE_PCLK_SMC2, MIF1_DIV_PCLK_MIF, CLK_ENABLE_ACLK_MIF1_SECURE_DREX_TZ, 0);
|
|
CLK_GATE(MIF1_GATE_SCLK_PROMISE, MIF1_DIV_SCLK_HPM_MIF, CLK_ENABLE_SCLK_HPM_MIF1, 0);
|
|
CLK_GATE(MIF1_GATE_RCLK_DREX, OSCCLK, CLK_ENABLE_SCLK_RCLK_DREX_MIF1, 0);
|
|
CLK_GATE(MIF2_GATE_ACLK_APSCDC, U_DFI_CLK_GEN_MIF2, CLK_ENABLE_ACLK_MIF2, 3);
|
|
CLK_GATE(MIF2_GATE_ACLK_PPC_DEBUG, U_DFI_CLK_GEN_MIF2, CLK_ENABLE_ACLK_MIF2, 2);
|
|
CLK_GATE(MIF2_GATE_ACLK_PPC_DVFS, U_DFI_CLK_GEN_MIF2, CLK_ENABLE_ACLK_MIF2, 1);
|
|
CLK_GATE(MIF2_GATE_ACLK_SMC, U_DFI_CLK_GEN_MIF2, CLK_ENABLE_ACLK_MIF2, 0);
|
|
CLK_GATE(MIF2_GATE_PCLK_SMC1, MIF2_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF2, 9);
|
|
CLK_GATE(MIF2_GATE_PCLK_DMC_MISC, MIF2_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF2, 8);
|
|
CLK_GATE(MIF2_GATE_PCLK_PPC_DEBUG, MIF2_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF2, 7);
|
|
CLK_GATE(MIF2_GATE_PCLK_PPC_DVFS, MIF2_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF2, 6);
|
|
CLK_GATE(MIF2_GATE_PCLK_SYSREG_MIF, MIF2_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF2, 5);
|
|
CLK_GATE(MIF2_GATE_PCLK_HPM, MIF2_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF2, 4);
|
|
CLK_GATE(MIF2_GATE_ACLK_AXI_ASYNC, MIF2_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF2, 3);
|
|
CLK_GATE(MIF2_GATE_PCLK_MIFP, MIF2_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF2, 2);
|
|
CLK_GATE(MIF2_GATE_PCLK_PMU_MIF, MIF2_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF2, 1);
|
|
CLK_GATE(MIF2_GATE_PCLK_LPDDR4PHY, MIF2_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF2, 0);
|
|
CLK_GATE(MIF2_GATE_PCLK_SMC2, MIF2_DIV_PCLK_MIF, CLK_ENABLE_ACLK_MIF2_SECURE_DREX_TZ, 0);
|
|
CLK_GATE(MIF2_GATE_SCLK_PROMISE, MIF2_DIV_SCLK_HPM_MIF, CLK_ENABLE_SCLK_HPM_MIF2, 0);
|
|
CLK_GATE(MIF2_GATE_RCLK_DREX, OSCCLK, CLK_ENABLE_SCLK_RCLK_DREX_MIF2, 0);
|
|
CLK_GATE(MIF3_GATE_ACLK_APSCDC, U_DFI_CLK_GEN_MIF3, CLK_ENABLE_ACLK_MIF3, 3);
|
|
CLK_GATE(MIF3_GATE_ACLK_PPC_DEBUG, U_DFI_CLK_GEN_MIF3, CLK_ENABLE_ACLK_MIF3, 2);
|
|
CLK_GATE(MIF3_GATE_ACLK_PPC_DVFS, U_DFI_CLK_GEN_MIF3, CLK_ENABLE_ACLK_MIF3, 1);
|
|
CLK_GATE(MIF3_GATE_ACLK_SMC, U_DFI_CLK_GEN_MIF3, CLK_ENABLE_ACLK_MIF3, 0);
|
|
CLK_GATE(MIF3_GATE_PCLK_SMC1, MIF3_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF3, 9);
|
|
CLK_GATE(MIF3_GATE_PCLK_DMC_MISC, MIF3_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF3, 8);
|
|
CLK_GATE(MIF3_GATE_PCLK_PPC_DEBUG, MIF3_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF3, 7);
|
|
CLK_GATE(MIF3_GATE_PCLK_PPC_DVFS, MIF3_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF3, 6);
|
|
CLK_GATE(MIF3_GATE_PCLK_SYSREG_MIF, MIF3_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF3, 5);
|
|
CLK_GATE(MIF3_GATE_PCLK_HPM, MIF3_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF3, 4);
|
|
CLK_GATE(MIF3_GATE_ACLK_AXI_ASYNC, MIF3_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF3, 3);
|
|
CLK_GATE(MIF3_GATE_PCLK_MIFP, MIF3_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF3, 2);
|
|
CLK_GATE(MIF3_GATE_PCLK_PMU_MIF, MIF3_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF3, 1);
|
|
CLK_GATE(MIF3_GATE_PCLK_LPDDR4PHY, MIF3_DIV_PCLK_MIF, CLK_ENABLE_PCLK_MIF3, 0);
|
|
CLK_GATE(MIF3_GATE_PCLK_SMC2, MIF3_DIV_PCLK_MIF, CLK_ENABLE_ACLK_MIF3_SECURE_DREX_TZ, 0);
|
|
CLK_GATE(MIF3_GATE_SCLK_PROMISE, MIF3_DIV_SCLK_HPM_MIF, CLK_ENABLE_SCLK_HPM_MIF3, 0);
|
|
CLK_GATE(MIF3_GATE_RCLK_DREX, OSCCLK, CLK_ENABLE_SCLK_RCLK_DREX_MIF3, 0);
|
|
CLK_GATE(MNGS_GATE_ACLK_ASYNCPACES_MNGS_SCI, MNGS_DIV_ACLK_MNGS, CLK_ENABLE_ACLK_MNGS, 0);
|
|
CLK_GATE(MNGS_GATE_ATCLKS_ATB_MNGS3_CSSYS, MNGS_DIV_ATCLK_MNGS_CORE, CLK_ENABLE_ATCLK_MNGS_CORE, 3);
|
|
CLK_GATE(MNGS_GATE_ATCLKS_ATB_MNGS2_CSSYS, MNGS_DIV_ATCLK_MNGS_CORE, CLK_ENABLE_ATCLK_MNGS_CORE, 2);
|
|
CLK_GATE(MNGS_GATE_ATCLKS_ATB_MNGS1_CSSYS, MNGS_DIV_ATCLK_MNGS_CORE, CLK_ENABLE_ATCLK_MNGS_CORE, 1);
|
|
CLK_GATE(MNGS_GATE_ATCLKS_ATB_MNGS0_CSSYS, MNGS_DIV_ATCLK_MNGS_CORE, CLK_ENABLE_ATCLK_MNGS_CORE, 0);
|
|
CLK_GATE(MNGS_GATE_ATCLK_XIU_MNGSX_2x1, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 16);
|
|
CLK_GATE(MNGS_GATE_ATCLK_STM_TXACTOR, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 15);
|
|
CLK_GATE(MNGS_GATE_ATCLK_ATB_BDU_CSSYS, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 14);
|
|
CLK_GATE(MNGS_GATE_ATCLK_ATB_AUD_CSSYS, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 13);
|
|
CLK_GATE(MNGS_GATE_ATCLK_ATB_CAM1_CSSYS, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 12);
|
|
CLK_GATE(MNGS_GATE_ATCLK_ATB_APOLLO3_CSSYS, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 11);
|
|
CLK_GATE(MNGS_GATE_ATCLK_ATB_APOLLO2_CSSYS, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 10);
|
|
CLK_GATE(MNGS_GATE_ATCLK_ATB_APOLLO1_CSSYS, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 9);
|
|
CLK_GATE(MNGS_GATE_ATCLK_ATB_APOLLO0_CSSYS, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 8);
|
|
CLK_GATE(MNGS_GATE_ATCLKM_ATB_MNGS3_CSSYS, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 7);
|
|
CLK_GATE(MNGS_GATE_ATCLKM_ATB_MNGS2_CSSYS, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 6);
|
|
CLK_GATE(MNGS_GATE_ATCLKM_ATB_MNGS1_CSSYS, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 5);
|
|
CLK_GATE(MNGS_GATE_ATCLKM_ATB_MNGS0_CSSYS, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 4);
|
|
CLK_GATE(MNGS_GATE_ATCLK_ASYNCAHB_CSSYS_SSS_ACLK, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 3);
|
|
CLK_GATE(MNGS_GATE_ATCLK_ASYNCLHAXI_CSSYS_ETR_ACLK, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 2);
|
|
CLK_GATE(MNGS_GATE_ATCLK_CSSYS_HCLK, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 1);
|
|
CLK_GATE(MNGS_GATE_ATCLK_CSSYS, MNGS_DIV_ATCLK_MNGS_SOC, CLK_ENABLE_ATCLK_MNGS_SOC, 0);
|
|
CLK_GATE(MNGS_GATE_ATCLK_CSSYS_TRACECLK, MNGS_DIV_ATCLK_MNGS_CSSYS_TRACECLK, CLK_ENABLE_ATCLK_MNGS_CSSYS_TRACECLK, 0);
|
|
CLK_GATE(MNGS_GATE_ATCLK_ASYNCATB_CAM1, MNGS_DIV_ATCLK_MNGS_ASYNCATB_CAM1, CLK_ENABLE_ATCLK_MNGS_ASYNCATB_CAM1, 0);
|
|
CLK_GATE(MNGS_GATE_ATCLK_ASYNCATB_AUD, MNGS_DIV_ATCLK_MNGS_ASYNCATB_AUD, CLK_ENABLE_ATCLK_MNGS_ASYNCATB_AUD, 0);
|
|
CLK_GATE(MNGS_GATE_PCLKDBG_ASAPBMST_CCORE_CSSYS, MNGS_DIV_PCLK_DBG_MNGS, CLK_ENABLE_PCLK_DBG_MNGS, 11);
|
|
CLK_GATE(MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_BDU, MNGS_DIV_PCLK_DBG_MNGS, CLK_ENABLE_PCLK_DBG_MNGS, 10);
|
|
CLK_GATE(MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_CAM1, MNGS_DIV_PCLK_DBG_MNGS, CLK_ENABLE_PCLK_DBG_MNGS, 9);
|
|
CLK_GATE(MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_AUD, MNGS_DIV_PCLK_DBG_MNGS, CLK_ENABLE_PCLK_DBG_MNGS, 8);
|
|
CLK_GATE(MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_APOLLO, MNGS_DIV_PCLK_DBG_MNGS, CLK_ENABLE_PCLK_DBG_MNGS, 7);
|
|
CLK_GATE(MNGS_GATE_PCLKDBG_DUMP_PC_MNGS, MNGS_DIV_PCLK_DBG_MNGS, CLK_ENABLE_PCLK_DBG_MNGS, 6);
|
|
CLK_GATE(MNGS_GATE_PCLKDBG_SECJTAG, MNGS_DIV_PCLK_DBG_MNGS, CLK_ENABLE_PCLK_DBG_MNGS, 5);
|
|
CLK_GATE(MNGS_GATE_PCLKDBG_AXIAP, MNGS_DIV_PCLK_DBG_MNGS, CLK_ENABLE_PCLK_DBG_MNGS, 4);
|
|
CLK_GATE(MNGS_GATE_PCLKDBG_CSSYS_CTMCLK, MNGS_DIV_PCLK_DBG_MNGS, CLK_ENABLE_PCLK_DBG_MNGS, 3);
|
|
CLK_GATE(MNGS_GATE_PCLKDBG_CSSYS, MNGS_DIV_PCLK_DBG_MNGS, CLK_ENABLE_PCLK_DBG_MNGS, 2);
|
|
CLK_GATE(MNGS_GATE_PCLKDBG_MNGS, MNGS_DIV_PCLK_DBG_MNGS, CLK_ENABLE_PCLK_DBG_MNGS, 1);
|
|
CLK_GATE(MNGS_GATE_PCLKDBG_ASYNCDAPSLV, MNGS_DIV_PCLK_DBG_MNGS, CLK_ENABLE_PCLK_DBG_MNGS, 0);
|
|
CLK_GATE(MNGS_GATE_PCLK_SYSREG_MNGS, MNGS_DIV_PCLK_MNGS, CLK_ENABLE_PCLK_MNGS, 5);
|
|
CLK_GATE(MNGS_GATE_PCLK_STM_TXACTOR, MNGS_DIV_PCLK_MNGS, CLK_ENABLE_PCLK_MNGS, 4);
|
|
CLK_GATE(MNGS_GATE_PCLK_XIU_PERI_MNGS_ACLK, MNGS_DIV_PCLK_MNGS, CLK_ENABLE_PCLK_MNGS, 3);
|
|
CLK_GATE(MNGS_GATE_PCLK_PMU_MNGS, MNGS_DIV_PCLK_MNGS, CLK_ENABLE_PCLK_MNGS, 2);
|
|
CLK_GATE(MNGS_GATE_PCLK_XIU_MNGSSFRX_1x2, MNGS_DIV_PCLK_MNGS, CLK_ENABLE_PCLK_MNGS, 1);
|
|
CLK_GATE(MNGS_GATE_PCLK_AXI2APB_MNGS_ACLK, MNGS_DIV_PCLK_MNGS, CLK_ENABLE_PCLK_MNGS, 0);
|
|
CLK_GATE(MNGS_GATE_PCLK_HPM_MNGS, MNGS_DIV_PCLK_MNGS, CLK_ENABLE_PCLK_HPM_MNGS, 0);
|
|
CLK_GATE(MNGS_GATE_SCLK_MNGS, MNGS_DIV_MNGS, CLK_ENABLE_SCLK_MNGS, 0);
|
|
CLK_GATE(MNGS_GATE_SCLK_PROMISE2_MNGS, MNGS_DIV_SCLK_PROMISE_MNGS, CLK_ENABLE_SCLK_PROMISE_MNGS, 2);
|
|
CLK_GATE(MNGS_GATE_SCLK_PROMISE1_MNGS, MNGS_DIV_SCLK_PROMISE_MNGS, CLK_ENABLE_SCLK_PROMISE_MNGS, 1);
|
|
CLK_GATE(MNGS_GATE_SCLK_PROMISE0_MNGS, MNGS_DIV_SCLK_PROMISE_MNGS, CLK_ENABLE_SCLK_PROMISE_MNGS, 0);
|
|
CLK_GATE(MSCL_GATE_ACLK_ASYNCAPB_JPEG, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL0_528, 9);
|
|
CLK_GATE(MSCL_GATE_ACLK_PPMU_MSCL_0, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL0_528, 8);
|
|
CLK_GATE(MSCL_GATE_ACLK_SMMU_JPEG, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL0_528, 7);
|
|
CLK_GATE(MSCL_GATE_ACLK_SMMU_MSCL_0, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL0_528, 6);
|
|
CLK_GATE(MSCL_GATE_ACLK_QE_JPEG, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL0_528, 5);
|
|
CLK_GATE(MSCL_GATE_ACLK_QE_MSCL_0, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL0_528, 4);
|
|
CLK_GATE(MSCL_GATE_ACLK_XIU_MSCLX_0, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL0_528, 3);
|
|
CLK_GATE(MSCL_GATE_ACLK_LH_ASYNC_SI_MSCL_0, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL0_528, 2);
|
|
CLK_GATE(MSCL_GATE_ACLK_JPEG, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL0_528, 1);
|
|
CLK_GATE(MSCL_GATE_ACLK_MSCL_0, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL0_528, 0);
|
|
CLK_GATE(MSCL_GATE_ACLK_SFW_MSCL_0, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL0_528_SECURE_SFW_MSCL_0, 0);
|
|
CLK_GATE(MSCL_GATE_ACLK_ASYNCAPB_G2D, MSCL_MUX_ACLK_MSCL1_528, CG_CTRL_VAL_ACLK_MSCL1_528, 10);
|
|
CLK_GATE(MSCL_GATE_ACLK_PPMU_MSCL_1, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL1_528, 9);
|
|
CLK_GATE(MSCL_GATE_ACLK_SMMU_G2D, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL1_528, 8);
|
|
CLK_GATE(MSCL_GATE_ACLK_SMMU_MSCL_1, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL1_528, 7);
|
|
CLK_GATE(MSCL_GATE_ACLK_QE_G2D, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL1_528, 6);
|
|
CLK_GATE(MSCL_GATE_ACLK_QE_MSCL_1, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL1_528, 5);
|
|
CLK_GATE(MSCL_GATE_ACLK_AXI2ACEL, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL1_528, 4);
|
|
CLK_GATE(MSCL_GATE_ACLK_XIU_MSCLX_1, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL1_528, 3);
|
|
CLK_GATE(MSCL_GATE_ACLK_LH_ASYNC_SI_MSCL_1, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL1_528, 2);
|
|
CLK_GATE(MSCL_GATE_ACLK_G2D, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL1_528, 1);
|
|
CLK_GATE(MSCL_GATE_ACLK_MSCL_1, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL1_528, 0);
|
|
CLK_GATE(MSCL_GATE_ACLK_SFW_MSCL_1, MSCL_MUX_ACLK_MSCL0_528_USER, CG_CTRL_VAL_ACLK_MSCL1_528_SECURE_SFW_MSCL_1, 0);
|
|
CLK_GATE(MSCL_GATE_ACLK_LH_ASYNC_MI_MSCLSFR, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 20);
|
|
CLK_GATE(MSCL_GATE_PCLK_PMU_MSCL, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 19);
|
|
CLK_GATE(MSCL_GATE_PCLK_SYSREG_MSCL, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 18);
|
|
CLK_GATE(MSCL_GATE_PCLK_CMU_MSCL, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 17);
|
|
CLK_GATE(MSCL_GATE_PCLK_PPMU_MSCL_1, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 16);
|
|
CLK_GATE(MSCL_GATE_PCLK_PPMU_MSCL_0, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 15);
|
|
CLK_GATE(MSCL_GATE_PCLK_SMMU_G2D, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 14);
|
|
CLK_GATE(MSCL_GATE_PCLK_SMMU_JPEG, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 13);
|
|
CLK_GATE(MSCL_GATE_PCLK_SMMU_MSCL_1, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 12);
|
|
CLK_GATE(MSCL_GATE_PCLK_SMMU_MSCL_0, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 11);
|
|
CLK_GATE(MSCL_GATE_PCLK_QE_G2D, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 10);
|
|
CLK_GATE(MSCL_GATE_PCLK_QE_JPEG, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 9);
|
|
CLK_GATE(MSCL_GATE_PCLK_QE_MSCL_1, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 8);
|
|
CLK_GATE(MSCL_GATE_PCLK_QE_MSCL_0, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 7);
|
|
CLK_GATE(MSCL_GATE_PCLK_ASYNCAPB_G2D, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 6);
|
|
CLK_GATE(MSCL_GATE_PCLK_ASYNCAPB_JPEG, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 5);
|
|
CLK_GATE(MSCL_GATE_PCLK_MSCL_1, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 4);
|
|
CLK_GATE(MSCL_GATE_PCLK_MSCL_0, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 3);
|
|
CLK_GATE(MSCL_GATE_ACLK_AXI2APB_MSCLSFR_1P, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 2);
|
|
CLK_GATE(MSCL_GATE_ACLK_AXI2APB_MSCLSFR_0P, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 1);
|
|
CLK_GATE(MSCL_GATE_ACLK_XIU_MSCLSFRX, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL, 0);
|
|
CLK_GATE(MSCL_GATE_PCLK_SFW_MSCL_0, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL_SECURE_SFW_MSCL_0, 0);
|
|
CLK_GATE(MSCL_GATE_PCLK_SFW_MSCL_1, MSCL_DIV_PCLK_MSCL, CG_CTRL_VAL_PCLK_MSCL_SECURE_SFW_MSCL_1, 0);
|
|
CLK_GATE(PERIC0_GATE_PCLK_HSI2C11, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 15);
|
|
CLK_GATE(PERIC0_GATE_PCLK_HSI2C10, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 14);
|
|
CLK_GATE(PERIC0_GATE_PCLK_HSI2C9, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 13);
|
|
CLK_GATE(PERIC0_GATE_PCLK_HSI2C5, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 12);
|
|
CLK_GATE(PERIC0_GATE_PCLK_HSI2C4, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 11);
|
|
CLK_GATE(PERIC0_GATE_PCLK_HSI2C1, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 10);
|
|
CLK_GATE(PERIC0_GATE_PCLK_HSI2C0, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 9);
|
|
CLK_GATE(PERIC0_GATE_PCLK_PWM, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 8);
|
|
CLK_GATE(PERIC0_GATE_PCLK_ADCIF, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 7);
|
|
CLK_GATE(PERIC0_GATE_PCLK_UART0, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 6);
|
|
CLK_GATE(PERIC0_GATE_PCLK_GPIO_BUS0, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 5);
|
|
CLK_GATE(PERIC0_GATE_PCLK_SYSREG_PERIC0, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 4);
|
|
CLK_GATE(PERIC0_GATE_PCLK_PMU_PERIC0, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 3);
|
|
CLK_GATE(PERIC0_GATE_PCLK_CMU_PERIC0, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 2);
|
|
CLK_GATE(PERIC0_GATE_ACLK_AXI2APB_PERIC0P, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 1);
|
|
CLK_GATE(PERIC0_GATE_ACLK_AXILHASYNCM_PERIC0, PERIC0_MUX_ACLK_PERIC0_66_USER, CG_CTRL_VAL_ACLK_PERIC0_66, 0);
|
|
CLK_GATE(PERIC0_GATE_SCLK_UART0, PERIC0_MUX_SCLK_UART0_USER, CG_CTRL_VAL_SCLK_UART0, 0);
|
|
CLK_GATE(PERIC0_GATE_SCLK_PWM, OSCCLK, CG_CTRL_VAL_SCLK_PWM, 0);
|
|
CLK_GATE(PERIC1_GATE_PCLK_SPI7, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 25);
|
|
CLK_GATE(PERIC1_GATE_PCLK_SPI6, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 24);
|
|
CLK_GATE(PERIC1_GATE_PCLK_SPI5, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 23);
|
|
CLK_GATE(PERIC1_GATE_PCLK_SPI4, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 22);
|
|
CLK_GATE(PERIC1_GATE_PCLK_SPI3, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 21);
|
|
CLK_GATE(PERIC1_GATE_PCLK_SPI2, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 20);
|
|
CLK_GATE(PERIC1_GATE_PCLK_SPI1, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 19);
|
|
CLK_GATE(PERIC1_GATE_PCLK_SPI0, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 18);
|
|
CLK_GATE(PERIC1_GATE_PCLK_UART5, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 17);
|
|
CLK_GATE(PERIC1_GATE_PCLK_UART4, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 16);
|
|
CLK_GATE(PERIC1_GATE_PCLK_UART3, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 15);
|
|
CLK_GATE(PERIC1_GATE_PCLK_UART2, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 14);
|
|
CLK_GATE(PERIC1_GATE_PCLK_UART1, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 13);
|
|
CLK_GATE(PERIC1_GATE_PCLK_GPIO_ESE, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 12);
|
|
CLK_GATE(PERIC1_GATE_PCLK_GPIO_FF, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 11);
|
|
CLK_GATE(PERIC1_GATE_PCLK_GPIO_TOUCH, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 10);
|
|
CLK_GATE(PERIC1_GATE_PCLK_GPIO_NFC, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 9);
|
|
CLK_GATE(PERIC1_GATE_PCLK_GPIO_PERIC1, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 8);
|
|
CLK_GATE(PERIC1_GATE_PCLK_SYSREG_PERIC1, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 7);
|
|
CLK_GATE(PERIC1_GATE_PCLK_PMU_PERIC1, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 6);
|
|
CLK_GATE(PERIC1_GATE_PCLK_CMU_PERIC1, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 5);
|
|
CLK_GATE(PERIC1_GATE_ACLK_AXI2APB_PERIC1_2P, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 4);
|
|
CLK_GATE(PERIC1_GATE_ACLK_AXI2APB_PERIC1_1P, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 3);
|
|
CLK_GATE(PERIC1_GATE_ACLK_AXI2APB_PERIC1_0P, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 2);
|
|
CLK_GATE(PERIC1_GATE_ACLK_XIU_PERIC1SFRX, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 1);
|
|
CLK_GATE(PERIC1_GATE_ACLK_AXILHASYNCM_PERIC1, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66, 0);
|
|
CLK_GATE(PERIC1_GATE_PCLK_HSI2C14, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66_HSI2C, 7);
|
|
CLK_GATE(PERIC1_GATE_PCLK_HSI2C13, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66_HSI2C, 6);
|
|
CLK_GATE(PERIC1_GATE_PCLK_HSI2C12, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66_HSI2C, 5);
|
|
CLK_GATE(PERIC1_GATE_PCLK_HSI2C8, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66_HSI2C, 4);
|
|
CLK_GATE(PERIC1_GATE_PCLK_HSI2C7, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66_HSI2C, 3);
|
|
CLK_GATE(PERIC1_GATE_PCLK_HSI2C6, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66_HSI2C, 2);
|
|
CLK_GATE(PERIC1_GATE_PCLK_HSI2C3, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66_HSI2C, 1);
|
|
CLK_GATE(PERIC1_GATE_PCLK_HSI2C2, PERIC1_MUX_ACLK_PERIC1_66_USER, CG_CTRL_VAL_ACLK_PERIC1_66_HSI2C, 0);
|
|
CLK_GATE(PERIC1_GATE_SCLK_SPI0, PERIC1_MUX_SCLK_SPI0_USER, CG_CTRL_VAL_SCLK_SPI0, 0);
|
|
CLK_GATE(PERIC1_GATE_SCLK_SPI1, PERIC1_MUX_SCLK_SPI1_USER, CG_CTRL_VAL_SCLK_SPI1, 0);
|
|
CLK_GATE(PERIC1_GATE_SCLK_SPI2, PERIC1_MUX_SCLK_SPI2_USER, CG_CTRL_VAL_SCLK_SPI2, 0);
|
|
CLK_GATE(PERIC1_GATE_SCLK_SPI3, PERIC1_MUX_SCLK_SPI3_USER, CG_CTRL_VAL_SCLK_SPI3, 0);
|
|
CLK_GATE(PERIC1_GATE_SCLK_SPI4, PERIC1_MUX_SCLK_SPI4_USER, CG_CTRL_VAL_SCLK_SPI4, 0);
|
|
CLK_GATE(PERIC1_GATE_SCLK_SPI5, PERIC1_MUX_SCLK_SPI5_USER, CG_CTRL_VAL_SCLK_SPI5, 0);
|
|
CLK_GATE(PERIC1_GATE_SCLK_SPI6, PERIC1_MUX_SCLK_SPI6_USER, CG_CTRL_VAL_SCLK_SPI6, 0);
|
|
CLK_GATE(PERIC1_GATE_SCLK_SPI7, PERIC1_MUX_SCLK_SPI7_USER, CG_CTRL_VAL_SCLK_SPI7, 0);
|
|
CLK_GATE(PERIC1_GATE_SCLK_UART1, PERIC1_MUX_SCLK_UART1_USER, CG_CTRL_VAL_SCLK_UART1, 0);
|
|
CLK_GATE(PERIC1_GATE_SCLK_UART2, PERIC1_MUX_SCLK_UART2_USER, CG_CTRL_VAL_SCLK_UART2, 0);
|
|
CLK_GATE(PERIC1_GATE_SCLK_UART3, PERIC1_MUX_SCLK_UART3_USER, CG_CTRL_VAL_SCLK_UART3, 0);
|
|
CLK_GATE(PERIC1_GATE_SCLK_UART4, PERIC1_MUX_SCLK_UART4_USER, CG_CTRL_VAL_SCLK_UART4, 0);
|
|
CLK_GATE(PERIC1_GATE_SCLK_UART5, PERIC1_MUX_SCLK_UART5_USER, CG_CTRL_VAL_SCLK_UART5, 0);
|
|
CLK_GATE(PERIS_GATE_PCLK_SFR_APBIF_HDMI_CEC, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS, 13);
|
|
CLK_GATE(PERIS_GATE_PCLK_SFR_APBIF_TMU, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS, 12);
|
|
CLK_GATE(PERIS_GATE_PCLK_RTC_APBIF, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS, 11);
|
|
CLK_GATE(PERIS_GATE_PCLK_MONOCNT_APBIF, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS, 10);
|
|
CLK_GATE(PERIS_GATE_PCLK_WDT_APOLLO, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS, 9);
|
|
CLK_GATE(PERIS_GATE_PCLK_WDT_MNGS, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS, 8);
|
|
CLK_GATE(PERIS_GATE_PCLK_MCT, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS, 7);
|
|
CLK_GATE(PERIS_GATE_PCLK_SYSREG_PERIS, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS, 6);
|
|
CLK_GATE(PERIS_GATE_PCLK_PMU_PERIS, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS, 5);
|
|
CLK_GATE(PERIS_GATE_PCLK_CMU_PERIS, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS, 4);
|
|
CLK_GATE(PERIS_GATE_ACLK_AXI2APB_PERIS1, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS, 3);
|
|
CLK_GATE(PERIS_GATE_ACLK_AXI2APB_PERIS0, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS, 2);
|
|
CLK_GATE(PERIS_GATE_ACLK_XIU_PERIS, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS, 1);
|
|
CLK_GATE(PERIS_GATE_ACLK_AXI_LH_ASYNC, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS, 0);
|
|
CLK_GATE(PERIS_GATE_PCLK_HPM_APBIF_PERIS, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_HPM_APBIF_PERIS, 0);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_15, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 15);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_14, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 14);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_13, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 13);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_12, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 12);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_11, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 11);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_10, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 10);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_9, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 9);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_8, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 8);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_7, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 7);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_6, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 6);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_5, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 5);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_4, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 4);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_3, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 3);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_2, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 2);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_1, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 1);
|
|
CLK_GATE(PERIS_GATE_PCLK_TZPC_0, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_TZPC, 0);
|
|
CLK_GATE(PERIS_GATE_PCLK_TOP_RTC, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_RTC, 0);
|
|
CLK_GATE(PERIS_GATE_PCLK_SFR_APBIF_CHIPID, PERIS_MUX_ACLK_PERIS_66_USER, CG_CTRL_VAL_ACLK_PERIS_SECURE_CHIPID, 0);
|
|
CLK_GATE(PERIS_GATE_SCLK_OTP_CON_TOP, OSCCLK, CG_CTRL_VAL_SCLK_PERIS_SECURE_OTP, 0);
|
|
CLK_GATE(PERIS_GATE_SCLK_CHIPID, OSCCLK, CG_CTRL_VAL_SCLK_PERIS_SECURE_CHIPID, 0);
|
|
CLK_GATE(PERIS_GATE_SCLK_TMU, OSCCLK, CG_CTRL_VAL_SCLK_PERIS, 0);
|
|
CLK_GATE(PERIS_GATE_SCLK_PROMISE_PERIS, TOP_GATE_SCLK_PROMISE_INT, CG_CTRL_VAL_SCLK_PERIS_PROMISE, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CCORE_800, TOP_DIV_ACLK_CCORE_800, CLK_ENABLE_ACLK_CCORE_800, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CCORE_264, TOP_DIV_ACLK_CCORE_264, CLK_ENABLE_ACLK_CCORE_264, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CCORE_G3D_800, TOP_DIV_ACLK_CCORE_G3D_800, CLK_ENABLE_ACLK_CCORE_G3D_800, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CCORE_528, TOP_DIV_ACLK_CCORE_528, CLK_ENABLE_ACLK_CCORE_528, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CCORE_132, TOP_DIV_ACLK_CCORE_132, CLK_ENABLE_ACLK_CCORE_132, 0);
|
|
CLK_GATE(TOP_GATE_PCLK_CCORE_66, TOP_DIV_PCLK_CCORE_66, CLK_ENABLE_PCLK_CCORE_66, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_BUS0_528, TOP_DIV_ACLK_BUS0_528, CLK_ENABLE_ACLK_BUS0_528_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_BUS0_200, TOP_DIV_ACLK_BUS0_200, CLK_ENABLE_ACLK_BUS0_200_TOP, 0);
|
|
CLK_GATE(TOP_GATE_PCLK_BUS0_132, TOP_DIV_PCLK_BUS0_132, CLK_ENABLE_PCLK_BUS0_132_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_BUS1_528, TOP_DIV_ACLK_BUS1_528, CLK_ENABLE_ACLK_BUS1_528_TOP, 0);
|
|
CLK_GATE(TOP_GATE_PCLK_BUS1_132, TOP_DIV_PCLK_BUS1_132, CLK_ENABLE_PCLK_BUS1_132_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_DISP0_0_400, TOP_DIV_ACLK_DISP0_0_400, CLK_ENABLE_ACLK_DISP0_0_400, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_DISP0_1_400, TOP_DIV_ACLK_DISP0_1_400, CLK_ENABLE_ACLK_DISP0_1_400, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_DISP1_0_400, TOP_DIV_ACLK_DISP1_0_400, CLK_ENABLE_ACLK_DISP1_0_400, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_DISP1_1_400, TOP_DIV_ACLK_DISP1_1_400, CLK_ENABLE_ACLK_DISP1_1_400, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_MFC_600, TOP_DIV_ACLK_MFC_600, CLK_ENABLE_ACLK_MFC_600, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_MSCL0_528, TOP_DIV_ACLK_MSCL0_528, CLK_ENABLE_ACLK_MSCL0_528, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_MSCL1_528, TOP_DIV_ACLK_MSCL1_528, CLK_ENABLE_ACLK_MSCL1_528, 1);
|
|
CLK_GATE(TOP_GATE_ACLK_IMEM_266, TOP_DIV_ACLK_IMEM_266, CLK_ENABLE_ACLK_IMEM_266, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_IMEM_200, TOP_DIV_ACLK_IMEM_200, CLK_ENABLE_ACLK_IMEM_200, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_IMEM_100, TOP_DIV_ACLK_IMEM_100, CLK_ENABLE_ACLK_IMEM_100, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_FSYS0_200, TOP_DIV_ACLK_FSYS0_200, CLK_ENABLE_ACLK_FSYS0_200, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_FSYS1_200, TOP_DIV_ACLK_FSYS1_200, CLK_ENABLE_ACLK_FSYS1_200, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_PERIS_66, TOP_DIV_ACLK_PERIS_66, CLK_ENABLE_ACLK_PERIS_66, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_PERIC0_66, TOP_DIV_ACLK_PERIC0_66, CLK_ENABLE_ACLK_PERIC0_66, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_PERIC1_66, TOP_DIV_ACLK_PERIC1_66, CLK_ENABLE_ACLK_PERIC1_66, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_ISP0_ISP0_528, TOP_DIV_ACLK_ISP0_ISP0_528, CLK_ENABLE_ACLK_ISP0_ISP0_528, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_ISP0_TPU_400, TOP_DIV_ACLK_ISP0_TPU_400, CLK_ENABLE_ACLK_ISP0_TPU_400, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_ISP0_TREX_528, TOP_DIV_ACLK_ISP0_TREX_528, CLK_ENABLE_ACLK_ISP0_TREX_528, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D, TOP_DIV_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D, CLK_ENABLE_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_ISP1_ISP1_468, TOP_DIV_ACLK_ISP1_ISP1_468, CLK_ENABLE_ACLK_ISP1_ISP1_468, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CAM0_CSIS0_414, TOP_DIV_ACLK_CAM0_CSIS0_414, CLK_ENABLE_ACLK_CAM0_CSIS1_414, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CAM0_CSIS1_168, TOP_DIV_ACLK_CAM0_CSIS1_168, CLK_ENABLE_ACLK_CAM0_CSIS1_168_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CAM0_CSIS2_234, TOP_DIV_ACLK_CAM0_CSIS2_234, CLK_ENABLE_ACLK_CAM0_CSIS2_234_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CAM0_3AA0_414, TOP_DIV_ACLK_CAM0_3AA0_414, CLK_ENABLE_ACLK_CAM0_3AA0_414_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CAM0_3AA1_414, TOP_DIV_ACLK_CAM0_3AA1_414, CLK_ENABLE_ACLK_CAM0_3AA1_414_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CAM0_CSIS3_132, TOP_DIV_ACLK_CAM0_CSIS3_132, CLK_ENABLE_ACLK_CAM0_CSIS3_132_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CAM0_TREX_528, TOP_DIV_ACLK_CAM0_TREX_528, CLK_ENABLE_ACLK_CAM0_TREX_528_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CAM1_ARM_672, TOP_DIV_ACLK_CAM1_ARM_672, CLK_ENABLE_ACLK_CAM1_ARM_672_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CAM1_TREX_VRA_528, TOP_DIV_ACLK_CAM1_TREX_VRA_528, CLK_ENABLE_ACLK_CAM1_TREX_VRA_528_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CAM1_TREX_B_528, TOP_DIV_ACLK_CAM1_TREX_B_528, CLK_ENABLE_ACLK_CAM1_TREX_B_528_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CAM1_BUS_264, TOP_DIV_ACLK_CAM1_BUS_264, CLK_ENABLE_ACLK_CAM1_BUS_264_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CAM1_PERI_84, TOP_DIV_ACLK_CAM1_PERI_84, CLK_ENABLE_ACLK_CAM1_PERI_84, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CAM1_CSIS2_414, TOP_DIV_ACLK_CAM1_CSIS2_414, CLK_ENABLE_ACLK_CAM1_CSIS2_414_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CAM1_CSIS3_132, TOP_DIV_ACLK_CAM1_CSIS3_132, CLK_ENABLE_ACLK_CAM1_CSIS3_132_TOP, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_CAM1_SCL_566, TOP_DIV_ACLK_CAM1_SCL_566, CLK_ENABLE_ACLK_CAM1_SCL_566_TOP, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_DISP0_DECON0_ECLK0, TOP_DIV_SCLK_DISP0_DECON0_ECLK0, CLK_ENABLE_SCLK_DISP0_DECON0_ECLK0, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_DISP0_DECON0_VCLK0, TOP_DIV_SCLK_DISP0_DECON0_VCLK0, CLK_ENABLE_SCLK_DISP0_DECON0_VCLK0, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_DISP0_DECON0_VCLK1, TOP_DIV_SCLK_DISP0_DECON0_VCLK1, CLK_ENABLE_SCLK_DISP0_DECON0_VCLK1, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_DISP0_HDMI_AUDIO, TOP_DIV_SCLK_DISP0_HDMI_AUDIO, CLK_ENABLE_SCLK_DISP0_HDMI_ADUIO, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_DISP1_DECON1_ECLK0, TOP_DIV_SCLK_DISP1_DECON1_ECLK0, CLK_ENABLE_SCLK_DISP1_DECON1_ECLK0, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_DISP1_DECON1_ECLK1, TOP_DIV_SCLK_DISP1_DECON1_ECLK1, CLK_ENABLE_SCLK_DISP1_DECON1_ECLK1, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_FSYS0_USBDRD30, TOP_DIV_SCLK_FSYS0_USBDRD30, CLK_ENABLE_SCLK_FSYS0_USBDRD30, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_FSYS0_MMC0, TOP_DIV_SCLK_FSYS0_MMC0, CLK_ENABLE_SCLK_FSYS0_MMC0, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_FSYS0_UFSUNIPRO20, TOP_DIV_SCLK_FSYS0_UFSUNIPRO20, CLK_ENABLE_SCLK_FSYS0_UFSUNIPRO20, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_FSYS0_PHY_24M, TOP_DIV_SCLK_FSYS0_PHY_24M, CLK_ENABLE_SCLK_FSYS0_PHY_24M, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_FSYS0_UFSUNIPRO_CFG, TOP_DIV_SCLK_FSYS0_UFSUNIPRO_CFG, CLK_ENABLE_SCLK_FSYS0_UFSUNIPRO_CFG, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_FSYS1_MMC2, TOP_DIV_SCLK_FSYS1_MMC2, CLK_ENABLE_SCLK_FSYS1_MMC2, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_FSYS1_UFSUNIPRO20, TOP_DIV_SCLK_FSYS1_UFSUNIPRO20, CLK_ENABLE_SCLK_FSYS1_UFSUNIPRO20, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_FSYS1_PCIE_PHY, TOP_DIV_SCLK_FSYS1_PCIE_PHY, CLK_ENABLE_SCLK_FSYS1_PCIE_PHY, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_FSYS1_UFSUNIPRO_CFG, TOP_DIV_SCLK_FSYS1_UFSUNIPRO_CFG, CLK_ENABLE_SCLK_FSYS1_UFSUNIPRO_CFG, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PERIC0_UART0, TOP_DIV_SCLK_PERIC0_UART0, CLK_ENABLE_SCLK_PERIC0_UART0, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PERIC1_SPI0, TOP_DIV_SCLK_PERIC1_SPI0, CLK_ENABLE_SCLK_PERIC1_SPI0, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PERIC1_SPI1, TOP_DIV_SCLK_PERIC1_SPI1, CLK_ENABLE_SCLK_PERIC1_SPI1, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PERIC1_SPI2, TOP_DIV_SCLK_PERIC1_SPI2, CLK_ENABLE_SCLK_PERIC1_SPI2, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PERIC1_SPI3, TOP_DIV_SCLK_PERIC1_SPI3, CLK_ENABLE_SCLK_PERIC1_SPI3, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PERIC1_SPI4, TOP_DIV_SCLK_PERIC1_SPI4, CLK_ENABLE_SCLK_PERIC1_SPI4, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PERIC1_SPI5, TOP_DIV_SCLK_PERIC1_SPI5, CLK_ENABLE_SCLK_PERIC1_SPI5, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PERIC1_SPI6, TOP_DIV_SCLK_PERIC1_SPI6, CLK_ENABLE_SCLK_PERIC1_SPI6, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PERIC1_SPI7, TOP_DIV_SCLK_PERIC1_SPI7, CLK_ENABLE_SCLK_PERIC1_SPI7, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PERIC1_UART1, TOP_DIV_SCLK_PERIC1_UART1, CLK_ENABLE_SCLK_PERIC1_UART1, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PERIC1_UART2, TOP_DIV_SCLK_PERIC1_UART2, CLK_ENABLE_SCLK_PERIC1_UART2, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PERIC1_UART3, TOP_DIV_SCLK_PERIC1_UART3, CLK_ENABLE_SCLK_PERIC1_UART3, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PERIC1_UART4, TOP_DIV_SCLK_PERIC1_UART4, CLK_ENABLE_SCLK_PERIC1_UART4, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PERIC1_UART5, TOP_DIV_SCLK_PERIC1_UART5, CLK_ENABLE_SCLK_PERIC1_UART5, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_CAM1_ISP_SPI0, TOP_DIV_SCLK_CAM1_ISP_SPI0, CLK_ENABLE_SCLK_CAM1_ISP_SPI0_TOP, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_CAM1_ISP_SPI1, TOP_DIV_SCLK_CAM1_ISP_SPI1, CLK_ENABLE_SCLK_CAM1_ISP_SPI1_TOP, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_CAM1_ISP_UART, TOP_DIV_SCLK_CAM1_ISP_UART, CLK_ENABLE_SCLK_CAM1_ISP_UART_TOP, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_AP2CP_MIF_PLL_OUT, TOP_DIV_SCLK_AP2CP_MIF_PLL_OUT, CLK_ENABLE_SCLK_AP2CP_MIF_PLL_OUT, 0);
|
|
CLK_GATE(TOP_GATE_ACLK_PSCDC_400, TOP_DIV_ACLK_PSCDC_400, CLK_ENABLE_ACLK_PSCDC_400, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_BUS_PLL_MNGS, TOP_DIV_SCLK_BUS_PLL_MNGS, CLK_ENABLE_SCLK_BUS_PLL_MNGS, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_BUS_PLL_APOLLO, TOP_DIV_SCLK_BUS_PLL_APOLLO, CLK_ENABLE_SCLK_BUS_PLL_APOLLO, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_BUS_PLL_MIF, TOP_MUX_SCLK_BUS_PLL_MIF, CLK_ENABLE_SCLK_BUS_PLL_MIF, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_BUS_PLL_G3D, TOP_DIV_SCLK_BUS_PLL_G3D, CLK_ENABLE_SCLK_BUS_PLL_G3D, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_ISP_SENSOR0, TOP_DIV_SCLK_ISP_SENSOR0, CLK_ENABLE_SCLK_ISP_SENSOR0, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_ISP_SENSOR1, TOP_DIV_SCLK_ISP_SENSOR1, CLK_ENABLE_SCLK_ISP_SENSOR1, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_ISP_SENSOR2, TOP_DIV_SCLK_ISP_SENSOR2, CLK_ENABLE_SCLK_ISP_SENSOR2, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_ISP_SENSOR3, TOP_DIV_SCLK_ISP_SENSOR3, CLK_ENABLE_SCLK_ISP_SENSOR3, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PROMISE_INT, TOP_DIV_SCLK_PROMISE_INT, CLK_ENABLE_SCLK_PROMISE_INT, 0);
|
|
CLK_GATE(TOP_GATE_SCLK_PROMISE_DISP, TOP_DIV_SCLK_PROMISE_DISP, CLK_ENABLE_SCLK_PROMISE_DISP, 0);
|
|
|
|
|
|
/* HWACG SW type */
|
|
CLK_GATE(DISP0_HWACG_DSIM0, DISP0_MUX_ACLK_DISP0_0_400_USER, QSTATE_CTRL_DSIM0, 1);
|
|
CLK_GATE(DISP0_HWACG_DSIM1, DISP0_MUX_ACLK_DISP0_0_400_USER, QSTATE_CTRL_DSIM1, 1);
|
|
CLK_GATE(DISP0_HWACG_DSIM2, DISP0_MUX_ACLK_DISP0_0_400_USER, QSTATE_CTRL_DSIM2, 1);
|
|
CLK_GATE(DISP0_HWACG_HDMI, DISP0_MUX_ACLK_DISP0_0_400_USER, QSTATE_CTRL_HDMI, 1);
|
|
CLK_GATE(DISP0_HWACG_HDMI_AUDIO, DISP0_MUX_SCLK_DISP0_HDMI_AUDIO, QSTATE_CTRL_HDMI_AUDIO, 1);
|
|
CLK_GATE(DISP0_HWACG_DP, DISP0_MUX_ACLK_DISP0_0_400_USER, QSTATE_CTRL_DP, 1);
|
|
CLK_GATE(DISP0_HWACG_DISP0_MUX, DISP0_MUX_ACLK_DISP0_0_400_USER, QSTATE_CTRL_DISP0_MUX, 1);
|
|
CLK_GATE(DISP0_HWACG_HDMI_PHY, DISP0_MUX_ACLK_DISP0_0_400_USER, QSTATE_CTRL_HDMI_PHY, 1);
|
|
CLK_GATE(DISP0_HWACG_DISP1_400, DISP0_MUX_ACLK_DISP0_1_400, QSTATE_CTRL_DISP1_400, 1);
|
|
CLK_GATE(DISP0_HWACG_DECON0, DISP0_MUX_ACLK_DISP0_0_400_USER, QSTATE_CTRL_DECON0, 1);
|
|
CLK_GATE(DISP0_HWACG_HPM_APBIF_DISP0, DISP0_DIV_PCLK_DISP0_0_133, QSTATE_CTRL_HPM_APBIF_DISP0, 1);
|
|
CLK_GATE(DISP0_HWACG_PROMISE_DISP0, TOP_GATE_SCLK_PROMISE_INT, QSTATE_CTRL_PROMISE_DISP0, 1);
|
|
CLK_GATE(DISP0_HWACG_DPTX_PHY, OSCCLK, QSTATE_CTRL_DPTX_PHY, 1);
|
|
CLK_GATE(DISP0_HWACG_MIPI_DPHY_M1S0, OSCCLK, QSTATE_CTRL_MIPI_DPHY_M1S0, 1);
|
|
CLK_GATE(DISP0_HWACG_MIPI_DPHY_M4S0, OSCCLK, QSTATE_CTRL_MIPI_DPHY_M4S0, 1);
|
|
CLK_GATE(DISP0_HWACG_MIPI_DPHY_M4S4, OSCCLK, QSTATE_CTRL_MIPI_DPHY_M4S4, 1);
|
|
CLK_GATE(DISP1_HWACG_DECON1_ECLK_0, DISP1_DIV_SCLK_DECON1_ECLK0, QSTATE_CTRL_DECON1_ECLK_0, 1);
|
|
CLK_GATE(DISP1_HWACG_DECON1_ECLK_1, DISP1_DIV_SCLK_DECON1_ECLK1, QSTATE_CTRL_DECON1_ECLK_1, 1);
|
|
CLK_GATE(DISP1_HWACG_HPM_APBIF_DISP1, DISP0_DIV_PCLK_DISP0_0_133, QSTATE_CTRL_HPM_APBIF_DISP1, 1);
|
|
CLK_GATE(DISP1_HWACG_PROMISE_DISP1, TOP_GATE_SCLK_PROMISE_INT, QSTATE_CTRL_PROMISE_DISP1, 1);
|
|
CLK_GATE(FSYS0_HWACG_USBDRD30, FSYS0_MUX_ACLK_FSYS0_200_USER, QSTATE_CTRL_USBDRD30, 1);
|
|
CLK_GATE(FSYS0_HWACG_QCH_USBDRD30, PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY, QCH_CTRL_USBDRD30, 0);
|
|
CLK_GATE(FSYS0_HWACG_UFS_LINK_EMBEDDED, FSYS0_MUX_ACLK_FSYS0_200_USER, QSTATE_CTRL_UFS_LINK_EMBEDDED, 1);
|
|
CLK_GATE(FSYS0_HWACG_USBHOST20, FSYS0_MUX_ACLK_FSYS0_200_USER, QSTATE_CTRL_USBHOST20, 1);
|
|
CLK_GATE(FSYS0_HWACG_USBHOST20_PHY, FSYS0_MUX_ACLK_FSYS0_200_USER, QSTATE_CTRL_USBHOST20_PHY, 1);
|
|
CLK_GATE(FSYS0_HWACG_GPIO_FSYS0, FSYS0_MUX_ACLK_FSYS0_200_USER, QSTATE_CTRL_GPIO_FSYS0, 1);
|
|
CLK_GATE(FSYS0_HWACG_HPM_APBIF_FSYS0, FSYS0_MUX_ACLK_FSYS0_200_USER, QSTATE_CTRL_HPM_APBIF_FSYS0, 1);
|
|
CLK_GATE(FSYS0_HWACG_PROMISE_FSYS0, TOP_GATE_SCLK_PROMISE_INT, QSTATE_CTRL_PROMISE_FSYS0, 1);
|
|
CLK_GATE(FSYS1_HWACG_SROMC_FSYS1, FSYS1_MUX_ACLK_FSYS1_200_USER, QSTATE_CTRL_SROMC_FSYS1, 1);
|
|
CLK_GATE(FSYS1_HWACG_GPIO_FSYS1, FSYS1_MUX_ACLK_FSYS1_200_USER, QSTATE_CTRL_GPIO_FSYS1, 1);
|
|
CLK_GATE(FSYS1_HWACG_HPM_APBIF_FSYS1, FSYS1_MUX_ACLK_FSYS1_200_USER, QSTATE_CTRL_HPM_APBIF_FSYS1, 1);
|
|
CLK_GATE(FSYS1_HWACG_PROMISE_FSYS1, TOP_GATE_SCLK_PROMISE_INT, QSTATE_CTRL_PROMISE_FSYS1, 1);
|
|
CLK_GATE(FSYS1_HWACG_PCIE_RC_LINK_WIFI0, FSYS1_MUX_ACLK_FSYS1_200_USER, QSTATE_CTRL_PCIE_RC_LINK_WIFI0, 1);
|
|
CLK_GATE(FSYS1_HWACG_PCIE_RC_LINK_WIFI1, FSYS1_MUX_ACLK_FSYS1_200_USER, QSTATE_CTRL_PCIE_RC_LINK_WIFI1, 1);
|
|
CLK_GATE(FSYS1_HWACG_PCIE_PCS_WIFI0, FSYS1_MUX_ACLK_FSYS1_200_USER, QSTATE_CTRL_PCIE_PCS_WIFI0, 1);
|
|
CLK_GATE(FSYS1_HWACG_PCIE_PCS_WIFI1, FSYS1_MUX_ACLK_FSYS1_200_USER, QSTATE_CTRL_PCIE_PCS_WIFI1, 1);
|
|
CLK_GATE(FSYS1_HWACG_PCIE_PHY_FSYS1_WIFI0, FSYS1_MUX_ACLK_FSYS1_200_USER, QSTATE_CTRL_PCIE_PHY_FSYS1_WIFI0, 1);
|
|
CLK_GATE(FSYS1_HWACG_PCIE_PHY_FSYS1_WIFI1, FSYS1_MUX_ACLK_FSYS1_200_USER, QSTATE_CTRL_PCIE_PHY_FSYS1_WIFI1, 1);
|
|
CLK_GATE(FSYS1_HWACG_UFS_LINK_SDCARD, FSYS1_MUX_ACLK_FSYS1_200_USER, QSTATE_CTRL_UFS_LINK_SDCARD, 1);
|
|
CLK_GATE(IMEM_HWACG_GIC, IMEM_MUX_ACLK_IMEM_200_USER, QSTATE_CTRL_GIC, 1);
|
|
CLK_GATE(IMEM_HWACG_ASYNCAHBM_SSS_ATLAS, IMEM_MUX_ACLK_IMEM_266_USER, QSTATE_CTRL_ASYNCAHBM_SSS_ATLAS, 1);
|
|
CLK_GATE(MFC_HWACG_HPM_APBIF_MFC, MFC_DIV_PCLK_MFC_150, QSTATE_CTRL_HPM_APBIF_MFC, 1);
|
|
CLK_GATE(MFC_HWACG_PROMISE_MFC, TOP_GATE_SCLK_PROMISE_INT, QSTATE_CTRL_PROMISE_MFC, 1);
|
|
CLK_GATE(PERIC0_HWACG_GPIO_BUS0, PERIC0_MUX_ACLK_PERIC0_66_USER, QSTATE_CTRL_GPIO_BUS0, 1);
|
|
CLK_GATE(PERIC0_HWACG_UART0, PERIC0_MUX_ACLK_PERIC0_66_USER, QSTATE_CTRL_UART0, 1);
|
|
CLK_GATE(PERIC0_HWACG_ADCIF, PERIC0_MUX_ACLK_PERIC0_66_USER, QSTATE_CTRL_ADCIF, 1);
|
|
CLK_GATE(PERIC0_HWACG_PWM, PERIC0_MUX_ACLK_PERIC0_66_USER, QSTATE_CTRL_PWM, 1);
|
|
CLK_GATE(PERIC0_HWACG_HSI2C0, PERIC0_MUX_ACLK_PERIC0_66_USER, QSTATE_CTRL_HSI2C0, 1);
|
|
CLK_GATE(PERIC0_HWACG_HSI2C1, PERIC0_MUX_ACLK_PERIC0_66_USER, QSTATE_CTRL_HSI2C1, 1);
|
|
CLK_GATE(PERIC0_HWACG_HSI2C4, PERIC0_MUX_ACLK_PERIC0_66_USER, QSTATE_CTRL_HSI2C4, 1);
|
|
CLK_GATE(PERIC0_HWACG_HSI2C5, PERIC0_MUX_ACLK_PERIC0_66_USER, QSTATE_CTRL_HSI2C5, 1);
|
|
CLK_GATE(PERIC0_HWACG_HSI2C9, PERIC0_MUX_ACLK_PERIC0_66_USER, QSTATE_CTRL_HSI2C9, 1);
|
|
CLK_GATE(PERIC0_HWACG_HSI2C10, PERIC0_MUX_ACLK_PERIC0_66_USER, QSTATE_CTRL_HSI2C10, 1);
|
|
CLK_GATE(PERIC0_HWACG_HSI2C11, PERIC0_MUX_ACLK_PERIC0_66_USER, QSTATE_CTRL_HSI2C11, 1);
|
|
CLK_GATE(PERIC1_HWACG_GPIO_PERIC1, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_GPIO_PERIC1, 1);
|
|
CLK_GATE(PERIC1_HWACG_GPIO_NFC, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_GPIO_NFC, 1);
|
|
CLK_GATE(PERIC1_HWACG_GPIO_TOUCH, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_GPIO_TOUCH, 1);
|
|
CLK_GATE(PERIC1_HWACG_GPIO_FF, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_GPIO_FF, 1);
|
|
CLK_GATE(PERIC1_HWACG_GPIO_ESE, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_GPIO_ESE, 1);
|
|
CLK_GATE(PERIC1_HWACG_UART1, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_UART1, 1);
|
|
CLK_GATE(PERIC1_HWACG_UART2, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_UART2, 1);
|
|
CLK_GATE(PERIC1_HWACG_UART3, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_UART3, 1);
|
|
CLK_GATE(PERIC1_HWACG_UART4, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_UART4, 1);
|
|
CLK_GATE(PERIC1_HWACG_UART5, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_UART5, 1);
|
|
CLK_GATE(PERIC1_HWACG_SPI0, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_SPI0, 1);
|
|
CLK_GATE(PERIC1_HWACG_SPI1, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_SPI1, 1);
|
|
CLK_GATE(PERIC1_HWACG_SPI2, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_SPI2, 1);
|
|
CLK_GATE(PERIC1_HWACG_SPI3, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_SPI3, 1);
|
|
CLK_GATE(PERIC1_HWACG_SPI4, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_SPI4, 1);
|
|
CLK_GATE(PERIC1_HWACG_SPI5, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_SPI5, 1);
|
|
CLK_GATE(PERIC1_HWACG_SPI6, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_SPI6, 1);
|
|
CLK_GATE(PERIC1_HWACG_SPI7, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_SPI7, 1);
|
|
CLK_GATE(PERIC1_HWACG_HSI2C2, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_HSI2C2, 1);
|
|
CLK_GATE(PERIC1_HWACG_HSI2C3, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_HSI2C3, 1);
|
|
CLK_GATE(PERIC1_HWACG_HSI2C6, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_HSI2C6, 1);
|
|
CLK_GATE(PERIC1_HWACG_HSI2C7, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_HSI2C7, 1);
|
|
CLK_GATE(PERIC1_HWACG_HSI2C8, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_HSI2C8, 1);
|
|
CLK_GATE(PERIC1_HWACG_HSI2C12, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_HSI2C12, 1);
|
|
CLK_GATE(PERIC1_HWACG_HSI2C13, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_HSI2C13, 1);
|
|
CLK_GATE(PERIC1_HWACG_HSI2C14, PERIC1_MUX_ACLK_PERIC1_66_USER, QSTATE_CTRL_HSI2C14, 1);
|
|
CLK_GATE(PERIS_HWACG_MCT, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_MCT, 1);
|
|
CLK_GATE(PERIS_HWACG_WDT_MNGS, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_WDT_MNGS, 1);
|
|
CLK_GATE(PERIS_HWACG_WDT_APOLLO, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_WDT_APOLLO, 1);
|
|
CLK_GATE(PERIS_HWACG_RTC_APBIF, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_RTC_APBIF, 1);
|
|
CLK_GATE(PERIS_HWACG_SFR_APBIF_TMU, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_SFR_APBIF_TMU, 1);
|
|
CLK_GATE(PERIS_HWACG_SFR_APBIF_HDMI_CEC, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_SFR_APBIF_HDMI_CEC, 1);
|
|
CLK_GATE(PERIS_HWACG_HPM_APBIF_PERIS, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_HPM_APBIF_PERIS, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_0, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_0, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_1, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_1, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_2, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_2, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_3, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_3, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_4, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_4, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_5, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_5, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_6, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_6, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_7, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_7, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_8, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_8, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_9, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_9, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_10, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_10, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_11, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_11, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_12, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_12, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_13, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_13, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_14, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_14, 1);
|
|
CLK_GATE(PERIS_HWACG_TZPC_15, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TZPC_15, 1);
|
|
CLK_GATE(PERIS_HWACG_TOP_RTC, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_TOP_RTC, 1);
|
|
CLK_GATE(PERIS_HWACG_OTP_CON_TOP, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_OTP_CON_TOP, 1);
|
|
CLK_GATE(PERIS_HWACG_SFR_APBIF_CHIPID, PERIS_MUX_ACLK_PERIS_66_USER, QSTATE_CTRL_SFR_APBIF_CHIPID, 1);
|
|
CLK_GATE(PERIS_HWACG_TMU, OSCCLK, QSTATE_CTRL_TMU, 1);
|
|
CLK_GATE(PERIS_HWACG_CHIPID, OSCCLK, QSTATE_CTRL_CHIPID, 1);
|
|
CLK_GATE(PERIS_HWACG_PROMISE_PERIS, TOP_GATE_SCLK_PROMISE_INT, QSTATE_CTRL_PROMISE_PERIS, 1);
|
|
CLK_GATE(CLKOUT_OSCCLK_NFC, 0, PMU_DEBUG1, 1);
|
|
CLK_GATE(CLKOUT_TCXO_26M, 0, PMU_DEBUG1, 19);
|
|
CLK_GATE(CLKOUT_TCXO_IN0, 0, PMU_DEBUG, 8);
|
|
CLK_GATE(CLKOUT_TCXO_IN1, 0, PMU_DEBUG, 9);
|
|
CLK_GATE(CLKOUT_TCXO_IN2, 0, PMU_DEBUG, 10);
|
|
CLK_GATE(CLKOUT_TCXO_IN3, 0, PMU_DEBUG, 11);
|
|
CLK_GATE(CLKOUT_TCXO_IN4, 0, PMU_DEBUG, 12);
|
|
CLK_GATE(CLKOUT_CLKOUT0_DISABLE, 0, PMU_DEBUG, 0);
|
|
|
|
static int strcmp_unalign_address(const char *src1, const char *src2)
|
|
{
|
|
for (; *src1 == *src2; src1++, src2++)
|
|
if (*src1 == '\0')
|
|
return 0;
|
|
|
|
return ((*(unsigned char *)src1 < *(unsigned char *)src2) ? -1 : 1);
|
|
}
|
|
|
|
static struct pwrcal_clk *clk_get_with_list(char *clk_name, struct pwrcal_clk **clk_list, int clk_count)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < clk_count; ++i) {
|
|
if (strcmp_unalign_address(clk_list[i]->name, clk_name) == 0)
|
|
return clk_list[i];
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
struct pwrcal_clk *clk_find(char *clk_name)
|
|
{
|
|
struct pwrcal_clk *ret_cal = NULL;
|
|
|
|
if (strstr(clk_name, "PLL"))
|
|
ret_cal = clk_get_with_list(clk_name, pll_type_list, NUM_OF_PLL_TYPE);
|
|
|
|
if (strstr(clk_name, "DIV"))
|
|
ret_cal = clk_get_with_list(clk_name, div_type_list, NUM_OF_DIV_TYPE);
|
|
|
|
if (strstr(clk_name, "MUX"))
|
|
ret_cal = clk_get_with_list(clk_name, mux_type_list, NUM_OF_MUX_TYPE);
|
|
|
|
if (strstr(clk_name, "GATE"))
|
|
ret_cal = clk_get_with_list(clk_name, gate_type_list, NUM_OF_GATE_TYPE);
|
|
|
|
return ret_cal;
|
|
}
|
|
|
|
void clk_pll_set_rate_table(struct pwrcal_pll *pll)
|
|
{
|
|
int i;
|
|
void *pll_block;
|
|
struct pwrcal_pll_rate_table *pll_rate_table;
|
|
struct ect_pll *pll_unit;
|
|
struct ect_pll_frequency *pll_frequency;
|
|
|
|
if (pll == NULL)
|
|
return;
|
|
|
|
pll_block = ect_get_block(BLOCK_PLL);
|
|
if (pll_block == NULL)
|
|
return;
|
|
|
|
pll_unit = ect_pll_get_pll(pll_block, (char *)pll->clk.name);
|
|
if (pll_unit == NULL)
|
|
return;
|
|
|
|
pll_rate_table = kzalloc(sizeof(struct pwrcal_pll_rate_table) * pll_unit->num_of_frequency, GFP_KERNEL);
|
|
if (pll_rate_table == NULL)
|
|
return;
|
|
|
|
for (i = 0; i < pll_unit->num_of_frequency; ++i) {
|
|
pll_frequency = &pll_unit->frequency_list[i];
|
|
|
|
pll_rate_table[i].rate = pll_frequency->frequency;
|
|
pll_rate_table[i].pdiv = pll_frequency->p;
|
|
pll_rate_table[i].mdiv = pll_frequency->m;
|
|
pll_rate_table[i].sdiv = pll_frequency->s;
|
|
pll_rate_table[i].kdiv = pll_frequency->k;
|
|
}
|
|
|
|
pll->rate_table = pll_rate_table;
|
|
pll->rate_count = pll_unit->num_of_frequency;
|
|
}
|
|
|
|
void clk_init(void)
|
|
{
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, OSCCLK);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, OSCCLK_26M);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, SCAN_CLK_OSC);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, I_CP2AP_MIF_CLK);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, OSCCLK_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, SCLK_CP2AP_AUD_CLK);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, IOCLK_AUDIOCDCLK0);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, IOCLK_SLIMBUS_CLK);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, IOCLK_I2S_BCLK);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, RTC_CLKIN);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, IOCLK_SPI0);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, IOCLK_SPI1);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, IOCLK_SPI2);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, IOCLK_SPI3);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, IOCLK_SPI4);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, IOCLK_SPI5);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, IOCLK_SPI6);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, IOCLK_SPI7);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_USB30_12MOHCI);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_UFS_TX0_SYMBOL_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_UFS_RX0_SYMBOL_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_UFS_RX_PWM_CLK_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_UFS_TX_PWM_CLK_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_UFS_REFCLK_OUT_SOC_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_USBHOST20_PHYCLOCK_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_USBHOST20_FREECLK_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_USBHOST20_CLK48MOHCI_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_UFS_LINK_SDCARD_TX1_SYMBOL_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_UFS_LINK_SDCARD_RX1_SYMBOL_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_UFS_LINK_SDCARD_RX_PWM_CLK_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_UFS_LINK_SDCARD_TX_PWM_CLK_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_UFS_LINK_SDCARD_REFCLK_OUT_SOC_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_PCIE_WIFI0_TX0_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_PCIE_WIFI0_RX0_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_PCIE_WIFI1_TX0_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_PCIE_WIFI1_RX0_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_PCIE_WIFI0_DIG_REFCLK_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_PCIE_WIFI1_DIG_REFCLK_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_MIPIDPHY0_BITCLKDIV2_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_MIPIDPHY1_BITCLKDIV2_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_MIPIDPHY2_BITCLKDIV2_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_HDMIPHY_PIXEL_CLKO_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_HDMIPHY_TMDS_CLKO_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_MIPIDPHY0_RXCLKESC0_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_MIPIDPHY1_RXCLKESC0_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_MIPIDPHY1_BITCLKDIV8_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_MIPIDPHY2_RXCLKESC0_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_MIPIDPHY2_BITCLKDIV8_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_DPPHY_CH0_TXD_CLK_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_DPPHY_CH1_TXD_CLK_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_DPPHY_CH2_TXD_CLK_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_DPPHY_CH3_TXD_CLK_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_PHY);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_RXBYTECLKHS0_CSIS0);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_RXBYTECLKHS1_CSIS0);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_RXBYTECLKHS2_CSIS0);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_RXBYTECLKHS3_CSIS0);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_RXBYTECLKHS0_CSIS1);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_RXBYTECLKHS1_CSIS1);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_RXBYTECLKHS0_CSIS2);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_RXBYTECLKHS1_CSIS2);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_RXBYTECLKHS2_CSIS2);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_RXBYTECLKHS3_CSIS2);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, PHYCLK_RXBYTECLKHS0_CSIS3);
|
|
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, TOP_FF_BUS0_PLL_DIV2);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, TOP_FF_BUS1_PLL_DIV2);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, TOP_FF_BUS2_PLL_DIV2);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, TOP_FF_BUS3_PLL_DIV2);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, TOP_FF_BUS3_PLL_DIV4);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, TOP_FF_MFC_PLL_DIV2);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, TOP_FF_ISP_PLL_DIV2);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, MIF0_FF_ACLK_MIF_PLL_DIV2);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, MIF0_FF_ACLK_MIF_PLL_DIV4);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, MIF1_FF_ACLK_MIF_PLL_DIV2);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, MIF1_FF_ACLK_MIF_PLL_DIV4);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, MIF2_FF_ACLK_MIF_PLL_DIV2);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, MIF2_FF_ACLK_MIF_PLL_DIV4);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, MIF3_FF_ACLK_MIF_PLL_DIV2);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, MIF3_FF_ACLK_MIF_PLL_DIV4);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, U_DFI_CLK_GEN_MIF0);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, U_DFI_CLK_GEN_MIF1);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, U_DFI_CLK_GEN_MIF2);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, U_DFI_CLK_GEN_MIF3);
|
|
|
|
ADD_CLK_TO_LIST(pll_type_list, MNGS_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, APOLLO_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, G3D_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, MIF_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, BUS0_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, BUS1_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, BUS2_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, BUS3_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, MFC_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, ISP_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, DISP_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, AUD_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, PCIE_PLL);
|
|
|
|
ADD_CLK_TO_LIST(mux_type_list, APOLLO_MUX_APOLLO_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, APOLLO_MUX_BUS_PLL_APOLLO_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, APOLLO_MUX_APOLLO);
|
|
ADD_CLK_TO_LIST(mux_type_list, AUD_MUX_AUD_PLL_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, AUD_MUX_SCLK_I2S);
|
|
ADD_CLK_TO_LIST(mux_type_list, AUD_MUX_SCLK_PCM);
|
|
ADD_CLK_TO_LIST(mux_type_list, AUD_MUX_CP2AP_AUD_CLK_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, AUD_MUX_ACLK_CA5);
|
|
ADD_CLK_TO_LIST(mux_type_list, AUD_MUX_CDCLK_AUD);
|
|
ADD_CLK_TO_LIST(mux_type_list, BUS0_MUX_ACLK_BUS0_528_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, BUS0_MUX_ACLK_BUS0_200_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, BUS0_MUX_PCLK_BUS0_132_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, BUS1_MUX_ACLK_BUS1_528_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, BUS1_MUX_PCLK_BUS1_132_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM0_MUX_ACLK_CAM0_CSIS0_414_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM0_MUX_ACLK_CAM0_CSIS1_168_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM0_MUX_ACLK_CAM0_CSIS2_234_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM0_MUX_ACLK_CAM0_CSIS3_132_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM0_MUX_ACLK_CAM0_3AA0_414_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM0_MUX_ACLK_CAM0_3AA1_414_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM0_MUX_ACLK_CAM0_TREX_528_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_ACLK_CAM1_ARM_672_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_ACLK_CAM1_TREX_VRA_528_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_ACLK_CAM1_TREX_B_528_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_ACLK_CAM1_BUS_264_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_ACLK_CAM1_PERI_84_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_ACLK_CAM1_CSIS2_414_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_ACLK_CAM1_CSIS3_132_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_ACLK_CAM1_SCL_566_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_SCLK_CAM1_ISP_SPI0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_SCLK_CAM1_ISP_SPI1_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_SCLK_CAM1_ISP_UART_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CCORE_MUX_ACLK_CCORE_800_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CCORE_MUX_ACLK_CCORE_264_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CCORE_MUX_ACLK_CCORE_G3D_800_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CCORE_MUX_ACLK_CCORE_528_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CCORE_MUX_ACLK_CCORE_132_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CCORE_MUX_PCLK_CCORE_66_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_DISP_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_ACLK_DISP0_0_400_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_ACLK_DISP0_1_400_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_SCLK_DISP0_DECON0_ECLK0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_SCLK_DISP0_DECON0_VCLK0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_SCLK_DISP0_DECON0_VCLK1_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_ACLK_DISP0_1_400);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_SCLK_DISP0_DECON0_ECLK0);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_SCLK_DISP0_DECON0_VCLK0);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_SCLK_DISP0_DECON0_VCLK1);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_SCLK_DISP0_HDMI_AUDIO);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP1_MUX_ACLK_DISP1_0_400_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP1_MUX_ACLK_DISP1_1_400_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP1_MUX_SCLK_DISP1_DECON1_ECLK0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP1_MUX_SCLK_DISP1_DECON1_ECLK1_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP1_MUX_SCLK_DISP1_600_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP1_MUX_ACLK_DISP1_1_400);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP1_MUX_SCLK_DISP1_DECON1_ECLK0);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP1_MUX_SCLK_DISP1_DECON1_ECLK1);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP1_MUX_SCLK_DECON1_ECLK1);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS0_MUX_ACLK_FSYS0_200_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS0_MUX_SCLK_FSYS0_USBDRD30_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS0_MUX_SCLK_FSYS0_MMC0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS0_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS0_MUX_SCLK_FSYS0_24M_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS0_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_CFG_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS1_MUX_ACLK_FSYS1_200_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS1_MUX_SCLK_FSYS1_MMC2_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS1_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS1_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_CFG_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS1_MUX_SCLK_FSYS1_PCIE_PHY_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS1_MUX_PCIE_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, G3D_MUX_G3D_PLL_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, G3D_MUX_BUS_PLL_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, G3D_MUX_G3D);
|
|
ADD_CLK_TO_LIST(mux_type_list, IMEM_MUX_ACLK_IMEM_266_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, IMEM_MUX_ACLK_IMEM_200_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, IMEM_MUX_ACLK_IMEM_100_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, ISP0_MUX_ACLK_ISP0_528_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, ISP0_MUX_ACLK_ISP0_TPU_400_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, ISP0_MUX_ACLK_ISP0_TREX_528_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, ISP0_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, ISP1_MUX_ACLK_ISP1_468_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, MFC_MUX_ACLK_MFC_600_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF0_MUX_MIF_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF0_MUX_BUS_PLL_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF0_MUX_ACLK_MIF_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF0_MUX_PCLK_MIF);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF0_MUX_SCLK_HPM_MIF);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF1_MUX_MIF_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF1_MUX_BUS_PLL_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF1_MUX_ACLK_MIF_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF1_MUX_PCLK_MIF);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF1_MUX_SCLK_HPM_MIF);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF2_MUX_MIF_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF2_MUX_BUS_PLL_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF2_MUX_ACLK_MIF_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF2_MUX_PCLK_MIF);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF2_MUX_SCLK_HPM_MIF);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF3_MUX_MIF_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF3_MUX_BUS_PLL_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF3_MUX_ACLK_MIF_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF3_MUX_PCLK_MIF);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF3_MUX_SCLK_HPM_MIF);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF0_MUX_PCLK_SMC);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF1_MUX_PCLK_SMC);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF2_MUX_PCLK_SMC);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF3_MUX_PCLK_SMC);
|
|
ADD_CLK_TO_LIST(mux_type_list, MNGS_MUX_MNGS_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, MNGS_MUX_BUS_PLL_MNGS_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, MNGS_MUX_MNGS);
|
|
ADD_CLK_TO_LIST(mux_type_list, MSCL_MUX_ACLK_MSCL0_528_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, MSCL_MUX_ACLK_MSCL1_528_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, MSCL_MUX_ACLK_MSCL1_528);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC0_MUX_ACLK_PERIC0_66_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC0_MUX_SCLK_UART0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC1_MUX_ACLK_PERIC1_66_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC1_MUX_SCLK_SPI0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC1_MUX_SCLK_SPI1_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC1_MUX_SCLK_SPI2_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC1_MUX_SCLK_SPI3_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC1_MUX_SCLK_SPI4_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC1_MUX_SCLK_SPI5_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC1_MUX_SCLK_SPI6_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC1_MUX_SCLK_SPI7_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC1_MUX_SCLK_UART1_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC1_MUX_SCLK_UART2_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC1_MUX_SCLK_UART3_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC1_MUX_SCLK_UART4_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIC1_MUX_SCLK_UART5_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, PERIS_MUX_ACLK_PERIS_66_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_BUS0_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_BUS1_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_BUS2_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_BUS3_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_MFC_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ISP_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_AUD_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_G3D_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_BUS0_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_BUS1_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_BUS2_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_BUS3_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_MFC_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_ISP_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CCORE_800);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CCORE_264);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CCORE_G3D_800);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CCORE_528);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CCORE_132);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_PCLK_CCORE_66);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_BUS0_528);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_BUS0_200);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_PCLK_BUS0_132);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_BUS1_528);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_PCLK_BUS1_132);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_DISP0_0_400);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_DISP0_1_400);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_DISP1_0_400);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_DISP1_1_400);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_MFC_600);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_MSCL0_528);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_MSCL1_528);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_IMEM_266);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_IMEM_200);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_IMEM_100);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_FSYS0_200);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_FSYS1_200);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_PERIS_66);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_PERIC0_66);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_PERIC1_66);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_ISP0_ISP0_528);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_ISP0_TPU_400);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_ISP0_TREX_528);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_ISP1_ISP1_468);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CAM0_CSIS0_414);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CAM0_CSIS1_168);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CAM0_CSIS2_234);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CAM0_3AA0_414);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CAM0_3AA1_414);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CAM0_CSIS3_132);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CAM0_TREX_528);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CAM1_ARM_672);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CAM1_TREX_VRA_528);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CAM1_TREX_B_528);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CAM1_BUS_264);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CAM1_PERI_84);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CAM1_CSIS2_414);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CAM1_CSIS3_132);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_CAM1_SCL_566);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_DISP0_DECON0_ECLK0);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_DISP0_DECON0_VCLK0);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_DISP0_DECON0_VCLK1);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_DISP0_HDMI_AUDIO);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_DISP1_DECON1_ECLK0);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_DISP1_DECON1_ECLK1);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_FSYS0_USBDRD30);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_FSYS0_MMC0);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_FSYS0_UFSUNIPRO20);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_FSYS0_PHY_24M);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_FSYS0_UFSUNIPRO_CFG);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_FSYS1_MMC2);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_FSYS1_UFSUNIPRO20);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_FSYS1_PCIE_PHY);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_FSYS1_UFSUNIPRO_CFG);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PERIC0_UART0);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PERIC1_SPI0);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PERIC1_SPI1);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PERIC1_SPI2);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PERIC1_SPI3);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PERIC1_SPI4);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PERIC1_SPI5);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PERIC1_SPI6);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PERIC1_SPI7);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PERIC1_UART1);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PERIC1_UART2);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PERIC1_UART3);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PERIC1_UART4);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PERIC1_UART5);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_CAM1_ISP_SPI0);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_CAM1_ISP_SPI1);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_CAM1_ISP_UART);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_AP2CP_MIF_PLL_OUT);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_PSCDC_400);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_BUS_PLL_MNGS);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_BUS_PLL_APOLLO);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_BUS_PLL_MIF);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_BUS_PLL_G3D);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_ISP_SENSOR0);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_ISP_SENSOR1);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_ISP_SENSOR2);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_ISP_SENSOR3);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PROMISE_INT);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_SCLK_PROMISE_DISP);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_CP2AP_MIF_CLK_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_MIF_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_BUS_PLL_MIF);
|
|
ADD_CLK_TO_LIST(mux_type_list, TOP_MUX_ACLK_MIF_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM0_MUX_PHYCLK_RXBYTECLKHS0_CSIS0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM0_MUX_PHYCLK_RXBYTECLKHS1_CSIS0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM0_MUX_PHYCLK_RXBYTECLKHS2_CSIS0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM0_MUX_PHYCLK_RXBYTECLKHS3_CSIS0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM0_MUX_PHYCLK_RXBYTECLKHS0_CSIS1_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM0_MUX_PHYCLK_RXBYTECLKHS1_CSIS1_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_PHYCLK_RXBYTECLKHS0_CSIS2_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_PHYCLK_RXBYTECLKHS1_CSIS2_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_PHYCLK_RXBYTECLKHS2_CSIS2_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_PHYCLK_RXBYTECLKHS3_CSIS2_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CAM1_MUX_PHYCLK_RXBYTECLKHS0_CSIS3_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_SCLK_DISP0_HDMI_AUDIO_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_PHYCLK_HDMIPHY_PIXEL_CLKO_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_PHYCLK_HDMIPHY_TMDS_CLKO_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_PHYCLK_MIPIDPHY0_RXCLKESC0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_PHYCLK_MIPIDPHY1_RXCLKESC0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_PHYCLK_MIPIDPHY2_RXCLKESC0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV8_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_PHYCLK_DPPHY_CH0_TXD_CLK_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_PHYCLK_DPPHY_CH1_TXD_CLK_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_PHYCLK_DPPHY_CH2_TXD_CLK_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP0_MUX_PHYCLK_DPPHY_CH3_TXD_CLK_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP1_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP1_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP1_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISP1_MUX_PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS0_MUX_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS0_MUX_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS0_MUX_PHYCLK_UFS_TX0_SYMBOL_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS0_MUX_PHYCLK_UFS_RX0_SYMBOL_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS0_MUX_PHYCLK_USBHOST20_PHYCLOCK_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS0_MUX_PHYCLK_USBHOST20PHY_REF_CLK);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS1_MUX_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS1_MUX_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS1_MUX_PHYCLK_PCIE_WIFI0_TX0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS1_MUX_PHYCLK_PCIE_WIFI0_RX0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS1_MUX_PHYCLK_PCIE_WIFI1_TX0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS1_MUX_PHYCLK_PCIE_WIFI1_RX0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS1_MUX_PHYCLK_PCIE_WIFI0_DIG_REFCLK_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS1_MUX_PHYCLK_PCIE_WIFI1_DIG_REFCLK_USER);
|
|
|
|
ADD_CLK_TO_LIST(div_type_list, APOLLO_DIV_APOLLO);
|
|
ADD_CLK_TO_LIST(div_type_list, APOLLO_DIV_ACLK_APOLLO);
|
|
ADD_CLK_TO_LIST(div_type_list, APOLLO_DIV_ATCLK_APOLLO);
|
|
ADD_CLK_TO_LIST(div_type_list, APOLLO_DIV_PCLK_DBG_APOLLO);
|
|
ADD_CLK_TO_LIST(div_type_list, APOLLO_DIV_PCLK_APOLLO);
|
|
ADD_CLK_TO_LIST(div_type_list, APOLLO_DIV_CNTCLK_APOLLO);
|
|
ADD_CLK_TO_LIST(div_type_list, APOLLO_DIV_APOLLO_RUN_MONITOR);
|
|
ADD_CLK_TO_LIST(div_type_list, APOLLO_DIV_SCLK_PROMISE_APOLLO);
|
|
ADD_CLK_TO_LIST(div_type_list, APOLLO_DIV_APOLLO_PLL);
|
|
ADD_CLK_TO_LIST(div_type_list, AUD_DIV_AUD_CA5);
|
|
ADD_CLK_TO_LIST(div_type_list, AUD_DIV_ACLK_AUD);
|
|
ADD_CLK_TO_LIST(div_type_list, AUD_DIV_PCLK_DBG);
|
|
ADD_CLK_TO_LIST(div_type_list, AUD_DIV_ATCLK_AUD);
|
|
ADD_CLK_TO_LIST(div_type_list, AUD_DIV_AUD_CDCLK);
|
|
ADD_CLK_TO_LIST(div_type_list, AUD_DIV_SCLK_I2S);
|
|
ADD_CLK_TO_LIST(div_type_list, AUD_DIV_SCLK_PCM);
|
|
ADD_CLK_TO_LIST(div_type_list, AUD_DIV_SCLK_SLIMBUS);
|
|
ADD_CLK_TO_LIST(div_type_list, AUD_DIV_SCLK_CP_I2S);
|
|
ADD_CLK_TO_LIST(div_type_list, AUD_DIV_SCLK_ASRC);
|
|
ADD_CLK_TO_LIST(div_type_list, AUD_DIV_CP_CA5);
|
|
ADD_CLK_TO_LIST(div_type_list, AUD_DIV_CP_CDCLK);
|
|
ADD_CLK_TO_LIST(div_type_list, CAM0_DIV_PCLK_CAM0_CSIS0_207);
|
|
ADD_CLK_TO_LIST(div_type_list, CAM0_DIV_PCLK_CAM0_3AA0_207);
|
|
ADD_CLK_TO_LIST(div_type_list, CAM0_DIV_PCLK_CAM0_3AA1_207);
|
|
ADD_CLK_TO_LIST(div_type_list, CAM0_DIV_PCLK_CAM0_TREX_264);
|
|
ADD_CLK_TO_LIST(div_type_list, CAM0_DIV_PCLK_CAM0_TREX_132);
|
|
ADD_CLK_TO_LIST(div_type_list, CAM1_DIV_PCLK_CAM1_ARM_168);
|
|
ADD_CLK_TO_LIST(div_type_list, CAM1_DIV_PCLK_CAM1_TREX_VRA_264);
|
|
ADD_CLK_TO_LIST(div_type_list, CAM1_DIV_PCLK_CAM1_BUS_132);
|
|
ADD_CLK_TO_LIST(div_type_list, CCORE_DIV_SCLK_HPM_CCORE);
|
|
ADD_CLK_TO_LIST(div_type_list, DISP0_DIV_PCLK_DISP0_0_133);
|
|
ADD_CLK_TO_LIST(div_type_list, DISP0_DIV_SCLK_DECON0_ECLK0);
|
|
ADD_CLK_TO_LIST(div_type_list, DISP0_DIV_SCLK_DECON0_VCLK0);
|
|
ADD_CLK_TO_LIST(div_type_list, DISP0_DIV_SCLK_DECON0_VCLK1);
|
|
ADD_CLK_TO_LIST(div_type_list, DISP0_DIV_PHYCLK_HDMIPHY_PIXEL_CLKO);
|
|
ADD_CLK_TO_LIST(div_type_list, DISP0_DIV_PHYCLK_HDMIPHY_TMDS_20B_CLKO);
|
|
ADD_CLK_TO_LIST(div_type_list, DISP1_DIV_PCLK_DISP1_0_133);
|
|
ADD_CLK_TO_LIST(div_type_list, DISP1_DIV_SCLK_DECON1_ECLK0);
|
|
ADD_CLK_TO_LIST(div_type_list, DISP1_DIV_SCLK_DECON1_ECLK1);
|
|
ADD_CLK_TO_LIST(div_type_list, FSYS1_DIV_PCLK_COMBO_PHY_WIFI);
|
|
ADD_CLK_TO_LIST(div_type_list, G3D_DIV_ACLK_G3D);
|
|
ADD_CLK_TO_LIST(div_type_list, G3D_DIV_PCLK_G3D);
|
|
ADD_CLK_TO_LIST(div_type_list, G3D_DIV_SCLK_HPM_G3D);
|
|
ADD_CLK_TO_LIST(div_type_list, G3D_DIV_SCLK_ATE_G3D);
|
|
ADD_CLK_TO_LIST(div_type_list, ISP0_DIV_PCLK_ISP0);
|
|
ADD_CLK_TO_LIST(div_type_list, ISP0_DIV_PCLK_ISP0_TPU);
|
|
ADD_CLK_TO_LIST(div_type_list, ISP0_DIV_PCLK_ISP0_TREX_264);
|
|
ADD_CLK_TO_LIST(div_type_list, ISP0_DIV_PCLK_ISP0_TREX_132);
|
|
ADD_CLK_TO_LIST(div_type_list, ISP1_DIV_PCLK_ISP1_234);
|
|
ADD_CLK_TO_LIST(div_type_list, MFC_DIV_PCLK_MFC_150);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF0_DIV_PCLK_MIF);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF0_DIV_SCLK_HPM_MIF);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF1_DIV_PCLK_MIF);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF1_DIV_SCLK_HPM_MIF);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF2_DIV_PCLK_MIF);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF2_DIV_SCLK_HPM_MIF);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF3_DIV_PCLK_MIF);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF3_DIV_SCLK_HPM_MIF);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF0_DIV_PCLK_SMC);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF1_DIV_PCLK_SMC);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF2_DIV_PCLK_SMC);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF3_DIV_PCLK_SMC);
|
|
ADD_CLK_TO_LIST(div_type_list, MNGS_DIV_MNGS);
|
|
ADD_CLK_TO_LIST(div_type_list, MNGS_DIV_ACLK_MNGS);
|
|
ADD_CLK_TO_LIST(div_type_list, MNGS_DIV_ATCLK_MNGS_CORE);
|
|
ADD_CLK_TO_LIST(div_type_list, MNGS_DIV_ATCLK_MNGS_SOC);
|
|
ADD_CLK_TO_LIST(div_type_list, MNGS_DIV_ATCLK_MNGS_CSSYS_TRACECLK);
|
|
ADD_CLK_TO_LIST(div_type_list, MNGS_DIV_ATCLK_MNGS_ASYNCATB_CAM1);
|
|
ADD_CLK_TO_LIST(div_type_list, MNGS_DIV_ATCLK_MNGS_ASYNCATB_AUD);
|
|
ADD_CLK_TO_LIST(div_type_list, MNGS_DIV_PCLK_DBG_MNGS);
|
|
ADD_CLK_TO_LIST(div_type_list, MNGS_DIV_PCLK_RUN_MONITOR);
|
|
ADD_CLK_TO_LIST(div_type_list, MNGS_DIV_PCLK_MNGS);
|
|
ADD_CLK_TO_LIST(div_type_list, MNGS_DIV_CNTCLK_MNGS);
|
|
ADD_CLK_TO_LIST(div_type_list, MNGS_DIV_MNGS_RUN_MONITOR);
|
|
ADD_CLK_TO_LIST(div_type_list, MNGS_DIV_SCLK_PROMISE_MNGS);
|
|
ADD_CLK_TO_LIST(div_type_list, MNGS_DIV_MNGS_PLL);
|
|
ADD_CLK_TO_LIST(div_type_list, MSCL_DIV_PCLK_MSCL);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CCORE_800);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CCORE_264);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CCORE_G3D_800);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CCORE_528);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CCORE_132);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_PCLK_CCORE_66);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_BUS0_528);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_BUS0_200);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_PCLK_BUS0_132);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_BUS1_528);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_PCLK_BUS1_132);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_DISP0_0_400);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_DISP0_1_400);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_DISP1_0_400);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_DISP1_1_400);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_MFC_600);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_MSCL0_528);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_MSCL1_528);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_IMEM_266);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_IMEM_200);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_IMEM_100);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_FSYS0_200);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_FSYS1_200);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_PERIS_66);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_PERIC0_66);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_PERIC1_66);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_ISP0_ISP0_528);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_ISP0_TPU_400);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_ISP0_TREX_528);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_ISP1_ISP1_468);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CAM0_CSIS0_414);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CAM0_CSIS1_168);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CAM0_CSIS2_234);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CAM0_3AA0_414);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CAM0_3AA1_414);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CAM0_CSIS3_132);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CAM0_TREX_528);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CAM1_ARM_672);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CAM1_TREX_VRA_528);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CAM1_TREX_B_528);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CAM1_BUS_264);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CAM1_PERI_84);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CAM1_CSIS2_414);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CAM1_CSIS3_132);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_CAM1_SCL_566);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_DISP0_DECON0_ECLK0);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_DISP0_DECON0_VCLK0);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_DISP0_DECON0_VCLK1);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_DISP0_HDMI_AUDIO);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_DISP1_DECON1_ECLK0);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_DISP1_DECON1_ECLK1);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_FSYS0_USBDRD30);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_FSYS0_MMC0);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_FSYS0_UFSUNIPRO20);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_FSYS0_PHY_24M);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_FSYS0_UFSUNIPRO_CFG);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_FSYS1_MMC2);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_FSYS1_UFSUNIPRO20);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_FSYS1_PCIE_PHY);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_FSYS1_UFSUNIPRO_CFG);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PERIC0_UART0);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PERIC1_SPI0);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PERIC1_SPI1);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PERIC1_SPI2);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PERIC1_SPI3);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PERIC1_SPI4);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PERIC1_SPI5);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PERIC1_SPI6);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PERIC1_SPI7);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PERIC1_UART1);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PERIC1_UART2);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PERIC1_UART3);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PERIC1_UART4);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PERIC1_UART5);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_CAM1_ISP_SPI0);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_CAM1_ISP_SPI1);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_CAM1_ISP_UART);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_AP2CP_MIF_PLL_OUT);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_ACLK_PSCDC_400);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_BUS_PLL_MNGS);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_BUS_PLL_APOLLO);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_BUS_PLL_MIF);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_BUS_PLL_G3D);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_ISP_SENSOR0);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_ISP_SENSOR1);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_ISP_SENSOR2);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_ISP_SENSOR3);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PROMISE_INT);
|
|
ADD_CLK_TO_LIST(div_type_list, TOP_DIV_SCLK_PROMISE_DISP);
|
|
|
|
ADD_CLK_TO_LIST(gate_type_list, APOLLO_GATE_ACLK_ASYNCACES_APOLLO_CCI);
|
|
ADD_CLK_TO_LIST(gate_type_list, APOLLO_GATE_ACLK_ASATBSLV_APOLLO3_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, APOLLO_GATE_ACLK_ASATBSLV_APOLLO2_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, APOLLO_GATE_ACLK_ASATBSLV_APOLLO1_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, APOLLO_GATE_ACLK_ASATBSLV_APOLLO0_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, APOLLO_GATE_PCLKDBG_DUMP_PC_APOLLO);
|
|
ADD_CLK_TO_LIST(gate_type_list, APOLLO_GATE_PCLKDBG_ASAPBMST_CSSYS_APOLLO);
|
|
ADD_CLK_TO_LIST(gate_type_list, APOLLO_GATE_PCLK_SYSREG_APOLLO);
|
|
ADD_CLK_TO_LIST(gate_type_list, APOLLO_GATE_PCLK_PMU_APOLLO);
|
|
ADD_CLK_TO_LIST(gate_type_list, APOLLO_GATE_PCLK_AXI2APB_APOLLO_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, APOLLO_GATE_PCLK_XIU_PERI_APOLLO_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, APOLLO_GATE_PCLK_HPM_APOLLO);
|
|
ADD_CLK_TO_LIST(gate_type_list, APOLLO_GATE_SCLK_APOLLO);
|
|
ADD_CLK_TO_LIST(gate_type_list, APOLLO_GATE_SCLK_PROMISE_APOLLO);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_SCLK_CA5);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_PCLK_PPMU_AUD);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_PCLK_CP_I2S);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_PCLK_SYSREG_AUD);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_PCLK_GPIO_AUD);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_PCLK_PMU_AUD);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_PCLK_SLIMBUS);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_PCLK_PCM);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_PCLK_I2S);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_PCLK_TIMER);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_PCLK_SFR1);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_PCLK_SFR0);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_PCLK_SMMU);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_ACLK_PPMU_AUD);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_ACLK_INTR);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_ACLK_XIU_LPASSX);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_ACLK_SMMU);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_ACLK_AXI_LH_ASYNC_SI_TOP);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_ACLK_AXI_LH_ASYNC_MI_TOP);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_ACLK_AXI_US_32TO64);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_ACLK_SRAMC);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_ACLK_DMAC);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_PCLK_DBG);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_ACLK_ATCLK_AUD);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_SCLK_I2S);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_SCLK_PCM);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_SCLK_SLIMBUS);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_SCLK_CP_I2S);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_SCLK_ASRC);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_SCLK_SLIMBUS_CLKIN);
|
|
ADD_CLK_TO_LIST(gate_type_list, AUD_GATE_SCLK_I2S_BCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_ACLK_ACE_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_ACLK_LH_ISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_ACLK_LH_DISP11);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_ACLK_LH_DISP10);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_ACLK_LH_DISP01);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_ACLK_LH_DISP00);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_ACLK_LH_CAM1);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_ACLK_LH_CAM0);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_ACLK_TREX_BUS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_ACLK_LH_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_CMU_BUS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_TREX_BUS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_PMU_BUS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_SYSREG_BUS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_LH_FSYS1SFRX);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_LH_PERIC1P);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_LH_PERIC0P);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_LH_PERISFRX);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_LH_DISP1SFRX);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_LH_DISP0SFRX);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_LH_ISPHX);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_LH_IS0X);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_AXI2APB_2MB_BUS0_TP);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_AHB2APB_BUS0P);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_AXI2APB_2MB_BUS0_TD);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_PCLK_TREX_P_BUS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS0_GATE_ACLK_TREX_P_BUS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_ACLK_LH_MSCL1);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_ACLK_LH_MSCL0);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_ACLK_LH_MFC1);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_ACLK_LH_MFC0);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_ACLK_LH_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_ACLK_TREX_BUS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_PCLK_CMU_BUS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_PCLK_TREX_BUS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_PCLK_SYSREG_BUS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_PCLK_PMU_BUS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_PCLK_LH_MSCLSFRX);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_PCLK_LH_MFCP);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_PCLK_LH_FSYS0SFRX);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_PCLK_AHB2APB_BUS1P);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_PCLK_AXI2APB_2MB_BUS1_TP);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_PCLK_AXI2APB_2MB_BUS1_TD);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_PCLK_TREX_P_BUS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, BUS1_GATE_ACLK_TREX_P_BUS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_ACLK_BNS);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_ACLK_PXL_ASBS_CSIS2_int);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_ACLK_CSIS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PCLK_BNS);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_ACLK_CSIS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_ACLK_CSIS2);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_ACLK_CSIS3);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_ACLK_3AA0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PCLK_3AA0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_ACLK_3AA1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PCLK_3AA1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_ACLK_SFW110_IS_A);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_ACLK_SysMMU6_IS_A);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_ACLK_TREX_A_5x1_IS_A);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_ACLK_LH_ASYNC_SI_CAM0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PCLK_PMU_CAM0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PCLK_SYSREG_CAM0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_ACLK_LH_ASYNC_MI_CAM0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_ACLK_XIUASYNC_MI_CAM0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PCLK_CAM0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PCLK_CSIS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PCLK_CSIS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PCLK_XIUASYNC_MI_CAM0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PCLK_TREX_A_5x1_IS_A);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PCLK_SysMMU6_IS_A);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PCLK_SFW110_IS_A_IS_A);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_SCLK_PROMISE_CAM0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PHYCLK_HS0_CSIS0_RX_BYTE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PHYCLK_HS1_CSIS0_RX_BYTE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PHYCLK_HS2_CSIS0_RX_BYTE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PHYCLK_HS3_CSIS0_RX_BYTE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PHYCLK_HS0_CSIS1_RX_BYTE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PHYCLK_HS1_CSIS1_RX_BYTE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_GATE_PCLK_HPM_APBIF_CAM0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_LOCAL_GATE_ACLK_BNS);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_LOCAL_GATE_ACLK_PXL_ASBS_CSIS2_int);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_LOCAL_GATE_ACLK_CSIS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_LOCAL_GATE_PCLK_BNS);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_LOCAL_GATE_ACLK_CSIS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_LOCAL_GATE_ACLK_CSIS2);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_LOCAL_GATE_ACLK_CSIS3);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_LOCAL_GATE_ACLK_3AA0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_LOCAL_GATE_PCLK_3AA0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_LOCAL_GATE_ACLK_3AA1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_LOCAL_GATE_PCLK_3AA1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_LOCAL_GATE_PCLK_CSIS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM0_LOCAL_GATE_PCLK_CSIS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_ARM);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_ARM);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_SMMU_VRA);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_VRA);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_VRA);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_LH_SI);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_TREX_CAM1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_XIU_from_ISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_SMMU_IS_B);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_SFW);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_ASYNC_CA7_TO_DRAM);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_SMMU_ISPCPU);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_TREX_B);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_LH_MI);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_PERI);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_CSIS3);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_CSIS2);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_XIU_to_CAM0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_XIU_to_ISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_XIU_to_ISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_CMU_LOCAL);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_SYSREG_CAM1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_PMU_CAM1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_TREX_CAM1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_XIU_from_ISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_PERI);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_SMMU_ISPCPU);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_SMMU_VRA);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_SMMU_IS_B);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_SFW);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_TREX_B);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_WDT);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_UART);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_SPI1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_SPI0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_PWM);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_MCUCTL);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_I2C3);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_I2C2);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_I2C1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_I2C0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_PDMA);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_BRIDGE_PERI);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_CSIS2);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_CSIS3);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_SMMU_MC_SC);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_ACLK_MC_SC);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PCLK_SMMU_MC_SC);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_SCLK_ISP_PERI_IS_B_SPI0_EXT_CLK_ISP);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_SCLK_ISP_PERI_IS_B_SPI1_EXT_CLK_ISP);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_SCLK_ISP_PERI_IS_B_UART_EXT_CLK_ISP);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C3_ISP);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C2_ISP);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C1_ISP);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C0_ISP);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_SCLK_ISP_PERI_IS_B_PWM_ISP);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PHYCLK_HS0_CSIS2_RX_BYTE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PHYCLK_HS1_CSIS2_RX_BYTE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PHYCLK_HS2_CSIS2_RX_BYTE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PHYCLK_HS3_CSIS2_RX_BYTE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_GATE_PHYCLK_HS0_CSIS3_RX_BYTE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_ACLK_VRA);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_PCLK_VRA);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_PCLK_CSIS3);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_PCLK_CSIS2);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_PCLK_WDT);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_PCLK_UART);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_PCLK_SPI1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_PCLK_SPI0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_PCLK_PWM);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_PCLK_MCUCTL);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_PCLK_I2C3);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_PCLK_I2C2);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_PCLK_I2C1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_PCLK_I2C0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_ACLK_PDMA);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_ACLK_CSIS2);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_ACLK_CSIS3);
|
|
ADD_CLK_TO_LIST(gate_type_list, CAM1_LOCAL_GATE_ACLK_MC_SC);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_AS_SI_IRPM);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_MPACEBRIDGE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_PULSE2HS);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_DBG_LH_MI_MIF_CCORE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_SCI_PPC_WRAPPER);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_ACE_AS_MI_APL_CCORE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_MPACE_SI);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_CPACE_MI);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_ATB_SI_CCOREBDU_MNGSCS);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_BDU);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_TREX_CCORE_SCI);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_SCI);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_CLEANY_CPPERI);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_US_CPPERI);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_LH_MI_CPPERI_CCORE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_LH_SI_CCORESFRX_IMEMX);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_LH_MI_G3DXIRAM_CCORESFR);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_DS_IRPM);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_XIU_CCORESFRX);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_TREX_P_CCORE_BUS);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_TREX_CCORE_PERI);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_AS_MI_IRPM);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_TREX_CCORE_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_ACEL_LH_MI_G3DX1_CCORETD);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_ACEL_LH_MI_G3DX0_CCORETD);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_ATB_APL_MNGS);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_XIU_CPX);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_CLEANY_CPDATA);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_LH_MI_CPDATA_CCORE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_LH_MI_IMEMX_CCORETD);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_LH_MI_AUDX_CCORETD);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_AS_MI_MNGSCS_CCORETD);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_TREX_CCORE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_CMU);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_HPM_APBIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_SCI);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_GPIO_CCORE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_S_MAILBOX);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_MAILBOX);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_SYSREG_CCORE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_GPIO_APBIF_ALIVE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_SCI_PPC_WRAPPER);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_VT_MON_APB);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_PMU_CCORE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_PMU_APBIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_CMU_TOPC_APBIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_AXI2APB_CORESIGHT);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_AXI2APB_TREX_P_CCORE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_AXI2APB_TREX_CCORE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_AXI2APB_CCORE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_TREX_P_CCORE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_TREX_CCORE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_BDU);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF3P);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF2P);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF1P);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF0P);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_G3DP);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_AUDX);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_AS_SI_CCORETP_APL);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_AXI_AS_SI_CCORETP_MNGS);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_APB_AS_MI_CCORETP_MNGSCS);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_APB_AS_MI_MNGSCS_CCOREBDU);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_ACLK_TREX_P_CCORE);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_APBASYNC_BAT_AP);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_APBASYNC_BAT_CP);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_HSI2C_BAT_AP);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_HSI2C);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_HSI2C_BAT_CP);
|
|
ADD_CLK_TO_LIST(gate_type_list, CCORE_GATE_PCLK_HSI2C_CP);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_PPMU_DISP0_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_SMMU_DISP0_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_XIU_DISP0_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_LH_ASYNC_SI_R_TOP_DISP);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_VPP0_ACLK_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_PPMU_DISP0_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_SMMU_DISP0_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_XIU_DISP0_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_LH_ASYNC_SI_TOP_DISP);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_VPP0_ACLK_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_SFW_DISP0_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_SFW_DISP0_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_SMMU_DISP0_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_SMMU_DISP0_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_PPMU_DISP0_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_PPMU_DISP0_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_HDMI_PHY);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_DISP0_MUX);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_DP);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_HDMI_AUDIO);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_HDMI);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_DSIM2);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_DSIM1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_DSIM0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_SYSREG_DISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_PMU_DISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_CMU_DISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_XIU_DISP0SFRX);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_AXI2APB_DISP0_1P);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_AXI2APB_DISP0_0P);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_ACLK_AXI_LH_ASYNC_MI_DISP0SFR);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_HPM_APBIF_DISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_DECON0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_VPP0_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_VPP0_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_SFW_DISP0_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PCLK_SFW_DISP0_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_SCLK_DISP1_400);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_SCLK_DECON0_ECLK0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_SCLK_DECON0_VCLK0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_SCLK_DECON0_VCLK1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_SCLK_HDMI_AUDIO);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_SCLK_PROMISE_DISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PHYCLK_HDMIPHY_TMDS_20B_CLKO);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PHYCLK_HDMIPHY_TMDS_10B_CLKO);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PHYCLK_HDMIPHY_PIXEL_CLKO);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PHYCLK_MIPIDPHY0_BITCLKDIV8);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PHYCLK_MIPIDPHY0_RXCLKESC0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PHYCLK_MIPIDPHY1_BITCLKDIV8);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PHYCLK_MIPIDPHY1_RXCLKESC0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PHYCLK_MIPIDPHY2_BITCLKDIV8);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PHYCLK_MIPIDPHY2_RXCLKESC0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PHYCLK_DPPHY_CH3_TXD_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PHYCLK_DPPHY_CH2_TXD_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PHYCLK_DPPHY_CH1_TXD_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_PHYCLK_DPPHY_CH0_TXD_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_OSCCLK_I_MIPI_DPHY_M4S4_M_XI);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_OSCCLK_I_MIPI_DPHY_M4S0_M_XI);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_OSCCLK_I_MIPI_DPHY_M1S0_M_XI);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_OSCCLK_I_DPTX_PHY_I_REF_CLK_24M);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_GATE_OSCCLK_DP_I_CLK_24M);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_XIU_DISP1X0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_AXI_LH_ASYNC_SI_DISP1_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_PPMU_DISP1_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_SMMU_DISP1_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_VPP1_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_XIU_DISP1X1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_AXI_LH_ASYNC_SI_DISP1_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_QE_DISP1_WDMA);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_PPMU_DISP1_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_SMMU_DISP1_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_VPP1_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_SFW_DISP1_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_SFW_DISP1_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_PCLK_DECON1_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_PCLK_DECON1_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_PCLK_QE_DISP1_WDMA);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_PCLK_PPMU_DISP1_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_PCLK_PPMU_DISP1_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_PCLK_SMMU_DISP1_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_PCLK_SMMU_DISP1_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_PCLK_SYSREG_DISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_PCLK_PMU_DISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_PCLK_CMU_DISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_PCLK_VPP1_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_PCLK_VPP1_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_AXI2APB_DISP1_1X);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_AXI2APB_DISP1_0X);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_XIU_DISP1SFRX);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_ACLK_AXI_LH_ASYNC_MI_DISP1SFR);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_PCLK_HPM_APBIF_DISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_PCLK_SFW_DISP1_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_PCLK_SFW_DISP1_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_SCLK_DECON1_ECLK_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_SCLK_DECON1_ECLK_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_GATE_SCLK_PROMISE_DISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_AXI2ACEL_FSYS0X);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_PCLK_CMU_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_PCLK_GPIO_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_PCLK_SYSREG_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_PCLK_PPMU_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_PCLK_PMU_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_PCLK_ETR_USB_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_HCLK_USBHOST20);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_AXI_US_USBHS_FSYS0X);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_ETR_USB_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_UFS_LINK_EMBEDDED);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_USBDRD30);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_MMC0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_PDMAS);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_PDMA0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_PPMU_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_XIU_FSYS0SFRX);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_AXI_US_USBDRD30X_FSYS0X);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_AXI_US_PDMAX_FSYS0X);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_AXI2AHB_FSYS0H);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_AXI2AHB_USBDRD30H);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_AXI_LH_ASYNC_MI_ETR_USB_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_XIU_PDMAX);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_XIU_USBX);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_XIU_EMBEDDEDX);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_XIU_FSYS0X);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_AXI2APB_FSYS0P);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_AHB_BRIDGE_FSYS0H);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_AXI_LH_ASYNC_MI_TOP_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_ACLK_ACEL_LH_ASYNC_SI_TOP_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_PCLK_HPM_APBIF_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_SCLK_USBDRD30_SUSPEND_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_SCLK_MMC0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_SCLK_UFSUNIPRO_EMBEDDED);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_SCLK_USBDRD30_REF_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_PHYCLK_USBDRD30_UDRD30_PHYCLOCK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_PHYCLK_UFS_TX0_SYMBOL);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_PHYCLK_UFS_RX0_SYMBOL);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_PHYCLK_USBHOST20_PHYCLOCK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_SCLK_PROMISE_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_SCLK_USBHOST20PHY_REF_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_SCLK_UFSUNIPRO_EMBEDDED_CFG);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_GATE_SCLK_USBHOST20_REF_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_AXI2ACEL_FSYS1X);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PCLK_CMU_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_COMBO_PHY_PCS_PCLK_WIFI1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_COMBO_PHY_PCS_PCLK_WIFI0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PCLK_PMU_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PCLK_PPMU_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PCLK_GPIO_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PCLK_SYSREG_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_SROMC_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PCLK_PCIE_WIFI1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_PCIE_WIFI1_DBI);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_PCIE_WIFI1_SLV);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_PCIE_WIFI1_MSTR);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_AHB2AXI_PCIE_WIFI1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PCLK_PCIE_WIFI0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_PCIE_WIFI0_DBI);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_PCIE_WIFI0_SLV);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_PCIE_WIFI0_MSTR);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_AHB2AXI_PCIE_WIFI0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_PPMU_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_AHB_BRIDGE_FSYS1_S4);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_AXI2AHB_FSYS1_S4);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_AXI2APB_FSYS1_S1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_AXI2AHB_FSYS1_S0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_XIU_FSYS1SFRX);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_XIU_SDCARDX);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_XIU_FSYS1X);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_AXI_LH_ASYNC_MI_TOP_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_ACEL_LH_ASYNC_SI_TOP_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_UFS_LINK_SDCARD);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_ACLK_MMC2);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PCLK_HPM_APBIF_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PCLK_COMBO_PHY_WIFI1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PCLK_COMBO_PHY_WIFI0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_SCLK_MMC2);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_SCLK_UFSUNIPRO_SDCARD);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_SCLK_UFSUNIPRO_SDCARD_CFG);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_SCLK_PCIE_LINK_WIFI0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_SCLK_PCIE_LINK_WIFI1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PHYCLK_PCIE_WIFI0_TX0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PHYCLK_PCIE_WIFI0_RX0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PHYCLK_PCIE_WIFI1_TX0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PHYCLK_PCIE_WIFI1_RX0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PHYCLK_PCIE_WIFI0_DIG_REFCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_PHYCLK_PCIE_WIFI1_DIG_REFCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_GATE_SCLK_PROMISE_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_ACLK_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_ACLK_GRAY_DEC);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_ACLK_SFW100_ACEL_G3D1);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_ACLK_SFW100_ACEL_G3D0);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_ACLK_XIU_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_ACLK_PPMU_G3D1);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_ACLK_PPMU_G3D0);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_ACLK_ASYNCAPBM_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_ACLK_ASYNCAXI_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_ACLK_AXI_DS_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_ACLK_ACEL_LH_ASYNC_SI_G3D1);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_ACLK_ACEL_LH_ASYNC_SI_G3D0);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_PCLK_SFW100_ACEL_G3D1);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_PCLK_SFW100_ACEL_G3D0);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_PCLK_HPM_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_PCLK_PPMU_G3D1);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_PCLK_PPMU_G3D0);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_PCLK_PMU_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_ACLK_ASYNCAPBS_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_PCLK_SYSREG_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_ACLK_AXI2APB_G3DP);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_ACLK_AXI_LH_ASYNC_MI_G3DP);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_SCLK_HPM2_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_SCLK_HPM1_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_SCLK_HPM0_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_SCLK_AXI_LH_ASYNC_SI_G3DIRAM);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_SCLK_ASYNCAXI_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_MC);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_XIU_3X1_SSS);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_AXI_US_APM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_ASYNCAHBMSTM_APM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_ASYNCAHBM_SSS_ATLAS);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_LH_ASYNC_SI_IMEM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_PPMU_SSSX);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_XIU_IMEMX);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_SSS);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_RTIC);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_PCLK_CMU_IMEM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_PCLK_SYSREG_IMEM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_PCLK_MC);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_PCLK_PPMU_SSSX);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_PCLK_PMU_IMEM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_ASYNCAHBSS_APM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_AXI2AHB_APM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_INT_MEM_ALV);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_INT_MEM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_AXIDS_PIMEMX_IMEM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_AXILHASYNCM_PIMEMX);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_AXI2APB_IMEM_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_AXI2APB_IMEM_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_XIU_PIMEMX1);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_XIU_PIMEMX0);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_GIC);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_PCLK_SSS);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_PCLK_RTIC);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_ASYNCAHBSM_APM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_AHB2AXI_APM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_ASYNCAHBMSTS_APM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_CM3_APM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_AHB_BUSMATRIX_APM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_SCLK_CM3_APM);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_GATE_ACLK_APM);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_ACLK_FIMC_ISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_PCLK_FIMC_ISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_ACLK_FIMC_TPU);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_PCLK_FIMC_TPU);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_ACLK_SysMMU601);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_CLK_C_TREX_C);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_CLK_AXI_LH_ASYNC_SI_TOP_ISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_PCLK_SYSREG_ISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_PCLK_PMU_ISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_ACLK_XIU_N_ASYNC_MI);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_PCLK_ISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_PCLK_HPM_APBIF_ISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_PCLK_SysMMU601);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_PCLK_TREX_C);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_SCLK_PROMISE_ISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_GATE_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_LOCAL_GATE_ACLK_FIMC_ISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_LOCAL_GATE_PCLK_FIMC_ISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_LOCAL_GATE_ACLK_FIMC_TPU);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_LOCAL_GATE_PCLK_FIMC_TPU);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_LOCAL_GATE_CLK_C_TREX_C);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP0_LOCAL_GATE_PCLK_TREX_C);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP1_GATE_ACLK_XIU_N_ASYNC_SI);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP1_GATE_ACLK_FIMC_ISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP1_GATE_PCLK_SYSREG_ISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP1_GATE_PCLK_PMU_ISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP1_GATE_ACLK_AXI2APB_BRIDGE_IS2P);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP1_GATE_ACLK_XIU_N_ASYNC_MI);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP1_GATE_PCLK_FIMC_ISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP1_GATE_PCLK_HPM_APBIF_ISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP1_GATE_SCLK_PROMISE_ISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP1_LOCAL_GATE_ACLK_FIMC_ISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP1_LOCAL_GATE_PCLK_FIMC_ISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_ACLK_ASYNCAPB_MFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_ACLK_SMMU_MFC_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_ACLK_SMMU_MFC_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_ACLK_MFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_ACLK_PPMU_MFC_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_ACLK_PPMU_MFC_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_ACLK_LH_S_MFC_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_ACLK_LH_S_MFC_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_ACLK_SFW_MFC_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_ACLK_SFW_MFC_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_PCLK_SYSREG_MFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_PCLK_SMMU_MFC_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_PCLK_SMMU_MFC_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_PCLK_PPMU_MFC_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_PCLK_PPMU_MFC_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_PCLK_PMU_MFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_PCLK_CMU_MFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_PCLK_ASYNCAPB_MFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_ACLK_AXI2APB_MFCSFR);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_ACLK_LH_M_MFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_PCLK_HPM_APBIF_MFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_PCLK_SFW_MFC_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_PCLK_SFW_MFC_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_GATE_SCLK_PROMISE_MFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_ACLK_APSCDC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_ACLK_PPC_DEBUG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_ACLK_PPC_DVFS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_ACLK_SMC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_PCLK_SMC1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_PCLK_DMC_MISC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_PCLK_PPC_DEBUG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_PCLK_PPC_DVFS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_PCLK_SYSREG_MIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_PCLK_HPM);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_ACLK_AXI_ASYNC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_PCLK_MIFP);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_PCLK_PMU_MIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_PCLK_LPDDR4PHY);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_PCLK_SMC2);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_SCLK_PROMISE);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF0_GATE_RCLK_DREX);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_ACLK_APSCDC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_ACLK_PPC_DEBUG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_ACLK_PPC_DVFS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_ACLK_SMC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_PCLK_SMC1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_PCLK_DMC_MISC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_PCLK_PPC_DEBUG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_PCLK_PPC_DVFS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_PCLK_SYSREG_MIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_PCLK_HPM);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_ACLK_AXI_ASYNC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_PCLK_MIFP);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_PCLK_PMU_MIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_PCLK_LPDDR4PHY);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_PCLK_SMC2);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_SCLK_PROMISE);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF1_GATE_RCLK_DREX);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_ACLK_APSCDC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_ACLK_PPC_DEBUG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_ACLK_PPC_DVFS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_ACLK_SMC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_PCLK_SMC1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_PCLK_DMC_MISC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_PCLK_PPC_DEBUG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_PCLK_PPC_DVFS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_PCLK_SYSREG_MIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_PCLK_HPM);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_ACLK_AXI_ASYNC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_PCLK_MIFP);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_PCLK_PMU_MIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_PCLK_LPDDR4PHY);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_PCLK_SMC2);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_SCLK_PROMISE);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF2_GATE_RCLK_DREX);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_ACLK_APSCDC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_ACLK_PPC_DEBUG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_ACLK_PPC_DVFS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_ACLK_SMC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_PCLK_SMC1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_PCLK_DMC_MISC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_PCLK_PPC_DEBUG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_PCLK_PPC_DVFS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_PCLK_SYSREG_MIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_PCLK_HPM);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_ACLK_AXI_ASYNC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_PCLK_MIFP);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_PCLK_PMU_MIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_PCLK_LPDDR4PHY);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_PCLK_SMC2);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_SCLK_PROMISE);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF3_GATE_RCLK_DREX);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ACLK_ASYNCPACES_MNGS_SCI);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLKS_ATB_MNGS3_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLKS_ATB_MNGS2_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLKS_ATB_MNGS1_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLKS_ATB_MNGS0_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_XIU_MNGSX_2x1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_STM_TXACTOR);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_ATB_BDU_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_ATB_AUD_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_ATB_CAM1_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_ATB_APOLLO3_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_ATB_APOLLO2_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_ATB_APOLLO1_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_ATB_APOLLO0_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLKM_ATB_MNGS3_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLKM_ATB_MNGS2_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLKM_ATB_MNGS1_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLKM_ATB_MNGS0_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_ASYNCAHB_CSSYS_SSS_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_ASYNCLHAXI_CSSYS_ETR_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_CSSYS_HCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_CSSYS_TRACECLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_ASYNCATB_CAM1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_ATCLK_ASYNCATB_AUD);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLKDBG_ASAPBMST_CCORE_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_BDU);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_CAM1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_AUD);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_APOLLO);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLKDBG_DUMP_PC_MNGS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLKDBG_SECJTAG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLKDBG_AXIAP);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLKDBG_CSSYS_CTMCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLKDBG_CSSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLKDBG_MNGS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLKDBG_ASYNCDAPSLV);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLK_SYSREG_MNGS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLK_STM_TXACTOR);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLK_XIU_PERI_MNGS_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLK_PMU_MNGS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLK_XIU_MNGSSFRX_1x2);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLK_AXI2APB_MNGS_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_PCLK_HPM_MNGS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_SCLK_MNGS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_SCLK_PROMISE2_MNGS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_SCLK_PROMISE1_MNGS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MNGS_GATE_SCLK_PROMISE0_MNGS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_ASYNCAPB_JPEG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_PPMU_MSCL_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_SMMU_JPEG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_SMMU_MSCL_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_QE_JPEG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_QE_MSCL_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_XIU_MSCLX_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_LH_ASYNC_SI_MSCL_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_JPEG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_MSCL_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_SFW_MSCL_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_ASYNCAPB_G2D);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_PPMU_MSCL_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_SMMU_G2D);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_SMMU_MSCL_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_QE_G2D);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_QE_MSCL_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_AXI2ACEL);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_XIU_MSCLX_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_LH_ASYNC_SI_MSCL_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_G2D);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_MSCL_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_SFW_MSCL_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_LH_ASYNC_MI_MSCLSFR);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_PMU_MSCL);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_SYSREG_MSCL);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_CMU_MSCL);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_PPMU_MSCL_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_PPMU_MSCL_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_SMMU_G2D);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_SMMU_JPEG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_SMMU_MSCL_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_SMMU_MSCL_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_QE_G2D);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_QE_JPEG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_QE_MSCL_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_QE_MSCL_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_ASYNCAPB_G2D);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_ASYNCAPB_JPEG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_MSCL_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_MSCL_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_AXI2APB_MSCLSFR_1P);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_AXI2APB_MSCLSFR_0P);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_ACLK_XIU_MSCLSFRX);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_SFW_MSCL_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MSCL_GATE_PCLK_SFW_MSCL_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_PCLK_HSI2C11);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_PCLK_HSI2C10);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_PCLK_HSI2C9);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_PCLK_HSI2C5);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_PCLK_HSI2C4);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_PCLK_HSI2C1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_PCLK_HSI2C0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_PCLK_PWM);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_PCLK_ADCIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_PCLK_UART0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_PCLK_GPIO_BUS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_PCLK_SYSREG_PERIC0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_PCLK_PMU_PERIC0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_PCLK_CMU_PERIC0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_ACLK_AXI2APB_PERIC0P);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_ACLK_AXILHASYNCM_PERIC0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_SCLK_UART0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_GATE_SCLK_PWM);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_SPI7);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_SPI6);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_SPI5);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_SPI4);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_SPI3);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_SPI2);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_SPI1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_SPI0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_UART5);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_UART4);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_UART3);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_UART2);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_UART1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_GPIO_ESE);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_GPIO_FF);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_GPIO_TOUCH);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_GPIO_NFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_GPIO_PERIC1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_SYSREG_PERIC1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_PMU_PERIC1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_CMU_PERIC1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_ACLK_AXI2APB_PERIC1_2P);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_ACLK_AXI2APB_PERIC1_1P);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_ACLK_AXI2APB_PERIC1_0P);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_ACLK_XIU_PERIC1SFRX);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_ACLK_AXILHASYNCM_PERIC1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_HSI2C14);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_HSI2C13);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_HSI2C12);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_HSI2C8);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_HSI2C7);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_HSI2C6);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_HSI2C3);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_PCLK_HSI2C2);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_SCLK_SPI0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_SCLK_SPI1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_SCLK_SPI2);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_SCLK_SPI3);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_SCLK_SPI4);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_SCLK_SPI5);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_SCLK_SPI6);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_SCLK_SPI7);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_SCLK_UART1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_SCLK_UART2);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_SCLK_UART3);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_SCLK_UART4);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_GATE_SCLK_UART5);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_SFR_APBIF_HDMI_CEC);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_SFR_APBIF_TMU);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_RTC_APBIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_MONOCNT_APBIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_WDT_APOLLO);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_WDT_MNGS);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_MCT);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_SYSREG_PERIS);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_PMU_PERIS);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_CMU_PERIS);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_ACLK_AXI2APB_PERIS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_ACLK_AXI2APB_PERIS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_ACLK_XIU_PERIS);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_ACLK_AXI_LH_ASYNC);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_HPM_APBIF_PERIS);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_15);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_14);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_13);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_12);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_11);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_10);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_9);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_8);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_7);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_6);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_5);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_4);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_3);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_2);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TZPC_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_TOP_RTC);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_PCLK_SFR_APBIF_CHIPID);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_SCLK_OTP_CON_TOP);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_SCLK_CHIPID);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_SCLK_TMU);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_GATE_SCLK_PROMISE_PERIS);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CCORE_800);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CCORE_264);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CCORE_G3D_800);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CCORE_528);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CCORE_132);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_PCLK_CCORE_66);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_BUS0_528);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_BUS0_200);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_PCLK_BUS0_132);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_BUS1_528);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_PCLK_BUS1_132);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_DISP0_0_400);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_DISP0_1_400);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_DISP1_0_400);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_DISP1_1_400);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_MFC_600);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_MSCL0_528);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_MSCL1_528);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_IMEM_266);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_IMEM_200);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_IMEM_100);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_FSYS0_200);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_FSYS1_200);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_PERIS_66);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_PERIC0_66);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_PERIC1_66);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_ISP0_ISP0_528);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_ISP0_TPU_400);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_ISP0_TREX_528);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_ISP1_ISP1_468);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CAM0_CSIS0_414);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CAM0_CSIS1_168);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CAM0_CSIS2_234);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CAM0_3AA0_414);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CAM0_3AA1_414);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CAM0_CSIS3_132);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CAM0_TREX_528);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CAM1_ARM_672);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CAM1_TREX_VRA_528);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CAM1_TREX_B_528);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CAM1_BUS_264);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CAM1_PERI_84);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CAM1_CSIS2_414);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CAM1_CSIS3_132);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_CAM1_SCL_566);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_DISP0_DECON0_ECLK0);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_DISP0_DECON0_VCLK0);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_DISP0_DECON0_VCLK1);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_DISP0_HDMI_AUDIO);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_DISP1_DECON1_ECLK0);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_DISP1_DECON1_ECLK1);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_FSYS0_USBDRD30);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_FSYS0_MMC0);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_FSYS0_UFSUNIPRO20);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_FSYS0_PHY_24M);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_FSYS0_UFSUNIPRO_CFG);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_FSYS1_MMC2);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_FSYS1_UFSUNIPRO20);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_FSYS1_PCIE_PHY);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_FSYS1_UFSUNIPRO_CFG);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PERIC0_UART0);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PERIC1_SPI0);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PERIC1_SPI1);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PERIC1_SPI2);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PERIC1_SPI3);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PERIC1_SPI4);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PERIC1_SPI5);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PERIC1_SPI6);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PERIC1_SPI7);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PERIC1_UART1);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PERIC1_UART2);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PERIC1_UART3);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PERIC1_UART4);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PERIC1_UART5);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_CAM1_ISP_SPI0);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_CAM1_ISP_SPI1);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_CAM1_ISP_UART);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_AP2CP_MIF_PLL_OUT);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_ACLK_PSCDC_400);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_BUS_PLL_MNGS);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_BUS_PLL_APOLLO);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_BUS_PLL_MIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_BUS_PLL_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_ISP_SENSOR0);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_ISP_SENSOR1);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_ISP_SENSOR2);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_ISP_SENSOR3);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PROMISE_INT);
|
|
ADD_CLK_TO_LIST(gate_type_list, TOP_GATE_SCLK_PROMISE_DISP);
|
|
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_DSIM0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_DSIM1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_DSIM2);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_HDMI);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_HDMI_AUDIO);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_DP);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_DISP0_MUX);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_HDMI_PHY);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_DISP1_400);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_DECON0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_HPM_APBIF_DISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_PROMISE_DISP0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_DPTX_PHY);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_MIPI_DPHY_M1S0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_MIPI_DPHY_M4S0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP0_HWACG_MIPI_DPHY_M4S4);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_HWACG_DECON1_ECLK_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_HWACG_DECON1_ECLK_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_HWACG_HPM_APBIF_DISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISP1_HWACG_PROMISE_DISP1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_HWACG_USBDRD30);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_HWACG_UFS_LINK_EMBEDDED);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_HWACG_USBHOST20);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_HWACG_USBHOST20_PHY);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_HWACG_GPIO_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_HWACG_HPM_APBIF_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS0_HWACG_PROMISE_FSYS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_HWACG_SROMC_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_HWACG_GPIO_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_HWACG_HPM_APBIF_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_HWACG_PROMISE_FSYS1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_HWACG_PCIE_RC_LINK_WIFI0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_HWACG_PCIE_RC_LINK_WIFI1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_HWACG_PCIE_PCS_WIFI0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_HWACG_PCIE_PCS_WIFI1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_HWACG_PCIE_PHY_FSYS1_WIFI0);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_HWACG_PCIE_PHY_FSYS1_WIFI1);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS1_HWACG_UFS_LINK_SDCARD);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_HWACG_GIC);
|
|
ADD_CLK_TO_LIST(gate_type_list, IMEM_HWACG_ASYNCAHBM_SSS_ATLAS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_HWACG_HPM_APBIF_MFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFC_HWACG_PROMISE_MFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_HWACG_GPIO_BUS0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_HWACG_UART0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_HWACG_ADCIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_HWACG_PWM);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_HWACG_HSI2C0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_HWACG_HSI2C1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_HWACG_HSI2C4);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_HWACG_HSI2C5);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_HWACG_HSI2C9);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_HWACG_HSI2C10);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC0_HWACG_HSI2C11);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_GPIO_PERIC1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_GPIO_NFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_GPIO_TOUCH);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_GPIO_FF);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_GPIO_ESE);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_UART1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_UART2);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_UART3);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_UART4);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_UART5);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_SPI0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_SPI1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_SPI2);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_SPI3);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_SPI4);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_SPI5);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_SPI6);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_SPI7);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_HSI2C2);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_HSI2C3);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_HSI2C6);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_HSI2C7);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_HSI2C8);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_HSI2C12);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_HSI2C13);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIC1_HWACG_HSI2C14);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_MCT);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_WDT_MNGS);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_WDT_APOLLO);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_RTC_APBIF);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_SFR_APBIF_TMU);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_SFR_APBIF_HDMI_CEC);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_HPM_APBIF_PERIS);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_2);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_3);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_4);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_5);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_6);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_7);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_8);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_9);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_10);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_11);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_12);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_13);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_14);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TZPC_15);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TOP_RTC);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_OTP_CON_TOP);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_SFR_APBIF_CHIPID);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_TMU);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_CHIPID);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERIS_HWACG_PROMISE_PERIS);
|
|
ADD_CLK_TO_LIST(gate_type_list, CLKOUT_OSCCLK_NFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, CLKOUT_TCXO_26M);
|
|
ADD_CLK_TO_LIST(gate_type_list, CLKOUT_TCXO_IN0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CLKOUT_TCXO_IN1);
|
|
ADD_CLK_TO_LIST(gate_type_list, CLKOUT_TCXO_IN2);
|
|
ADD_CLK_TO_LIST(gate_type_list, CLKOUT_TCXO_IN3);
|
|
ADD_CLK_TO_LIST(gate_type_list, CLKOUT_TCXO_IN4);
|
|
ADD_CLK_TO_LIST(gate_type_list, CLKOUT_CLKOUT0_DISABLE);
|
|
|
|
clk_pll_set_rate_table(&clk_MNGS_PLL);
|
|
clk_pll_set_rate_table(&clk_APOLLO_PLL);
|
|
clk_pll_set_rate_table(&clk_G3D_PLL);
|
|
clk_pll_set_rate_table(&clk_MIF_PLL);
|
|
clk_pll_set_rate_table(&clk_BUS0_PLL);
|
|
clk_pll_set_rate_table(&clk_BUS1_PLL);
|
|
clk_pll_set_rate_table(&clk_BUS2_PLL);
|
|
clk_pll_set_rate_table(&clk_BUS3_PLL);
|
|
clk_pll_set_rate_table(&clk_MFC_PLL);
|
|
clk_pll_set_rate_table(&clk_ISP_PLL);
|
|
clk_pll_set_rate_table(&clk_DISP_PLL);
|
|
clk_pll_set_rate_table(&clk_AUD_PLL);
|
|
}
|