mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-01 08:38:52 +01:00
3281 lines
110 KiB
C
3281 lines
110 KiB
C
#ifndef __EXYNOS8890_CMU_H__
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#define __EXYNOS8890_CMU_H__
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#include "../pwrcal-clk.h"
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enum clk_id {
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OSCCLK = fixed_rate_type,
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OSCCLK_26M,
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SCAN_CLK_OSC,
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I_CP2AP_MIF_CLK,
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OSCCLK_PHY,
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SCLK_CP2AP_AUD_CLK,
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IOCLK_AUDIOCDCLK0,
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IOCLK_SLIMBUS_CLK,
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IOCLK_I2S_BCLK,
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RTC_CLKIN,
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IOCLK_SPI0,
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IOCLK_SPI1,
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IOCLK_SPI2,
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IOCLK_SPI3,
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IOCLK_SPI4,
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IOCLK_SPI5,
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IOCLK_SPI6,
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IOCLK_SPI7,
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PHYCLK_USB30_12MOHCI,
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PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
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PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
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PHYCLK_UFS_TX0_SYMBOL_PHY,
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PHYCLK_UFS_RX0_SYMBOL_PHY,
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PHYCLK_UFS_RX_PWM_CLK_PHY,
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PHYCLK_UFS_TX_PWM_CLK_PHY,
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PHYCLK_UFS_REFCLK_OUT_SOC_PHY,
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PHYCLK_USBHOST20_PHYCLOCK_PHY,
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PHYCLK_USBHOST20_FREECLK_PHY,
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PHYCLK_USBHOST20_CLK48MOHCI_PHY,
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PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_PHY,
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PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_PHY,
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PHYCLK_UFS_LINK_SDCARD_TX1_SYMBOL_PHY,
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PHYCLK_UFS_LINK_SDCARD_RX1_SYMBOL_PHY,
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PHYCLK_UFS_LINK_SDCARD_RX_PWM_CLK_PHY,
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PHYCLK_UFS_LINK_SDCARD_TX_PWM_CLK_PHY,
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PHYCLK_UFS_LINK_SDCARD_REFCLK_OUT_SOC_PHY,
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PHYCLK_PCIE_WIFI0_TX0_PHY,
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PHYCLK_PCIE_WIFI0_RX0_PHY,
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PHYCLK_PCIE_WIFI1_TX0_PHY,
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PHYCLK_PCIE_WIFI1_RX0_PHY,
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PHYCLK_PCIE_WIFI0_DIG_REFCLK_PHY,
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PHYCLK_PCIE_WIFI1_DIG_REFCLK_PHY,
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PHYCLK_MIPIDPHY0_BITCLKDIV2_PHY,
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PHYCLK_MIPIDPHY1_BITCLKDIV2_PHY,
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PHYCLK_MIPIDPHY2_BITCLKDIV2_PHY,
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PHYCLK_HDMIPHY_PIXEL_CLKO_PHY,
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PHYCLK_HDMIPHY_TMDS_CLKO_PHY,
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PHYCLK_MIPIDPHY0_RXCLKESC0_PHY,
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PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY,
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PHYCLK_MIPIDPHY1_RXCLKESC0_PHY,
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PHYCLK_MIPIDPHY1_BITCLKDIV8_PHY,
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PHYCLK_MIPIDPHY2_RXCLKESC0_PHY,
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PHYCLK_MIPIDPHY2_BITCLKDIV8_PHY,
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PHYCLK_DPPHY_CH0_TXD_CLK_PHY,
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PHYCLK_DPPHY_CH1_TXD_CLK_PHY,
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PHYCLK_DPPHY_CH2_TXD_CLK_PHY,
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PHYCLK_DPPHY_CH3_TXD_CLK_PHY,
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PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_PHY,
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PHYCLK_RXBYTECLKHS0_CSIS0,
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PHYCLK_RXBYTECLKHS1_CSIS0,
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PHYCLK_RXBYTECLKHS2_CSIS0,
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PHYCLK_RXBYTECLKHS3_CSIS0,
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PHYCLK_RXBYTECLKHS0_CSIS1,
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PHYCLK_RXBYTECLKHS1_CSIS1,
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PHYCLK_RXBYTECLKHS0_CSIS2,
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PHYCLK_RXBYTECLKHS1_CSIS2,
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PHYCLK_RXBYTECLKHS2_CSIS2,
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PHYCLK_RXBYTECLKHS3_CSIS2,
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PHYCLK_RXBYTECLKHS0_CSIS3,
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NUM_OF_FIXED_RATE_TYPE = PHYCLK_RXBYTECLKHS0_CSIS3 - fixed_rate_type + 1,
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TOP_FF_BUS0_PLL_DIV2 = fixed_factor_type,
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TOP_FF_BUS1_PLL_DIV2,
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TOP_FF_BUS2_PLL_DIV2,
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TOP_FF_BUS3_PLL_DIV2,
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TOP_FF_BUS3_PLL_DIV4,
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TOP_FF_MFC_PLL_DIV2,
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TOP_FF_ISP_PLL_DIV2,
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MIF0_FF_ACLK_MIF_PLL_DIV2,
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MIF0_FF_ACLK_MIF_PLL_DIV4,
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MIF1_FF_ACLK_MIF_PLL_DIV2,
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MIF1_FF_ACLK_MIF_PLL_DIV4,
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MIF2_FF_ACLK_MIF_PLL_DIV2,
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MIF2_FF_ACLK_MIF_PLL_DIV4,
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MIF3_FF_ACLK_MIF_PLL_DIV2,
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MIF3_FF_ACLK_MIF_PLL_DIV4,
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U_DFI_CLK_GEN_MIF0,
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U_DFI_CLK_GEN_MIF1,
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U_DFI_CLK_GEN_MIF2,
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U_DFI_CLK_GEN_MIF3,
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NUM_OF_FIXED_FACTOR_TYPE = U_DFI_CLK_GEN_MIF3 - fixed_factor_type + 1,
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MNGS_PLL = pll_type,
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APOLLO_PLL,
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G3D_PLL,
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MIF_PLL,
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BUS0_PLL,
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BUS1_PLL,
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BUS2_PLL,
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BUS3_PLL,
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MFC_PLL,
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ISP_PLL,
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DISP_PLL,
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AUD_PLL,
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PCIE_PLL,
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NUM_OF_PLL_TYPE = PCIE_PLL - pll_type + 1,
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APOLLO_MUX_APOLLO_PLL = mux_type,
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APOLLO_MUX_BUS_PLL_APOLLO_USER,
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APOLLO_MUX_APOLLO,
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AUD_MUX_AUD_PLL_USER,
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AUD_MUX_SCLK_I2S,
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AUD_MUX_SCLK_PCM,
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AUD_MUX_CP2AP_AUD_CLK_USER,
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AUD_MUX_ACLK_CA5,
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AUD_MUX_CDCLK_AUD,
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BUS0_MUX_ACLK_BUS0_528_USER,
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BUS0_MUX_ACLK_BUS0_200_USER,
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BUS0_MUX_PCLK_BUS0_132_USER,
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BUS1_MUX_ACLK_BUS1_528_USER,
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BUS1_MUX_PCLK_BUS1_132_USER,
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CAM0_MUX_ACLK_CAM0_CSIS0_414_USER,
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CAM0_MUX_ACLK_CAM0_CSIS1_168_USER,
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CAM0_MUX_ACLK_CAM0_CSIS2_234_USER,
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CAM0_MUX_ACLK_CAM0_CSIS3_132_USER,
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CAM0_MUX_ACLK_CAM0_3AA0_414_USER,
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CAM0_MUX_ACLK_CAM0_3AA1_414_USER,
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CAM0_MUX_ACLK_CAM0_TREX_528_USER,
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CAM1_MUX_ACLK_CAM1_ARM_672_USER,
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CAM1_MUX_ACLK_CAM1_TREX_VRA_528_USER,
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CAM1_MUX_ACLK_CAM1_TREX_B_528_USER,
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CAM1_MUX_ACLK_CAM1_BUS_264_USER,
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CAM1_MUX_ACLK_CAM1_PERI_84_USER,
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CAM1_MUX_ACLK_CAM1_CSIS2_414_USER,
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CAM1_MUX_ACLK_CAM1_CSIS3_132_USER,
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CAM1_MUX_ACLK_CAM1_SCL_566_USER,
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CAM1_MUX_SCLK_CAM1_ISP_SPI0_USER,
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CAM1_MUX_SCLK_CAM1_ISP_SPI1_USER,
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CAM1_MUX_SCLK_CAM1_ISP_UART_USER,
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CCORE_MUX_ACLK_CCORE_800_USER,
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CCORE_MUX_ACLK_CCORE_264_USER,
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CCORE_MUX_ACLK_CCORE_G3D_800_USER,
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CCORE_MUX_ACLK_CCORE_528_USER,
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CCORE_MUX_ACLK_CCORE_132_USER,
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CCORE_MUX_PCLK_CCORE_66_USER,
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DISP0_MUX_DISP_PLL,
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DISP0_MUX_ACLK_DISP0_0_400_USER,
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DISP0_MUX_ACLK_DISP0_1_400_USER,
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DISP0_MUX_SCLK_DISP0_DECON0_ECLK0_USER,
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DISP0_MUX_SCLK_DISP0_DECON0_VCLK0_USER,
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DISP0_MUX_SCLK_DISP0_DECON0_VCLK1_USER,
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DISP0_MUX_ACLK_DISP0_1_400,
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DISP0_MUX_SCLK_DISP0_DECON0_ECLK0,
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DISP0_MUX_SCLK_DISP0_DECON0_VCLK0,
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DISP0_MUX_SCLK_DISP0_DECON0_VCLK1,
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DISP0_MUX_SCLK_DISP0_HDMI_AUDIO,
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DISP1_MUX_ACLK_DISP1_0_400_USER,
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DISP1_MUX_ACLK_DISP1_1_400_USER,
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DISP1_MUX_SCLK_DISP1_DECON1_ECLK0_USER,
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DISP1_MUX_SCLK_DISP1_DECON1_ECLK1_USER,
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DISP1_MUX_SCLK_DISP1_600_USER,
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DISP1_MUX_ACLK_DISP1_1_400,
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DISP1_MUX_SCLK_DISP1_DECON1_ECLK0,
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DISP1_MUX_SCLK_DISP1_DECON1_ECLK1,
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DISP1_MUX_SCLK_DECON1_ECLK1,
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FSYS0_MUX_ACLK_FSYS0_200_USER,
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FSYS0_MUX_SCLK_FSYS0_USBDRD30_USER,
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FSYS0_MUX_SCLK_FSYS0_MMC0_USER,
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FSYS0_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_USER,
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FSYS0_MUX_SCLK_FSYS0_24M_USER,
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FSYS0_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_CFG_USER,
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FSYS1_MUX_ACLK_FSYS1_200_USER,
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FSYS1_MUX_SCLK_FSYS1_MMC2_USER,
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FSYS1_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_USER,
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FSYS1_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_CFG_USER,
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FSYS1_MUX_SCLK_FSYS1_PCIE_PHY_USER,
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FSYS1_MUX_PCIE_PLL,
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G3D_MUX_G3D_PLL_USER,
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G3D_MUX_BUS_PLL_USER,
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G3D_MUX_G3D,
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IMEM_MUX_ACLK_IMEM_266_USER,
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IMEM_MUX_ACLK_IMEM_200_USER,
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IMEM_MUX_ACLK_IMEM_100_USER,
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ISP0_MUX_ACLK_ISP0_528_USER,
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ISP0_MUX_ACLK_ISP0_TPU_400_USER,
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ISP0_MUX_ACLK_ISP0_TREX_528_USER,
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ISP0_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_USER,
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ISP1_MUX_ACLK_ISP1_468_USER,
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MFC_MUX_ACLK_MFC_600_USER,
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MIF0_MUX_MIF_PLL,
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MIF0_MUX_BUS_PLL_USER,
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MIF0_MUX_ACLK_MIF_PLL,
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MIF0_MUX_PCLK_MIF,
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MIF0_MUX_SCLK_HPM_MIF,
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MIF1_MUX_MIF_PLL,
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MIF1_MUX_BUS_PLL_USER,
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MIF1_MUX_ACLK_MIF_PLL,
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MIF1_MUX_PCLK_MIF,
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MIF1_MUX_SCLK_HPM_MIF,
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MIF2_MUX_MIF_PLL,
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MIF2_MUX_BUS_PLL_USER,
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MIF2_MUX_ACLK_MIF_PLL,
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MIF2_MUX_PCLK_MIF,
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MIF2_MUX_SCLK_HPM_MIF,
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MIF3_MUX_MIF_PLL,
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MIF3_MUX_BUS_PLL_USER,
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MIF3_MUX_ACLK_MIF_PLL,
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MIF3_MUX_PCLK_MIF,
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MIF3_MUX_SCLK_HPM_MIF,
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MIF0_MUX_PCLK_SMC,
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MIF1_MUX_PCLK_SMC,
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MIF2_MUX_PCLK_SMC,
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MIF3_MUX_PCLK_SMC,
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MNGS_MUX_MNGS_PLL,
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MNGS_MUX_BUS_PLL_MNGS_USER,
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MNGS_MUX_MNGS,
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MSCL_MUX_ACLK_MSCL0_528_USER,
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MSCL_MUX_ACLK_MSCL1_528_USER,
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MSCL_MUX_ACLK_MSCL1_528,
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PERIC0_MUX_ACLK_PERIC0_66_USER,
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PERIC0_MUX_SCLK_UART0_USER,
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PERIC1_MUX_ACLK_PERIC1_66_USER,
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PERIC1_MUX_SCLK_SPI0_USER,
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PERIC1_MUX_SCLK_SPI1_USER,
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PERIC1_MUX_SCLK_SPI2_USER,
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PERIC1_MUX_SCLK_SPI3_USER,
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PERIC1_MUX_SCLK_SPI4_USER,
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PERIC1_MUX_SCLK_SPI5_USER,
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PERIC1_MUX_SCLK_SPI6_USER,
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PERIC1_MUX_SCLK_SPI7_USER,
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PERIC1_MUX_SCLK_UART1_USER,
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PERIC1_MUX_SCLK_UART2_USER,
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PERIC1_MUX_SCLK_UART3_USER,
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PERIC1_MUX_SCLK_UART4_USER,
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PERIC1_MUX_SCLK_UART5_USER,
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PERIS_MUX_ACLK_PERIS_66_USER,
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TOP_MUX_BUS0_PLL,
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TOP_MUX_BUS1_PLL,
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TOP_MUX_BUS2_PLL,
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TOP_MUX_BUS3_PLL,
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TOP_MUX_MFC_PLL,
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TOP_MUX_ISP_PLL,
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TOP_MUX_AUD_PLL,
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TOP_MUX_G3D_PLL,
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TOP_MUX_SCLK_BUS0_PLL,
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TOP_MUX_SCLK_BUS1_PLL,
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TOP_MUX_SCLK_BUS2_PLL,
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TOP_MUX_SCLK_BUS3_PLL,
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TOP_MUX_SCLK_MFC_PLL,
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TOP_MUX_SCLK_ISP_PLL,
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TOP_MUX_ACLK_CCORE_800,
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TOP_MUX_ACLK_CCORE_264,
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TOP_MUX_ACLK_CCORE_G3D_800,
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TOP_MUX_ACLK_CCORE_528,
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TOP_MUX_ACLK_CCORE_132,
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TOP_MUX_PCLK_CCORE_66,
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TOP_MUX_ACLK_BUS0_528,
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TOP_MUX_ACLK_BUS0_200,
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TOP_MUX_PCLK_BUS0_132,
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TOP_MUX_ACLK_BUS1_528,
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TOP_MUX_PCLK_BUS1_132,
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TOP_MUX_ACLK_DISP0_0_400,
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TOP_MUX_ACLK_DISP0_1_400,
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TOP_MUX_ACLK_DISP1_0_400,
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TOP_MUX_ACLK_DISP1_1_400,
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TOP_MUX_ACLK_MFC_600,
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TOP_MUX_ACLK_MSCL0_528,
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TOP_MUX_ACLK_MSCL1_528,
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TOP_MUX_ACLK_IMEM_266,
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TOP_MUX_ACLK_IMEM_200,
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TOP_MUX_ACLK_IMEM_100,
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TOP_MUX_ACLK_FSYS0_200,
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TOP_MUX_ACLK_FSYS1_200,
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TOP_MUX_ACLK_PERIS_66,
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TOP_MUX_ACLK_PERIC0_66,
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TOP_MUX_ACLK_PERIC1_66,
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TOP_MUX_ACLK_ISP0_ISP0_528,
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TOP_MUX_ACLK_ISP0_TPU_400,
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TOP_MUX_ACLK_ISP0_TREX_528,
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TOP_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D,
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TOP_MUX_ACLK_ISP1_ISP1_468,
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TOP_MUX_ACLK_CAM0_CSIS0_414,
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TOP_MUX_ACLK_CAM0_CSIS1_168,
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TOP_MUX_ACLK_CAM0_CSIS2_234,
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TOP_MUX_ACLK_CAM0_3AA0_414,
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TOP_MUX_ACLK_CAM0_3AA1_414,
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TOP_MUX_ACLK_CAM0_CSIS3_132,
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TOP_MUX_ACLK_CAM0_TREX_528,
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TOP_MUX_ACLK_CAM1_ARM_672,
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TOP_MUX_ACLK_CAM1_TREX_VRA_528,
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TOP_MUX_ACLK_CAM1_TREX_B_528,
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TOP_MUX_ACLK_CAM1_BUS_264,
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TOP_MUX_ACLK_CAM1_PERI_84,
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TOP_MUX_ACLK_CAM1_CSIS2_414,
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TOP_MUX_ACLK_CAM1_CSIS3_132,
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TOP_MUX_ACLK_CAM1_SCL_566,
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TOP_MUX_SCLK_DISP0_DECON0_ECLK0,
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TOP_MUX_SCLK_DISP0_DECON0_VCLK0,
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TOP_MUX_SCLK_DISP0_DECON0_VCLK1,
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TOP_MUX_SCLK_DISP0_HDMI_AUDIO,
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TOP_MUX_SCLK_DISP1_DECON1_ECLK0,
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TOP_MUX_SCLK_DISP1_DECON1_ECLK1,
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TOP_MUX_SCLK_FSYS0_USBDRD30,
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TOP_MUX_SCLK_FSYS0_MMC0,
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TOP_MUX_SCLK_FSYS0_UFSUNIPRO20,
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TOP_MUX_SCLK_FSYS0_PHY_24M,
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TOP_MUX_SCLK_FSYS0_UFSUNIPRO_CFG,
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TOP_MUX_SCLK_FSYS1_MMC2,
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TOP_MUX_SCLK_FSYS1_UFSUNIPRO20,
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TOP_MUX_SCLK_FSYS1_PCIE_PHY,
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TOP_MUX_SCLK_FSYS1_UFSUNIPRO_CFG,
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TOP_MUX_SCLK_PERIC0_UART0,
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TOP_MUX_SCLK_PERIC1_SPI0,
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TOP_MUX_SCLK_PERIC1_SPI1,
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TOP_MUX_SCLK_PERIC1_SPI2,
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TOP_MUX_SCLK_PERIC1_SPI3,
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TOP_MUX_SCLK_PERIC1_SPI4,
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TOP_MUX_SCLK_PERIC1_SPI5,
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TOP_MUX_SCLK_PERIC1_SPI6,
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TOP_MUX_SCLK_PERIC1_SPI7,
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TOP_MUX_SCLK_PERIC1_UART1,
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TOP_MUX_SCLK_PERIC1_UART2,
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TOP_MUX_SCLK_PERIC1_UART3,
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TOP_MUX_SCLK_PERIC1_UART4,
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TOP_MUX_SCLK_PERIC1_UART5,
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TOP_MUX_SCLK_CAM1_ISP_SPI0,
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TOP_MUX_SCLK_CAM1_ISP_SPI1,
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TOP_MUX_SCLK_CAM1_ISP_UART,
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TOP_MUX_SCLK_AP2CP_MIF_PLL_OUT,
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TOP_MUX_ACLK_PSCDC_400,
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TOP_MUX_SCLK_BUS_PLL_MNGS,
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TOP_MUX_SCLK_BUS_PLL_APOLLO,
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TOP_MUX_SCLK_BUS_PLL_MIF,
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TOP_MUX_SCLK_BUS_PLL_G3D,
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TOP_MUX_SCLK_ISP_SENSOR0,
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TOP_MUX_SCLK_ISP_SENSOR1,
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TOP_MUX_SCLK_ISP_SENSOR2,
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TOP_MUX_SCLK_ISP_SENSOR3,
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TOP_MUX_SCLK_PROMISE_INT,
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TOP_MUX_SCLK_PROMISE_DISP,
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TOP_MUX_CP2AP_MIF_CLK_USER,
|
|
TOP_MUX_MIF_PLL,
|
|
TOP_MUX_BUS_PLL_MIF,
|
|
TOP_MUX_ACLK_MIF_PLL,
|
|
|
|
/* user_mux_type */
|
|
CAM0_MUX_PHYCLK_RXBYTECLKHS0_CSIS0_USER = TOP_MUX_ACLK_MIF_PLL + 0x1001,
|
|
CAM0_MUX_PHYCLK_RXBYTECLKHS1_CSIS0_USER,
|
|
CAM0_MUX_PHYCLK_RXBYTECLKHS2_CSIS0_USER,
|
|
CAM0_MUX_PHYCLK_RXBYTECLKHS3_CSIS0_USER,
|
|
CAM0_MUX_PHYCLK_RXBYTECLKHS0_CSIS1_USER,
|
|
CAM0_MUX_PHYCLK_RXBYTECLKHS1_CSIS1_USER,
|
|
CAM1_MUX_PHYCLK_RXBYTECLKHS0_CSIS2_USER,
|
|
CAM1_MUX_PHYCLK_RXBYTECLKHS1_CSIS2_USER,
|
|
CAM1_MUX_PHYCLK_RXBYTECLKHS2_CSIS2_USER,
|
|
CAM1_MUX_PHYCLK_RXBYTECLKHS3_CSIS2_USER,
|
|
CAM1_MUX_PHYCLK_RXBYTECLKHS0_CSIS3_USER,
|
|
DISP0_MUX_SCLK_DISP0_HDMI_AUDIO_USER,
|
|
DISP0_MUX_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
|
|
DISP0_MUX_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
|
|
DISP0_MUX_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
|
|
DISP0_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER,
|
|
DISP0_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
|
|
DISP0_MUX_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
|
|
DISP0_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER,
|
|
DISP0_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
|
|
DISP0_MUX_PHYCLK_MIPIDPHY2_RXCLKESC0_USER,
|
|
DISP0_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER,
|
|
DISP0_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV8_USER,
|
|
DISP0_MUX_PHYCLK_DPPHY_CH0_TXD_CLK_USER,
|
|
DISP0_MUX_PHYCLK_DPPHY_CH1_TXD_CLK_USER,
|
|
DISP0_MUX_PHYCLK_DPPHY_CH2_TXD_CLK_USER,
|
|
DISP0_MUX_PHYCLK_DPPHY_CH3_TXD_CLK_USER,
|
|
DISP1_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER,
|
|
DISP1_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER,
|
|
DISP1_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER,
|
|
DISP1_MUX_PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_USER,
|
|
FSYS0_MUX_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
|
|
FSYS0_MUX_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
|
|
FSYS0_MUX_PHYCLK_UFS_TX0_SYMBOL_USER,
|
|
FSYS0_MUX_PHYCLK_UFS_RX0_SYMBOL_USER,
|
|
FSYS0_MUX_PHYCLK_USBHOST20_PHYCLOCK_USER,
|
|
FSYS0_MUX_PHYCLK_USBHOST20PHY_REF_CLK,
|
|
FSYS1_MUX_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_USER,
|
|
FSYS1_MUX_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_USER,
|
|
FSYS1_MUX_PHYCLK_PCIE_WIFI0_TX0_USER,
|
|
FSYS1_MUX_PHYCLK_PCIE_WIFI0_RX0_USER,
|
|
FSYS1_MUX_PHYCLK_PCIE_WIFI1_TX0_USER,
|
|
FSYS1_MUX_PHYCLK_PCIE_WIFI1_RX0_USER,
|
|
FSYS1_MUX_PHYCLK_PCIE_WIFI0_DIG_REFCLK_USER,
|
|
FSYS1_MUX_PHYCLK_PCIE_WIFI1_DIG_REFCLK_USER,
|
|
NUM_OF_MUX_TYPE = FSYS1_MUX_PHYCLK_PCIE_WIFI1_DIG_REFCLK_USER - 0x1000 - mux_type + 1,
|
|
|
|
APOLLO_DIV_APOLLO = div_type,
|
|
APOLLO_DIV_ACLK_APOLLO,
|
|
APOLLO_DIV_ATCLK_APOLLO,
|
|
APOLLO_DIV_PCLK_DBG_APOLLO,
|
|
APOLLO_DIV_PCLK_APOLLO,
|
|
APOLLO_DIV_CNTCLK_APOLLO,
|
|
APOLLO_DIV_APOLLO_RUN_MONITOR,
|
|
APOLLO_DIV_SCLK_PROMISE_APOLLO,
|
|
APOLLO_DIV_APOLLO_PLL,
|
|
AUD_DIV_AUD_CA5,
|
|
AUD_DIV_ACLK_AUD,
|
|
AUD_DIV_PCLK_DBG,
|
|
AUD_DIV_ATCLK_AUD,
|
|
AUD_DIV_AUD_CDCLK,
|
|
AUD_DIV_SCLK_I2S,
|
|
AUD_DIV_SCLK_PCM,
|
|
AUD_DIV_SCLK_SLIMBUS,
|
|
AUD_DIV_SCLK_CP_I2S,
|
|
AUD_DIV_SCLK_ASRC,
|
|
AUD_DIV_CP_CA5,
|
|
AUD_DIV_CP_CDCLK,
|
|
CAM0_DIV_PCLK_CAM0_CSIS0_207,
|
|
CAM0_DIV_PCLK_CAM0_3AA0_207,
|
|
CAM0_DIV_PCLK_CAM0_3AA1_207,
|
|
CAM0_DIV_PCLK_CAM0_TREX_264,
|
|
CAM0_DIV_PCLK_CAM0_TREX_132,
|
|
CAM1_DIV_PCLK_CAM1_ARM_168,
|
|
CAM1_DIV_PCLK_CAM1_TREX_VRA_264,
|
|
CAM1_DIV_PCLK_CAM1_BUS_132,
|
|
CCORE_DIV_SCLK_HPM_CCORE,
|
|
DISP0_DIV_PCLK_DISP0_0_133,
|
|
DISP0_DIV_SCLK_DECON0_ECLK0,
|
|
DISP0_DIV_SCLK_DECON0_VCLK0,
|
|
DISP0_DIV_SCLK_DECON0_VCLK1,
|
|
DISP0_DIV_PHYCLK_HDMIPHY_PIXEL_CLKO,
|
|
DISP0_DIV_PHYCLK_HDMIPHY_TMDS_20B_CLKO,
|
|
DISP1_DIV_PCLK_DISP1_0_133,
|
|
DISP1_DIV_SCLK_DECON1_ECLK0,
|
|
DISP1_DIV_SCLK_DECON1_ECLK1,
|
|
FSYS1_DIV_PCLK_COMBO_PHY_WIFI,
|
|
G3D_DIV_ACLK_G3D,
|
|
G3D_DIV_PCLK_G3D,
|
|
G3D_DIV_SCLK_HPM_G3D,
|
|
G3D_DIV_SCLK_ATE_G3D,
|
|
ISP0_DIV_PCLK_ISP0,
|
|
ISP0_DIV_PCLK_ISP0_TPU,
|
|
ISP0_DIV_PCLK_ISP0_TREX_264,
|
|
ISP0_DIV_PCLK_ISP0_TREX_132,
|
|
ISP1_DIV_PCLK_ISP1_234,
|
|
MFC_DIV_PCLK_MFC_150,
|
|
MIF0_DIV_PCLK_MIF,
|
|
MIF0_DIV_SCLK_HPM_MIF,
|
|
MIF1_DIV_PCLK_MIF,
|
|
MIF1_DIV_SCLK_HPM_MIF,
|
|
MIF2_DIV_PCLK_MIF,
|
|
MIF2_DIV_SCLK_HPM_MIF,
|
|
MIF3_DIV_PCLK_MIF,
|
|
MIF3_DIV_SCLK_HPM_MIF,
|
|
MIF0_DIV_PCLK_SMC,
|
|
MIF1_DIV_PCLK_SMC,
|
|
MIF2_DIV_PCLK_SMC,
|
|
MIF3_DIV_PCLK_SMC,
|
|
MNGS_DIV_MNGS,
|
|
MNGS_DIV_ACLK_MNGS,
|
|
MNGS_DIV_ATCLK_MNGS_CORE,
|
|
MNGS_DIV_ATCLK_MNGS_SOC,
|
|
MNGS_DIV_ATCLK_MNGS_CSSYS_TRACECLK,
|
|
MNGS_DIV_ATCLK_MNGS_ASYNCATB_CAM1,
|
|
MNGS_DIV_ATCLK_MNGS_ASYNCATB_AUD,
|
|
MNGS_DIV_PCLK_DBG_MNGS,
|
|
MNGS_DIV_PCLK_RUN_MONITOR,
|
|
MNGS_DIV_PCLK_MNGS,
|
|
MNGS_DIV_CNTCLK_MNGS,
|
|
MNGS_DIV_MNGS_RUN_MONITOR,
|
|
MNGS_DIV_SCLK_PROMISE_MNGS,
|
|
MNGS_DIV_MNGS_PLL,
|
|
MSCL_DIV_PCLK_MSCL,
|
|
TOP_DIV_ACLK_CCORE_800,
|
|
TOP_DIV_ACLK_CCORE_264,
|
|
TOP_DIV_ACLK_CCORE_G3D_800,
|
|
TOP_DIV_ACLK_CCORE_528,
|
|
TOP_DIV_ACLK_CCORE_132,
|
|
TOP_DIV_PCLK_CCORE_66,
|
|
TOP_DIV_ACLK_BUS0_528,
|
|
TOP_DIV_ACLK_BUS0_200,
|
|
TOP_DIV_PCLK_BUS0_132,
|
|
TOP_DIV_ACLK_BUS1_528,
|
|
TOP_DIV_PCLK_BUS1_132,
|
|
TOP_DIV_ACLK_DISP0_0_400,
|
|
TOP_DIV_ACLK_DISP0_1_400,
|
|
TOP_DIV_ACLK_DISP1_0_400,
|
|
TOP_DIV_ACLK_DISP1_1_400,
|
|
TOP_DIV_ACLK_MFC_600,
|
|
TOP_DIV_ACLK_MSCL0_528,
|
|
TOP_DIV_ACLK_MSCL1_528,
|
|
TOP_DIV_ACLK_IMEM_266,
|
|
TOP_DIV_ACLK_IMEM_200,
|
|
TOP_DIV_ACLK_IMEM_100,
|
|
TOP_DIV_ACLK_FSYS0_200,
|
|
TOP_DIV_ACLK_FSYS1_200,
|
|
TOP_DIV_ACLK_PERIS_66,
|
|
TOP_DIV_ACLK_PERIC0_66,
|
|
TOP_DIV_ACLK_PERIC1_66,
|
|
TOP_DIV_ACLK_ISP0_ISP0_528,
|
|
TOP_DIV_ACLK_ISP0_TPU_400,
|
|
TOP_DIV_ACLK_ISP0_TREX_528,
|
|
TOP_DIV_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D,
|
|
TOP_DIV_ACLK_ISP1_ISP1_468,
|
|
TOP_DIV_ACLK_CAM0_CSIS0_414,
|
|
TOP_DIV_ACLK_CAM0_CSIS1_168,
|
|
TOP_DIV_ACLK_CAM0_CSIS2_234,
|
|
TOP_DIV_ACLK_CAM0_3AA0_414,
|
|
TOP_DIV_ACLK_CAM0_3AA1_414,
|
|
TOP_DIV_ACLK_CAM0_CSIS3_132,
|
|
TOP_DIV_ACLK_CAM0_TREX_528,
|
|
TOP_DIV_ACLK_CAM1_ARM_672,
|
|
TOP_DIV_ACLK_CAM1_TREX_VRA_528,
|
|
TOP_DIV_ACLK_CAM1_TREX_B_528,
|
|
TOP_DIV_ACLK_CAM1_BUS_264,
|
|
TOP_DIV_ACLK_CAM1_PERI_84,
|
|
TOP_DIV_ACLK_CAM1_CSIS2_414,
|
|
TOP_DIV_ACLK_CAM1_CSIS3_132,
|
|
TOP_DIV_ACLK_CAM1_SCL_566,
|
|
TOP_DIV_SCLK_DISP0_DECON0_ECLK0,
|
|
TOP_DIV_SCLK_DISP0_DECON0_VCLK0,
|
|
TOP_DIV_SCLK_DISP0_DECON0_VCLK1,
|
|
TOP_DIV_SCLK_DISP0_HDMI_AUDIO,
|
|
TOP_DIV_SCLK_DISP1_DECON1_ECLK0,
|
|
TOP_DIV_SCLK_DISP1_DECON1_ECLK1,
|
|
TOP_DIV_SCLK_FSYS0_USBDRD30,
|
|
TOP_DIV_SCLK_FSYS0_MMC0,
|
|
TOP_DIV_SCLK_FSYS0_UFSUNIPRO20,
|
|
TOP_DIV_SCLK_FSYS0_PHY_24M,
|
|
TOP_DIV_SCLK_FSYS0_UFSUNIPRO_CFG,
|
|
TOP_DIV_SCLK_FSYS1_MMC2,
|
|
TOP_DIV_SCLK_FSYS1_UFSUNIPRO20,
|
|
TOP_DIV_SCLK_FSYS1_PCIE_PHY,
|
|
TOP_DIV_SCLK_FSYS1_UFSUNIPRO_CFG,
|
|
TOP_DIV_SCLK_PERIC0_UART0,
|
|
TOP_DIV_SCLK_PERIC1_SPI0,
|
|
TOP_DIV_SCLK_PERIC1_SPI1,
|
|
TOP_DIV_SCLK_PERIC1_SPI2,
|
|
TOP_DIV_SCLK_PERIC1_SPI3,
|
|
TOP_DIV_SCLK_PERIC1_SPI4,
|
|
TOP_DIV_SCLK_PERIC1_SPI5,
|
|
TOP_DIV_SCLK_PERIC1_SPI6,
|
|
TOP_DIV_SCLK_PERIC1_SPI7,
|
|
TOP_DIV_SCLK_PERIC1_UART1,
|
|
TOP_DIV_SCLK_PERIC1_UART2,
|
|
TOP_DIV_SCLK_PERIC1_UART3,
|
|
TOP_DIV_SCLK_PERIC1_UART4,
|
|
TOP_DIV_SCLK_PERIC1_UART5,
|
|
TOP_DIV_SCLK_CAM1_ISP_SPI0,
|
|
TOP_DIV_SCLK_CAM1_ISP_SPI1,
|
|
TOP_DIV_SCLK_CAM1_ISP_UART,
|
|
TOP_DIV_SCLK_AP2CP_MIF_PLL_OUT,
|
|
TOP_DIV_ACLK_PSCDC_400,
|
|
TOP_DIV_SCLK_BUS_PLL_MNGS,
|
|
TOP_DIV_SCLK_BUS_PLL_APOLLO,
|
|
TOP_DIV_SCLK_BUS_PLL_MIF,
|
|
TOP_DIV_SCLK_BUS_PLL_G3D,
|
|
TOP_DIV_SCLK_ISP_SENSOR0,
|
|
TOP_DIV_SCLK_ISP_SENSOR1,
|
|
TOP_DIV_SCLK_ISP_SENSOR2,
|
|
TOP_DIV_SCLK_ISP_SENSOR3,
|
|
TOP_DIV_SCLK_PROMISE_INT,
|
|
TOP_DIV_SCLK_PROMISE_DISP,
|
|
NUM_OF_DIV_TYPE = TOP_DIV_SCLK_PROMISE_DISP - div_type + 1,
|
|
|
|
|
|
APOLLO_GATE_ACLK_ASYNCACES_APOLLO_CCI = gate_type,
|
|
APOLLO_GATE_ACLK_ASATBSLV_APOLLO3_CSSYS,
|
|
APOLLO_GATE_ACLK_ASATBSLV_APOLLO2_CSSYS,
|
|
APOLLO_GATE_ACLK_ASATBSLV_APOLLO1_CSSYS,
|
|
APOLLO_GATE_ACLK_ASATBSLV_APOLLO0_CSSYS,
|
|
APOLLO_GATE_PCLKDBG_DUMP_PC_APOLLO,
|
|
APOLLO_GATE_PCLKDBG_ASAPBMST_CSSYS_APOLLO,
|
|
APOLLO_GATE_PCLK_SYSREG_APOLLO,
|
|
APOLLO_GATE_PCLK_PMU_APOLLO,
|
|
APOLLO_GATE_PCLK_AXI2APB_APOLLO_ACLK,
|
|
APOLLO_GATE_PCLK_XIU_PERI_APOLLO_ACLK,
|
|
APOLLO_GATE_PCLK_HPM_APOLLO,
|
|
APOLLO_GATE_SCLK_APOLLO,
|
|
APOLLO_GATE_SCLK_PROMISE_APOLLO,
|
|
AUD_GATE_SCLK_CA5,
|
|
AUD_GATE_PCLK_PPMU_AUD,
|
|
AUD_GATE_PCLK_CP_I2S,
|
|
AUD_GATE_PCLK_SYSREG_AUD,
|
|
AUD_GATE_PCLK_GPIO_AUD,
|
|
AUD_GATE_PCLK_PMU_AUD,
|
|
AUD_GATE_PCLK_SLIMBUS,
|
|
AUD_GATE_PCLK_PCM,
|
|
AUD_GATE_PCLK_I2S,
|
|
AUD_GATE_PCLK_TIMER,
|
|
AUD_GATE_PCLK_SFR1,
|
|
AUD_GATE_PCLK_SFR0,
|
|
AUD_GATE_PCLK_SMMU,
|
|
AUD_GATE_ACLK_PPMU_AUD,
|
|
AUD_GATE_ACLK_INTR,
|
|
AUD_GATE_ACLK_XIU_LPASSX,
|
|
AUD_GATE_ACLK_SMMU,
|
|
AUD_GATE_ACLK_AXI_LH_ASYNC_SI_TOP,
|
|
AUD_GATE_ACLK_AXI_LH_ASYNC_MI_TOP,
|
|
AUD_GATE_ACLK_AXI_US_32TO64,
|
|
AUD_GATE_ACLK_SRAMC,
|
|
AUD_GATE_ACLK_DMAC,
|
|
AUD_GATE_PCLK_DBG,
|
|
AUD_GATE_ACLK_ATCLK_AUD,
|
|
AUD_GATE_SCLK_I2S,
|
|
AUD_GATE_SCLK_PCM,
|
|
AUD_GATE_SCLK_SLIMBUS,
|
|
AUD_GATE_SCLK_CP_I2S,
|
|
AUD_GATE_SCLK_ASRC,
|
|
AUD_GATE_SCLK_SLIMBUS_CLKIN,
|
|
AUD_GATE_SCLK_I2S_BCLK,
|
|
BUS0_GATE_ACLK_ACE_FSYS1,
|
|
BUS0_GATE_ACLK_LH_ISP0,
|
|
BUS0_GATE_ACLK_LH_DISP11,
|
|
BUS0_GATE_ACLK_LH_DISP10,
|
|
BUS0_GATE_ACLK_LH_DISP01,
|
|
BUS0_GATE_ACLK_LH_DISP00,
|
|
BUS0_GATE_ACLK_LH_CAM1,
|
|
BUS0_GATE_ACLK_LH_CAM0,
|
|
BUS0_GATE_ACLK_TREX_BUS0,
|
|
BUS0_GATE_ACLK_LH_FSYS1,
|
|
BUS0_GATE_PCLK_CMU_BUS0,
|
|
BUS0_GATE_PCLK_TREX_BUS0,
|
|
BUS0_GATE_PCLK_PMU_BUS0,
|
|
BUS0_GATE_PCLK_SYSREG_BUS0,
|
|
BUS0_GATE_PCLK_LH_FSYS1SFRX,
|
|
BUS0_GATE_PCLK_LH_PERIC1P,
|
|
BUS0_GATE_PCLK_LH_PERIC0P,
|
|
BUS0_GATE_PCLK_LH_PERISFRX,
|
|
BUS0_GATE_PCLK_LH_DISP1SFRX,
|
|
BUS0_GATE_PCLK_LH_DISP0SFRX,
|
|
BUS0_GATE_PCLK_LH_ISPHX,
|
|
BUS0_GATE_PCLK_LH_IS0X,
|
|
BUS0_GATE_PCLK_AXI2APB_2MB_BUS0_TP,
|
|
BUS0_GATE_PCLK_AHB2APB_BUS0P,
|
|
BUS0_GATE_PCLK_AXI2APB_2MB_BUS0_TD,
|
|
BUS0_GATE_PCLK_TREX_P_BUS0,
|
|
BUS0_GATE_ACLK_TREX_P_BUS0,
|
|
BUS1_GATE_ACLK_LH_MSCL1,
|
|
BUS1_GATE_ACLK_LH_MSCL0,
|
|
BUS1_GATE_ACLK_LH_MFC1,
|
|
BUS1_GATE_ACLK_LH_MFC0,
|
|
BUS1_GATE_ACLK_LH_FSYS0,
|
|
BUS1_GATE_ACLK_TREX_BUS1,
|
|
BUS1_GATE_PCLK_CMU_BUS1,
|
|
BUS1_GATE_PCLK_TREX_BUS1,
|
|
BUS1_GATE_PCLK_SYSREG_BUS1,
|
|
BUS1_GATE_PCLK_PMU_BUS1,
|
|
BUS1_GATE_PCLK_LH_MSCLSFRX,
|
|
BUS1_GATE_PCLK_LH_MFCP,
|
|
BUS1_GATE_PCLK_LH_FSYS0SFRX,
|
|
BUS1_GATE_PCLK_AHB2APB_BUS1P,
|
|
BUS1_GATE_PCLK_AXI2APB_2MB_BUS1_TP,
|
|
BUS1_GATE_PCLK_AXI2APB_2MB_BUS1_TD,
|
|
BUS1_GATE_PCLK_TREX_P_BUS1,
|
|
BUS1_GATE_ACLK_TREX_P_BUS1,
|
|
CAM0_GATE_ACLK_BNS,
|
|
CAM0_GATE_ACLK_PXL_ASBS_CSIS2_int,
|
|
CAM0_GATE_ACLK_CSIS0,
|
|
CAM0_GATE_PCLK_BNS,
|
|
CAM0_GATE_ACLK_CSIS1,
|
|
CAM0_GATE_ACLK_CSIS2,
|
|
CAM0_GATE_ACLK_CSIS3,
|
|
CAM0_GATE_ACLK_3AA0,
|
|
CAM0_GATE_PCLK_3AA0,
|
|
CAM0_GATE_ACLK_3AA1,
|
|
CAM0_GATE_PCLK_3AA1,
|
|
CAM0_GATE_ACLK_SFW110_IS_A,
|
|
CAM0_GATE_ACLK_SysMMU6_IS_A,
|
|
CAM0_GATE_ACLK_TREX_A_5x1_IS_A,
|
|
CAM0_GATE_ACLK_LH_ASYNC_SI_CAM0,
|
|
CAM0_GATE_PCLK_PMU_CAM0,
|
|
CAM0_GATE_PCLK_SYSREG_CAM0,
|
|
CAM0_GATE_ACLK_LH_ASYNC_MI_CAM0,
|
|
CAM0_GATE_ACLK_XIUASYNC_MI_CAM0,
|
|
CAM0_GATE_PCLK_CAM0,
|
|
CAM0_GATE_PCLK_CSIS1,
|
|
CAM0_GATE_PCLK_CSIS0,
|
|
CAM0_GATE_PCLK_XIUASYNC_MI_CAM0,
|
|
CAM0_GATE_PCLK_TREX_A_5x1_IS_A,
|
|
CAM0_GATE_PCLK_SysMMU6_IS_A,
|
|
CAM0_GATE_PCLK_SFW110_IS_A_IS_A,
|
|
CAM0_GATE_SCLK_PROMISE_CAM0,
|
|
CAM0_GATE_PHYCLK_HS0_CSIS0_RX_BYTE,
|
|
CAM0_GATE_PHYCLK_HS1_CSIS0_RX_BYTE,
|
|
CAM0_GATE_PHYCLK_HS2_CSIS0_RX_BYTE,
|
|
CAM0_GATE_PHYCLK_HS3_CSIS0_RX_BYTE,
|
|
CAM0_GATE_PHYCLK_HS0_CSIS1_RX_BYTE,
|
|
CAM0_GATE_PHYCLK_HS1_CSIS1_RX_BYTE,
|
|
CAM0_GATE_PCLK_HPM_APBIF_CAM0,
|
|
CAM0_LOCAL_GATE_ACLK_BNS,
|
|
CAM0_LOCAL_GATE_ACLK_PXL_ASBS_CSIS2_int,
|
|
CAM0_LOCAL_GATE_ACLK_CSIS0,
|
|
CAM0_LOCAL_GATE_PCLK_BNS,
|
|
CAM0_LOCAL_GATE_ACLK_CSIS1,
|
|
CAM0_LOCAL_GATE_ACLK_CSIS2,
|
|
CAM0_LOCAL_GATE_ACLK_CSIS3,
|
|
CAM0_LOCAL_GATE_ACLK_3AA0,
|
|
CAM0_LOCAL_GATE_PCLK_3AA0,
|
|
CAM0_LOCAL_GATE_ACLK_3AA1,
|
|
CAM0_LOCAL_GATE_PCLK_3AA1,
|
|
CAM0_LOCAL_GATE_PCLK_CSIS1,
|
|
CAM0_LOCAL_GATE_PCLK_CSIS0,
|
|
CAM1_GATE_ACLK_ARM,
|
|
CAM1_GATE_PCLK_ARM,
|
|
CAM1_GATE_ACLK_SMMU_VRA,
|
|
CAM1_GATE_ACLK_VRA,
|
|
CAM1_GATE_PCLK_VRA,
|
|
CAM1_GATE_ACLK_LH_SI,
|
|
CAM1_GATE_ACLK_TREX_CAM1,
|
|
CAM1_GATE_ACLK_XIU_from_ISP1,
|
|
CAM1_GATE_ACLK_SMMU_IS_B,
|
|
CAM1_GATE_ACLK_SFW,
|
|
CAM1_GATE_ACLK_ASYNC_CA7_TO_DRAM,
|
|
CAM1_GATE_ACLK_SMMU_ISPCPU,
|
|
CAM1_GATE_ACLK_TREX_B,
|
|
CAM1_GATE_ACLK_LH_MI,
|
|
CAM1_GATE_ACLK_PERI,
|
|
CAM1_GATE_PCLK_CSIS3,
|
|
CAM1_GATE_PCLK_CSIS2,
|
|
CAM1_GATE_ACLK_XIU_to_CAM0,
|
|
CAM1_GATE_ACLK_XIU_to_ISP1,
|
|
CAM1_GATE_ACLK_XIU_to_ISP0,
|
|
CAM1_GATE_PCLK_CMU_LOCAL,
|
|
CAM1_GATE_PCLK_SYSREG_CAM1,
|
|
CAM1_GATE_PCLK_PMU_CAM1,
|
|
CAM1_GATE_PCLK_TREX_CAM1,
|
|
CAM1_GATE_PCLK_XIU_from_ISP1,
|
|
CAM1_GATE_PCLK_PERI,
|
|
CAM1_GATE_PCLK_SMMU_ISPCPU,
|
|
CAM1_GATE_PCLK_SMMU_VRA,
|
|
CAM1_GATE_PCLK_SMMU_IS_B,
|
|
CAM1_GATE_PCLK_SFW,
|
|
CAM1_GATE_PCLK_TREX_B,
|
|
CAM1_GATE_PCLK_WDT,
|
|
CAM1_GATE_PCLK_UART,
|
|
CAM1_GATE_PCLK_SPI1,
|
|
CAM1_GATE_PCLK_SPI0,
|
|
CAM1_GATE_PCLK_PWM,
|
|
CAM1_GATE_PCLK_MCUCTL,
|
|
CAM1_GATE_PCLK_I2C3,
|
|
CAM1_GATE_PCLK_I2C2,
|
|
CAM1_GATE_PCLK_I2C1,
|
|
CAM1_GATE_PCLK_I2C0,
|
|
CAM1_GATE_ACLK_PDMA,
|
|
CAM1_GATE_ACLK_BRIDGE_PERI,
|
|
CAM1_GATE_ACLK_CSIS2,
|
|
CAM1_GATE_ACLK_CSIS3,
|
|
CAM1_GATE_ACLK_SMMU_MC_SC,
|
|
CAM1_GATE_ACLK_MC_SC,
|
|
CAM1_GATE_PCLK_SMMU_MC_SC,
|
|
CAM1_GATE_SCLK_ISP_PERI_IS_B_SPI0_EXT_CLK_ISP,
|
|
CAM1_GATE_SCLK_ISP_PERI_IS_B_SPI1_EXT_CLK_ISP,
|
|
CAM1_GATE_SCLK_ISP_PERI_IS_B_UART_EXT_CLK_ISP,
|
|
CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C3_ISP,
|
|
CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C2_ISP,
|
|
CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C1_ISP,
|
|
CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C0_ISP,
|
|
CAM1_GATE_SCLK_ISP_PERI_IS_B_PWM_ISP,
|
|
CAM1_GATE_PHYCLK_HS0_CSIS2_RX_BYTE,
|
|
CAM1_GATE_PHYCLK_HS1_CSIS2_RX_BYTE,
|
|
CAM1_GATE_PHYCLK_HS2_CSIS2_RX_BYTE,
|
|
CAM1_GATE_PHYCLK_HS3_CSIS2_RX_BYTE,
|
|
CAM1_GATE_PHYCLK_HS0_CSIS3_RX_BYTE,
|
|
CAM1_LOCAL_GATE_ACLK_VRA,
|
|
CAM1_LOCAL_GATE_PCLK_VRA,
|
|
CAM1_LOCAL_GATE_PCLK_CSIS3,
|
|
CAM1_LOCAL_GATE_PCLK_CSIS2,
|
|
CAM1_LOCAL_GATE_PCLK_WDT,
|
|
CAM1_LOCAL_GATE_PCLK_UART,
|
|
CAM1_LOCAL_GATE_PCLK_SPI1,
|
|
CAM1_LOCAL_GATE_PCLK_SPI0,
|
|
CAM1_LOCAL_GATE_PCLK_PWM,
|
|
CAM1_LOCAL_GATE_PCLK_MCUCTL,
|
|
CAM1_LOCAL_GATE_PCLK_I2C3,
|
|
CAM1_LOCAL_GATE_PCLK_I2C2,
|
|
CAM1_LOCAL_GATE_PCLK_I2C1,
|
|
CAM1_LOCAL_GATE_PCLK_I2C0,
|
|
CAM1_LOCAL_GATE_ACLK_PDMA,
|
|
CAM1_LOCAL_GATE_ACLK_CSIS2,
|
|
CAM1_LOCAL_GATE_ACLK_CSIS3,
|
|
CAM1_LOCAL_GATE_ACLK_MC_SC,
|
|
CCORE_GATE_ACLK_AXI_AS_SI_IRPM,
|
|
CCORE_GATE_ACLK_MPACEBRIDGE,
|
|
CCORE_GATE_ACLK_PULSE2HS,
|
|
CCORE_GATE_ACLK_DBG_LH_MI_MIF_CCORE,
|
|
CCORE_GATE_ACLK_SCI_PPC_WRAPPER,
|
|
CCORE_GATE_ACLK_ACE_AS_MI_APL_CCORE,
|
|
CCORE_GATE_ACLK_MPACE_SI,
|
|
CCORE_GATE_ACLK_CPACE_MI,
|
|
CCORE_GATE_ACLK_ATB_SI_CCOREBDU_MNGSCS,
|
|
CCORE_GATE_ACLK_BDU,
|
|
CCORE_GATE_ACLK_TREX_CCORE_SCI,
|
|
CCORE_GATE_ACLK_SCI,
|
|
CCORE_GATE_ACLK_CLEANY_CPPERI,
|
|
CCORE_GATE_ACLK_AXI_US_CPPERI,
|
|
CCORE_GATE_ACLK_AXI_LH_MI_CPPERI_CCORE,
|
|
CCORE_GATE_ACLK_AXI_LH_SI_CCORESFRX_IMEMX,
|
|
CCORE_GATE_ACLK_AXI_LH_MI_G3DXIRAM_CCORESFR,
|
|
CCORE_GATE_ACLK_AXI_DS_IRPM,
|
|
CCORE_GATE_ACLK_XIU_CCORESFRX,
|
|
CCORE_GATE_ACLK_TREX_P_CCORE_BUS,
|
|
CCORE_GATE_ACLK_TREX_CCORE_PERI,
|
|
CCORE_GATE_ACLK_AXI_AS_MI_IRPM,
|
|
CCORE_GATE_ACLK_TREX_CCORE_G3D,
|
|
CCORE_GATE_ACLK_ACEL_LH_MI_G3DX1_CCORETD,
|
|
CCORE_GATE_ACLK_ACEL_LH_MI_G3DX0_CCORETD,
|
|
CCORE_GATE_ACLK_ATB_APL_MNGS,
|
|
CCORE_GATE_ACLK_XIU_CPX,
|
|
CCORE_GATE_ACLK_CLEANY_CPDATA,
|
|
CCORE_GATE_ACLK_AXI_LH_MI_CPDATA_CCORE,
|
|
CCORE_GATE_ACLK_AXI_LH_MI_IMEMX_CCORETD,
|
|
CCORE_GATE_ACLK_AXI_LH_MI_AUDX_CCORETD,
|
|
CCORE_GATE_ACLK_AXI_AS_MI_MNGSCS_CCORETD,
|
|
CCORE_GATE_ACLK_TREX_CCORE,
|
|
CCORE_GATE_PCLK_CMU,
|
|
CCORE_GATE_PCLK_HPM_APBIF,
|
|
CCORE_GATE_PCLK_SCI,
|
|
CCORE_GATE_PCLK_GPIO_CCORE,
|
|
CCORE_GATE_PCLK_S_MAILBOX,
|
|
CCORE_GATE_PCLK_MAILBOX,
|
|
CCORE_GATE_PCLK_SYSREG_CCORE,
|
|
CCORE_GATE_PCLK_GPIO_APBIF_ALIVE,
|
|
CCORE_GATE_PCLK_SCI_PPC_WRAPPER,
|
|
CCORE_GATE_PCLK_VT_MON_APB,
|
|
CCORE_GATE_PCLK_PMU_CCORE,
|
|
CCORE_GATE_PCLK_PMU_APBIF,
|
|
CCORE_GATE_PCLK_CMU_TOPC_APBIF,
|
|
CCORE_GATE_PCLK_AXI2APB_CORESIGHT,
|
|
CCORE_GATE_PCLK_AXI2APB_TREX_P_CCORE,
|
|
CCORE_GATE_PCLK_AXI2APB_TREX_CCORE,
|
|
CCORE_GATE_PCLK_AXI2APB_CCORE,
|
|
CCORE_GATE_PCLK_TREX_P_CCORE,
|
|
CCORE_GATE_PCLK_TREX_CCORE,
|
|
CCORE_GATE_PCLK_BDU,
|
|
CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF3P,
|
|
CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF2P,
|
|
CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF1P,
|
|
CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF0P,
|
|
CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_G3DP,
|
|
CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_AUDX,
|
|
CCORE_GATE_ACLK_AXI_AS_SI_CCORETP_APL,
|
|
CCORE_GATE_ACLK_AXI_AS_SI_CCORETP_MNGS,
|
|
CCORE_GATE_ACLK_APB_AS_MI_CCORETP_MNGSCS,
|
|
CCORE_GATE_ACLK_APB_AS_MI_MNGSCS_CCOREBDU,
|
|
CCORE_GATE_ACLK_TREX_P_CCORE,
|
|
CCORE_GATE_PCLK_APBASYNC_BAT_AP,
|
|
CCORE_GATE_PCLK_APBASYNC_BAT_CP,
|
|
CCORE_GATE_PCLK_HSI2C_BAT_AP,
|
|
CCORE_GATE_PCLK_HSI2C,
|
|
CCORE_GATE_PCLK_HSI2C_BAT_CP,
|
|
CCORE_GATE_PCLK_HSI2C_CP,
|
|
CCORE_GATE_SCLK_PROMISE,
|
|
DISP0_GATE_ACLK_PPMU_DISP0_0,
|
|
DISP0_GATE_ACLK_SMMU_DISP0_0,
|
|
DISP0_GATE_ACLK_XIU_DISP0_0,
|
|
DISP0_GATE_ACLK_LH_ASYNC_SI_R_TOP_DISP,
|
|
DISP0_GATE_ACLK_VPP0_ACLK_0,
|
|
DISP0_GATE_ACLK_PPMU_DISP0_1,
|
|
DISP0_GATE_ACLK_SMMU_DISP0_1,
|
|
DISP0_GATE_ACLK_XIU_DISP0_1,
|
|
DISP0_GATE_ACLK_LH_ASYNC_SI_TOP_DISP,
|
|
DISP0_GATE_ACLK_VPP0_ACLK_1,
|
|
DISP0_GATE_ACLK_SFW_DISP0_0,
|
|
DISP0_GATE_ACLK_SFW_DISP0_1,
|
|
DISP0_GATE_PCLK_SMMU_DISP0_1,
|
|
DISP0_GATE_PCLK_SMMU_DISP0_0,
|
|
DISP0_GATE_PCLK_PPMU_DISP0_1,
|
|
DISP0_GATE_PCLK_PPMU_DISP0_0,
|
|
DISP0_GATE_PCLK_HDMI_PHY,
|
|
DISP0_GATE_PCLK_DISP0_MUX,
|
|
DISP0_GATE_PCLK_DP,
|
|
DISP0_GATE_PCLK_HDMI_AUDIO,
|
|
DISP0_GATE_PCLK_HDMI,
|
|
DISP0_GATE_PCLK_DSIM2,
|
|
DISP0_GATE_PCLK_DSIM1,
|
|
DISP0_GATE_PCLK_DSIM0,
|
|
DISP0_GATE_PCLK_SYSREG_DISP0,
|
|
DISP0_GATE_PCLK_PMU_DISP0,
|
|
DISP0_GATE_PCLK_CMU_DISP0,
|
|
DISP0_GATE_ACLK_XIU_DISP0SFRX,
|
|
DISP0_GATE_ACLK_AXI2APB_DISP0_1P,
|
|
DISP0_GATE_ACLK_AXI2APB_DISP0_0P,
|
|
DISP0_GATE_ACLK_AXI_LH_ASYNC_MI_DISP0SFR,
|
|
DISP0_GATE_PCLK_HPM_APBIF_DISP0,
|
|
DISP0_GATE_PCLK_DECON0,
|
|
DISP0_GATE_PCLK_VPP0_0,
|
|
DISP0_GATE_PCLK_VPP0_1,
|
|
DISP0_GATE_PCLK_SFW_DISP0_0,
|
|
DISP0_GATE_PCLK_SFW_DISP0_1,
|
|
DISP0_GATE_SCLK_DISP1_400,
|
|
DISP0_GATE_SCLK_DECON0_ECLK0,
|
|
DISP0_GATE_SCLK_DECON0_VCLK0,
|
|
DISP0_GATE_SCLK_DECON0_VCLK1,
|
|
DISP0_GATE_SCLK_HDMI_AUDIO,
|
|
DISP0_GATE_SCLK_PROMISE_DISP0,
|
|
DISP0_GATE_PHYCLK_HDMIPHY_TMDS_20B_CLKO,
|
|
DISP0_GATE_PHYCLK_HDMIPHY_TMDS_10B_CLKO,
|
|
DISP0_GATE_PHYCLK_HDMIPHY_PIXEL_CLKO,
|
|
DISP0_GATE_PHYCLK_MIPIDPHY0_BITCLKDIV8,
|
|
DISP0_GATE_PHYCLK_MIPIDPHY0_RXCLKESC0,
|
|
DISP0_GATE_PHYCLK_MIPIDPHY1_BITCLKDIV8,
|
|
DISP0_GATE_PHYCLK_MIPIDPHY1_RXCLKESC0,
|
|
DISP0_GATE_PHYCLK_MIPIDPHY2_BITCLKDIV8,
|
|
DISP0_GATE_PHYCLK_MIPIDPHY2_RXCLKESC0,
|
|
DISP0_GATE_PHYCLK_DPPHY_CH3_TXD_CLK,
|
|
DISP0_GATE_PHYCLK_DPPHY_CH2_TXD_CLK,
|
|
DISP0_GATE_PHYCLK_DPPHY_CH1_TXD_CLK,
|
|
DISP0_GATE_PHYCLK_DPPHY_CH0_TXD_CLK,
|
|
DISP0_GATE_OSCCLK_I_MIPI_DPHY_M4S4_M_XI,
|
|
DISP0_GATE_OSCCLK_I_MIPI_DPHY_M4S0_M_XI,
|
|
DISP0_GATE_OSCCLK_I_MIPI_DPHY_M1S0_M_XI,
|
|
DISP0_GATE_OSCCLK_I_DPTX_PHY_I_REF_CLK_24M,
|
|
DISP0_GATE_OSCCLK_DP_I_CLK_24M,
|
|
DISP1_GATE_ACLK_XIU_DISP1X0,
|
|
DISP1_GATE_ACLK_AXI_LH_ASYNC_SI_DISP1_0,
|
|
DISP1_GATE_ACLK_PPMU_DISP1_0,
|
|
DISP1_GATE_ACLK_SMMU_DISP1_0,
|
|
DISP1_GATE_ACLK_VPP1_0,
|
|
DISP1_GATE_ACLK_XIU_DISP1X1,
|
|
DISP1_GATE_ACLK_AXI_LH_ASYNC_SI_DISP1_1,
|
|
DISP1_GATE_ACLK_QE_DISP1_WDMA,
|
|
DISP1_GATE_ACLK_PPMU_DISP1_1,
|
|
DISP1_GATE_ACLK_SMMU_DISP1_1,
|
|
DISP1_GATE_ACLK_VPP1_1,
|
|
DISP1_GATE_ACLK_SFW_DISP1_0,
|
|
DISP1_GATE_ACLK_SFW_DISP1_1,
|
|
DISP1_GATE_PCLK_DECON1_1,
|
|
DISP1_GATE_PCLK_DECON1_0,
|
|
DISP1_GATE_PCLK_QE_DISP1_WDMA,
|
|
DISP1_GATE_PCLK_PPMU_DISP1_1,
|
|
DISP1_GATE_PCLK_PPMU_DISP1_0,
|
|
DISP1_GATE_PCLK_SMMU_DISP1_1,
|
|
DISP1_GATE_PCLK_SMMU_DISP1_0,
|
|
DISP1_GATE_PCLK_SYSREG_DISP1,
|
|
DISP1_GATE_PCLK_PMU_DISP1,
|
|
DISP1_GATE_PCLK_CMU_DISP1,
|
|
DISP1_GATE_PCLK_VPP1_0,
|
|
DISP1_GATE_PCLK_VPP1_1,
|
|
DISP1_GATE_ACLK_AXI2APB_DISP1_1X,
|
|
DISP1_GATE_ACLK_AXI2APB_DISP1_0X,
|
|
DISP1_GATE_ACLK_XIU_DISP1SFRX,
|
|
DISP1_GATE_ACLK_AXI_LH_ASYNC_MI_DISP1SFR,
|
|
DISP1_GATE_PCLK_HPM_APBIF_DISP1,
|
|
DISP1_GATE_PCLK_SFW_DISP1_0,
|
|
DISP1_GATE_PCLK_SFW_DISP1_1,
|
|
DISP1_GATE_SCLK_DECON1_ECLK_0,
|
|
DISP1_GATE_SCLK_DECON1_ECLK_1,
|
|
DISP1_GATE_SCLK_PROMISE_DISP1,
|
|
FSYS0_GATE_ACLK_AXI2ACEL_FSYS0X,
|
|
FSYS0_GATE_PCLK_CMU_FSYS0,
|
|
FSYS0_GATE_PCLK_GPIO_FSYS0,
|
|
FSYS0_GATE_PCLK_SYSREG_FSYS0,
|
|
FSYS0_GATE_PCLK_PPMU_FSYS0,
|
|
FSYS0_GATE_PCLK_PMU_FSYS0,
|
|
FSYS0_GATE_PCLK_ETR_USB_FSYS0,
|
|
FSYS0_GATE_HCLK_USBHOST20,
|
|
FSYS0_GATE_ACLK_AXI_US_USBHS_FSYS0X,
|
|
FSYS0_GATE_ACLK_ETR_USB_FSYS0,
|
|
FSYS0_GATE_ACLK_UFS_LINK_EMBEDDED,
|
|
FSYS0_GATE_ACLK_USBDRD30,
|
|
FSYS0_GATE_ACLK_MMC0,
|
|
FSYS0_GATE_ACLK_PDMAS,
|
|
FSYS0_GATE_ACLK_PDMA0,
|
|
FSYS0_GATE_ACLK_PPMU_FSYS0,
|
|
FSYS0_GATE_ACLK_XIU_FSYS0SFRX,
|
|
FSYS0_GATE_ACLK_AXI_US_USBDRD30X_FSYS0X,
|
|
FSYS0_GATE_ACLK_AXI_US_PDMAX_FSYS0X,
|
|
FSYS0_GATE_ACLK_AXI2AHB_FSYS0H,
|
|
FSYS0_GATE_ACLK_AXI2AHB_USBDRD30H,
|
|
FSYS0_GATE_ACLK_AXI_LH_ASYNC_MI_ETR_USB_FSYS0,
|
|
FSYS0_GATE_ACLK_XIU_PDMAX,
|
|
FSYS0_GATE_ACLK_XIU_USBX,
|
|
FSYS0_GATE_ACLK_XIU_EMBEDDEDX,
|
|
FSYS0_GATE_ACLK_XIU_FSYS0X,
|
|
FSYS0_GATE_ACLK_AXI2APB_FSYS0P,
|
|
FSYS0_GATE_ACLK_AHB_BRIDGE_FSYS0H,
|
|
FSYS0_GATE_ACLK_AXI_LH_ASYNC_MI_TOP_FSYS0,
|
|
FSYS0_GATE_ACLK_ACEL_LH_ASYNC_SI_TOP_FSYS0,
|
|
FSYS0_GATE_PCLK_HPM_APBIF_FSYS0,
|
|
FSYS0_GATE_SCLK_USBDRD30_SUSPEND_CLK,
|
|
FSYS0_GATE_SCLK_MMC0,
|
|
FSYS0_GATE_SCLK_UFSUNIPRO_EMBEDDED,
|
|
FSYS0_GATE_SCLK_USBDRD30_REF_CLK,
|
|
FSYS0_GATE_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
|
|
FSYS0_GATE_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
|
|
FSYS0_GATE_PHYCLK_UFS_TX0_SYMBOL,
|
|
FSYS0_GATE_PHYCLK_UFS_RX0_SYMBOL,
|
|
FSYS0_GATE_PHYCLK_USBHOST20_PHYCLOCK,
|
|
FSYS0_GATE_SCLK_PROMISE_FSYS0,
|
|
FSYS0_GATE_SCLK_USBHOST20PHY_REF_CLK,
|
|
FSYS0_GATE_SCLK_UFSUNIPRO_EMBEDDED_CFG,
|
|
FSYS0_GATE_SCLK_USBHOST20_REF_CLK,
|
|
FSYS1_GATE_ACLK_AXI2ACEL_FSYS1X,
|
|
FSYS1_GATE_PCLK_CMU_FSYS1,
|
|
FSYS1_GATE_ACLK_COMBO_PHY_PCS_PCLK_WIFI1,
|
|
FSYS1_GATE_ACLK_COMBO_PHY_PCS_PCLK_WIFI0,
|
|
FSYS1_GATE_PCLK_PMU_FSYS1,
|
|
FSYS1_GATE_PCLK_PPMU_FSYS1,
|
|
FSYS1_GATE_PCLK_GPIO_FSYS1,
|
|
FSYS1_GATE_PCLK_SYSREG_FSYS1,
|
|
FSYS1_GATE_ACLK_SROMC_FSYS1,
|
|
FSYS1_GATE_PCLK_PCIE_WIFI1,
|
|
FSYS1_GATE_ACLK_PCIE_WIFI1_DBI,
|
|
FSYS1_GATE_ACLK_PCIE_WIFI1_SLV,
|
|
FSYS1_GATE_ACLK_PCIE_WIFI1_MSTR,
|
|
FSYS1_GATE_ACLK_AHB2AXI_PCIE_WIFI1,
|
|
FSYS1_GATE_PCLK_PCIE_WIFI0,
|
|
FSYS1_GATE_ACLK_PCIE_WIFI0_DBI,
|
|
FSYS1_GATE_ACLK_PCIE_WIFI0_SLV,
|
|
FSYS1_GATE_ACLK_PCIE_WIFI0_MSTR,
|
|
FSYS1_GATE_ACLK_AHB2AXI_PCIE_WIFI0,
|
|
FSYS1_GATE_ACLK_PPMU_FSYS1,
|
|
FSYS1_GATE_ACLK_AHB_BRIDGE_FSYS1_S4,
|
|
FSYS1_GATE_ACLK_AXI2AHB_FSYS1_S4,
|
|
FSYS1_GATE_ACLK_AXI2APB_FSYS1_S1,
|
|
FSYS1_GATE_ACLK_AXI2AHB_FSYS1_S0,
|
|
FSYS1_GATE_ACLK_XIU_FSYS1SFRX,
|
|
FSYS1_GATE_ACLK_XIU_SDCARDX,
|
|
FSYS1_GATE_ACLK_XIU_FSYS1X,
|
|
FSYS1_GATE_ACLK_AXI_LH_ASYNC_MI_TOP_FSYS1,
|
|
FSYS1_GATE_ACLK_ACEL_LH_ASYNC_SI_TOP_FSYS1,
|
|
FSYS1_GATE_ACLK_UFS_LINK_SDCARD,
|
|
FSYS1_GATE_ACLK_MMC2,
|
|
FSYS1_GATE_PCLK_HPM_APBIF_FSYS1,
|
|
FSYS1_GATE_PCLK_COMBO_PHY_WIFI1,
|
|
FSYS1_GATE_PCLK_COMBO_PHY_WIFI0,
|
|
FSYS1_GATE_SCLK_MMC2,
|
|
FSYS1_GATE_SCLK_UFSUNIPRO_SDCARD,
|
|
FSYS1_GATE_SCLK_UFSUNIPRO_SDCARD_CFG,
|
|
FSYS1_GATE_SCLK_PCIE_LINK_WIFI0,
|
|
FSYS1_GATE_SCLK_PCIE_LINK_WIFI1,
|
|
FSYS1_GATE_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL,
|
|
FSYS1_GATE_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL,
|
|
FSYS1_GATE_PHYCLK_PCIE_WIFI0_TX0,
|
|
FSYS1_GATE_PHYCLK_PCIE_WIFI0_RX0,
|
|
FSYS1_GATE_PHYCLK_PCIE_WIFI1_TX0,
|
|
FSYS1_GATE_PHYCLK_PCIE_WIFI1_RX0,
|
|
FSYS1_GATE_PHYCLK_PCIE_WIFI0_DIG_REFCLK,
|
|
FSYS1_GATE_PHYCLK_PCIE_WIFI1_DIG_REFCLK,
|
|
FSYS1_GATE_PHYCLK_UFS_LINK_SDCARD_RX_PWM_CLK,
|
|
FSYS1_GATE_PHYCLK_UFS_LINK_SDCARD_TX_PWM_CLK,
|
|
FSYS1_GATE_PHYCLK_UFS_LINK_SDCARD_REFCLK_OUT_SOC,
|
|
FSYS1_GATE_SCLK_PROMISE_FSYS1,
|
|
G3D_GATE_ACLK_G3D,
|
|
G3D_GATE_ACLK_GRAY_DEC,
|
|
G3D_GATE_ACLK_SFW100_ACEL_G3D1,
|
|
G3D_GATE_ACLK_SFW100_ACEL_G3D0,
|
|
G3D_GATE_ACLK_XIU_G3D,
|
|
G3D_GATE_ACLK_PPMU_G3D1,
|
|
G3D_GATE_ACLK_PPMU_G3D0,
|
|
G3D_GATE_ACLK_ASYNCAPBM_G3D,
|
|
G3D_GATE_ACLK_ASYNCAXI_G3D,
|
|
G3D_GATE_ACLK_AXI_DS_G3D,
|
|
G3D_GATE_ACLK_ACEL_LH_ASYNC_SI_G3D1,
|
|
G3D_GATE_ACLK_ACEL_LH_ASYNC_SI_G3D0,
|
|
G3D_GATE_PCLK_SFW100_ACEL_G3D1,
|
|
G3D_GATE_PCLK_SFW100_ACEL_G3D0,
|
|
G3D_GATE_PCLK_HPM_G3D,
|
|
G3D_GATE_PCLK_PPMU_G3D1,
|
|
G3D_GATE_PCLK_PPMU_G3D0,
|
|
G3D_GATE_PCLK_PMU_G3D,
|
|
G3D_GATE_ACLK_ASYNCAPBS_G3D,
|
|
G3D_GATE_PCLK_SYSREG_G3D,
|
|
G3D_GATE_ACLK_AXI2APB_G3DP,
|
|
G3D_GATE_ACLK_AXI_LH_ASYNC_MI_G3DP,
|
|
G3D_GATE_SCLK_HPM2_G3D,
|
|
G3D_GATE_SCLK_HPM1_G3D,
|
|
G3D_GATE_SCLK_HPM0_G3D,
|
|
G3D_GATE_SCLK_AXI_LH_ASYNC_SI_G3DIRAM,
|
|
G3D_GATE_SCLK_ASYNCAXI_G3D,
|
|
IMEM_GATE_ACLK_MC,
|
|
IMEM_GATE_ACLK_XIU_3X1_SSS,
|
|
IMEM_GATE_ACLK_AXI_US_APM,
|
|
IMEM_GATE_ACLK_ASYNCAHBMSTM_APM,
|
|
IMEM_GATE_ACLK_ASYNCAHBM_SSS_ATLAS,
|
|
IMEM_GATE_ACLK_LH_ASYNC_SI_IMEM,
|
|
IMEM_GATE_ACLK_PPMU_SSSX,
|
|
IMEM_GATE_ACLK_XIU_IMEMX,
|
|
IMEM_GATE_ACLK_SSS,
|
|
IMEM_GATE_ACLK_RTIC,
|
|
IMEM_GATE_PCLK_CMU_IMEM,
|
|
IMEM_GATE_PCLK_SYSREG_IMEM,
|
|
IMEM_GATE_PCLK_MC,
|
|
IMEM_GATE_PCLK_PPMU_SSSX,
|
|
IMEM_GATE_PCLK_PMU_IMEM,
|
|
IMEM_GATE_ACLK_ASYNCAHBSS_APM,
|
|
IMEM_GATE_ACLK_AXI2AHB_APM,
|
|
IMEM_GATE_ACLK_INT_MEM_ALV,
|
|
IMEM_GATE_ACLK_INT_MEM,
|
|
IMEM_GATE_ACLK_AXIDS_PIMEMX_IMEM,
|
|
IMEM_GATE_ACLK_AXILHASYNCM_PIMEMX,
|
|
IMEM_GATE_ACLK_AXI2APB_IMEM_1,
|
|
IMEM_GATE_ACLK_AXI2APB_IMEM_0,
|
|
IMEM_GATE_ACLK_XIU_PIMEMX1,
|
|
IMEM_GATE_ACLK_XIU_PIMEMX0,
|
|
IMEM_GATE_ACLK_GIC,
|
|
IMEM_GATE_PCLK_SSS,
|
|
IMEM_GATE_PCLK_RTIC,
|
|
IMEM_GATE_ACLK_ASYNCAHBSM_APM,
|
|
IMEM_GATE_ACLK_AHB2AXI_APM,
|
|
IMEM_GATE_ACLK_ASYNCAHBMSTS_APM,
|
|
IMEM_GATE_ACLK_CM3_APM,
|
|
IMEM_GATE_ACLK_AHB_BUSMATRIX_APM,
|
|
IMEM_GATE_SCLK_CM3_APM,
|
|
IMEM_GATE_ACLK_APM,
|
|
ISP0_GATE_ACLK_FIMC_ISP0,
|
|
ISP0_GATE_PCLK_FIMC_ISP0,
|
|
ISP0_GATE_ACLK_FIMC_TPU,
|
|
ISP0_GATE_PCLK_FIMC_TPU,
|
|
ISP0_GATE_ACLK_SysMMU601,
|
|
ISP0_GATE_CLK_C_TREX_C,
|
|
ISP0_GATE_CLK_AXI_LH_ASYNC_SI_TOP_ISP0,
|
|
ISP0_GATE_PCLK_SYSREG_ISP0,
|
|
ISP0_GATE_PCLK_PMU_ISP0,
|
|
ISP0_GATE_ACLK_XIU_N_ASYNC_MI,
|
|
ISP0_GATE_PCLK_ISP0,
|
|
ISP0_GATE_PCLK_HPM_APBIF_ISP0,
|
|
ISP0_GATE_PCLK_SysMMU601,
|
|
ISP0_GATE_PCLK_TREX_C,
|
|
ISP0_GATE_SCLK_PROMISE_ISP0,
|
|
ISP0_GATE_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D,
|
|
ISP0_LOCAL_GATE_ACLK_FIMC_ISP0,
|
|
ISP0_LOCAL_GATE_PCLK_FIMC_ISP0,
|
|
ISP0_LOCAL_GATE_ACLK_FIMC_TPU,
|
|
ISP0_LOCAL_GATE_PCLK_FIMC_TPU,
|
|
ISP0_LOCAL_GATE_CLK_C_TREX_C,
|
|
ISP0_LOCAL_GATE_PCLK_TREX_C,
|
|
ISP1_GATE_ACLK_XIU_N_ASYNC_SI,
|
|
ISP1_GATE_ACLK_FIMC_ISP1,
|
|
ISP1_GATE_PCLK_SYSREG_ISP1,
|
|
ISP1_GATE_PCLK_PMU_ISP1,
|
|
ISP1_GATE_ACLK_AXI2APB_BRIDGE_IS2P,
|
|
ISP1_GATE_ACLK_XIU_N_ASYNC_MI,
|
|
ISP1_GATE_PCLK_FIMC_ISP1,
|
|
ISP1_GATE_PCLK_HPM_APBIF_ISP1,
|
|
ISP1_GATE_SCLK_PROMISE_ISP1,
|
|
ISP1_LOCAL_GATE_ACLK_FIMC_ISP1,
|
|
ISP1_LOCAL_GATE_PCLK_FIMC_ISP1,
|
|
MFC_GATE_ACLK_ASYNCAPB_MFC,
|
|
MFC_GATE_ACLK_SMMU_MFC_1,
|
|
MFC_GATE_ACLK_SMMU_MFC_0,
|
|
MFC_GATE_ACLK_MFC,
|
|
MFC_GATE_ACLK_PPMU_MFC_1,
|
|
MFC_GATE_ACLK_PPMU_MFC_0,
|
|
MFC_GATE_ACLK_LH_S_MFC_1,
|
|
MFC_GATE_ACLK_LH_S_MFC_0,
|
|
MFC_GATE_ACLK_SFW_MFC_0,
|
|
MFC_GATE_ACLK_SFW_MFC_1,
|
|
MFC_GATE_PCLK_SYSREG_MFC,
|
|
MFC_GATE_PCLK_SMMU_MFC_1,
|
|
MFC_GATE_PCLK_SMMU_MFC_0,
|
|
MFC_GATE_PCLK_PPMU_MFC_1,
|
|
MFC_GATE_PCLK_PPMU_MFC_0,
|
|
MFC_GATE_PCLK_PMU_MFC,
|
|
MFC_GATE_PCLK_CMU_MFC,
|
|
MFC_GATE_PCLK_ASYNCAPB_MFC,
|
|
MFC_GATE_ACLK_AXI2APB_MFCSFR,
|
|
MFC_GATE_ACLK_LH_M_MFC,
|
|
MFC_GATE_PCLK_HPM_APBIF_MFC,
|
|
MFC_GATE_PCLK_SFW_MFC_0,
|
|
MFC_GATE_PCLK_SFW_MFC_1,
|
|
MFC_GATE_SCLK_PROMISE_MFC,
|
|
MIF0_GATE_ACLK_APSCDC,
|
|
MIF0_GATE_ACLK_PPC_DEBUG,
|
|
MIF0_GATE_ACLK_PPC_DVFS,
|
|
MIF0_GATE_ACLK_SMC,
|
|
MIF0_GATE_PCLK_SMC1,
|
|
MIF0_GATE_PCLK_DMC_MISC,
|
|
MIF0_GATE_PCLK_PPC_DEBUG,
|
|
MIF0_GATE_PCLK_PPC_DVFS,
|
|
MIF0_GATE_PCLK_SYSREG_MIF,
|
|
MIF0_GATE_PCLK_HPM,
|
|
MIF0_GATE_ACLK_AXI_ASYNC,
|
|
MIF0_GATE_PCLK_MIFP,
|
|
MIF0_GATE_PCLK_PMU_MIF,
|
|
MIF0_GATE_PCLK_LPDDR4PHY,
|
|
MIF0_GATE_PCLK_SMC2,
|
|
MIF0_GATE_SCLK_PROMISE,
|
|
MIF0_GATE_RCLK_DREX,
|
|
MIF1_GATE_ACLK_APSCDC,
|
|
MIF1_GATE_ACLK_PPC_DEBUG,
|
|
MIF1_GATE_ACLK_PPC_DVFS,
|
|
MIF1_GATE_ACLK_SMC,
|
|
MIF1_GATE_PCLK_SMC1,
|
|
MIF1_GATE_PCLK_DMC_MISC,
|
|
MIF1_GATE_PCLK_PPC_DEBUG,
|
|
MIF1_GATE_PCLK_PPC_DVFS,
|
|
MIF1_GATE_PCLK_SYSREG_MIF,
|
|
MIF1_GATE_PCLK_HPM,
|
|
MIF1_GATE_ACLK_AXI_ASYNC,
|
|
MIF1_GATE_PCLK_MIFP,
|
|
MIF1_GATE_PCLK_PMU_MIF,
|
|
MIF1_GATE_PCLK_LPDDR4PHY,
|
|
MIF1_GATE_PCLK_SMC2,
|
|
MIF1_GATE_SCLK_PROMISE,
|
|
MIF1_GATE_RCLK_DREX,
|
|
MIF2_GATE_ACLK_APSCDC,
|
|
MIF2_GATE_ACLK_PPC_DEBUG,
|
|
MIF2_GATE_ACLK_PPC_DVFS,
|
|
MIF2_GATE_ACLK_SMC,
|
|
MIF2_GATE_PCLK_SMC1,
|
|
MIF2_GATE_PCLK_DMC_MISC,
|
|
MIF2_GATE_PCLK_PPC_DEBUG,
|
|
MIF2_GATE_PCLK_PPC_DVFS,
|
|
MIF2_GATE_PCLK_SYSREG_MIF,
|
|
MIF2_GATE_PCLK_HPM,
|
|
MIF2_GATE_ACLK_AXI_ASYNC,
|
|
MIF2_GATE_PCLK_MIFP,
|
|
MIF2_GATE_PCLK_PMU_MIF,
|
|
MIF2_GATE_PCLK_LPDDR4PHY,
|
|
MIF2_GATE_PCLK_SMC2,
|
|
MIF2_GATE_SCLK_PROMISE,
|
|
MIF2_GATE_RCLK_DREX,
|
|
MIF3_GATE_ACLK_APSCDC,
|
|
MIF3_GATE_ACLK_PPC_DEBUG,
|
|
MIF3_GATE_ACLK_PPC_DVFS,
|
|
MIF3_GATE_ACLK_SMC,
|
|
MIF3_GATE_PCLK_SMC1,
|
|
MIF3_GATE_PCLK_DMC_MISC,
|
|
MIF3_GATE_PCLK_PPC_DEBUG,
|
|
MIF3_GATE_PCLK_PPC_DVFS,
|
|
MIF3_GATE_PCLK_SYSREG_MIF,
|
|
MIF3_GATE_PCLK_HPM,
|
|
MIF3_GATE_ACLK_AXI_ASYNC,
|
|
MIF3_GATE_PCLK_MIFP,
|
|
MIF3_GATE_PCLK_PMU_MIF,
|
|
MIF3_GATE_PCLK_LPDDR4PHY,
|
|
MIF3_GATE_PCLK_SMC2,
|
|
MIF3_GATE_SCLK_PROMISE,
|
|
MIF3_GATE_RCLK_DREX,
|
|
MNGS_GATE_ACLK_ASYNCPACES_MNGS_SCI,
|
|
MNGS_GATE_ATCLKS_ATB_MNGS3_CSSYS,
|
|
MNGS_GATE_ATCLKS_ATB_MNGS2_CSSYS,
|
|
MNGS_GATE_ATCLKS_ATB_MNGS1_CSSYS,
|
|
MNGS_GATE_ATCLKS_ATB_MNGS0_CSSYS,
|
|
MNGS_GATE_ATCLK_XIU_MNGSX_2x1,
|
|
MNGS_GATE_ATCLK_STM_TXACTOR,
|
|
MNGS_GATE_ATCLK_ATB_BDU_CSSYS,
|
|
MNGS_GATE_ATCLK_ATB_AUD_CSSYS,
|
|
MNGS_GATE_ATCLK_ATB_CAM1_CSSYS,
|
|
MNGS_GATE_ATCLK_ATB_APOLLO3_CSSYS,
|
|
MNGS_GATE_ATCLK_ATB_APOLLO2_CSSYS,
|
|
MNGS_GATE_ATCLK_ATB_APOLLO1_CSSYS,
|
|
MNGS_GATE_ATCLK_ATB_APOLLO0_CSSYS,
|
|
MNGS_GATE_ATCLKM_ATB_MNGS3_CSSYS,
|
|
MNGS_GATE_ATCLKM_ATB_MNGS2_CSSYS,
|
|
MNGS_GATE_ATCLKM_ATB_MNGS1_CSSYS,
|
|
MNGS_GATE_ATCLKM_ATB_MNGS0_CSSYS,
|
|
MNGS_GATE_ATCLK_ASYNCAHB_CSSYS_SSS_ACLK,
|
|
MNGS_GATE_ATCLK_ASYNCLHAXI_CSSYS_ETR_ACLK,
|
|
MNGS_GATE_ATCLK_CSSYS_HCLK,
|
|
MNGS_GATE_ATCLK_CSSYS,
|
|
MNGS_GATE_ATCLK_CSSYS_TRACECLK,
|
|
MNGS_GATE_ATCLK_ASYNCATB_CAM1,
|
|
MNGS_GATE_ATCLK_ASYNCATB_AUD,
|
|
MNGS_GATE_PCLKDBG_ASAPBMST_CCORE_CSSYS,
|
|
MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_BDU,
|
|
MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_CAM1,
|
|
MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_AUD,
|
|
MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_APOLLO,
|
|
MNGS_GATE_PCLKDBG_DUMP_PC_MNGS,
|
|
MNGS_GATE_PCLKDBG_SECJTAG,
|
|
MNGS_GATE_PCLKDBG_AXIAP,
|
|
MNGS_GATE_PCLKDBG_CSSYS_CTMCLK,
|
|
MNGS_GATE_PCLKDBG_CSSYS,
|
|
MNGS_GATE_PCLKDBG_MNGS,
|
|
MNGS_GATE_PCLKDBG_ASYNCDAPSLV,
|
|
MNGS_GATE_PCLK_SYSREG_MNGS,
|
|
MNGS_GATE_PCLK_STM_TXACTOR,
|
|
MNGS_GATE_PCLK_XIU_PERI_MNGS_ACLK,
|
|
MNGS_GATE_PCLK_PMU_MNGS,
|
|
MNGS_GATE_PCLK_XIU_MNGSSFRX_1x2,
|
|
MNGS_GATE_PCLK_AXI2APB_MNGS_ACLK,
|
|
MNGS_GATE_PCLK_HPM_MNGS,
|
|
MNGS_GATE_SCLK_MNGS,
|
|
MNGS_GATE_SCLK_PROMISE2_MNGS,
|
|
MNGS_GATE_SCLK_PROMISE1_MNGS,
|
|
MNGS_GATE_SCLK_PROMISE0_MNGS,
|
|
MSCL_GATE_ACLK_ASYNCAPB_JPEG,
|
|
MSCL_GATE_ACLK_PPMU_MSCL_0,
|
|
MSCL_GATE_ACLK_SMMU_JPEG,
|
|
MSCL_GATE_ACLK_SMMU_MSCL_0,
|
|
MSCL_GATE_ACLK_QE_JPEG,
|
|
MSCL_GATE_ACLK_QE_MSCL_0,
|
|
MSCL_GATE_ACLK_XIU_MSCLX_0,
|
|
MSCL_GATE_ACLK_LH_ASYNC_SI_MSCL_0,
|
|
MSCL_GATE_ACLK_JPEG,
|
|
MSCL_GATE_ACLK_MSCL_0,
|
|
MSCL_GATE_ACLK_SFW_MSCL_0,
|
|
MSCL_GATE_ACLK_ASYNCAPB_G2D,
|
|
MSCL_GATE_ACLK_PPMU_MSCL_1,
|
|
MSCL_GATE_ACLK_SMMU_G2D,
|
|
MSCL_GATE_ACLK_SMMU_MSCL_1,
|
|
MSCL_GATE_ACLK_QE_G2D,
|
|
MSCL_GATE_ACLK_QE_MSCL_1,
|
|
MSCL_GATE_ACLK_AXI2ACEL,
|
|
MSCL_GATE_ACLK_XIU_MSCLX_1,
|
|
MSCL_GATE_ACLK_LH_ASYNC_SI_MSCL_1,
|
|
MSCL_GATE_ACLK_G2D,
|
|
MSCL_GATE_ACLK_MSCL_1,
|
|
MSCL_GATE_ACLK_SFW_MSCL_1,
|
|
MSCL_GATE_ACLK_LH_ASYNC_MI_MSCLSFR,
|
|
MSCL_GATE_PCLK_PMU_MSCL,
|
|
MSCL_GATE_PCLK_SYSREG_MSCL,
|
|
MSCL_GATE_PCLK_CMU_MSCL,
|
|
MSCL_GATE_PCLK_PPMU_MSCL_1,
|
|
MSCL_GATE_PCLK_PPMU_MSCL_0,
|
|
MSCL_GATE_PCLK_SMMU_G2D,
|
|
MSCL_GATE_PCLK_SMMU_JPEG,
|
|
MSCL_GATE_PCLK_SMMU_MSCL_1,
|
|
MSCL_GATE_PCLK_SMMU_MSCL_0,
|
|
MSCL_GATE_PCLK_QE_G2D,
|
|
MSCL_GATE_PCLK_QE_JPEG,
|
|
MSCL_GATE_PCLK_QE_MSCL_1,
|
|
MSCL_GATE_PCLK_QE_MSCL_0,
|
|
MSCL_GATE_PCLK_ASYNCAPB_G2D,
|
|
MSCL_GATE_PCLK_ASYNCAPB_JPEG,
|
|
MSCL_GATE_PCLK_MSCL_1,
|
|
MSCL_GATE_PCLK_MSCL_0,
|
|
MSCL_GATE_ACLK_AXI2APB_MSCLSFR_1P,
|
|
MSCL_GATE_ACLK_AXI2APB_MSCLSFR_0P,
|
|
MSCL_GATE_ACLK_XIU_MSCLSFRX,
|
|
MSCL_GATE_PCLK_SFW_MSCL_0,
|
|
MSCL_GATE_PCLK_SFW_MSCL_1,
|
|
PERIC0_GATE_PCLK_HSI2C11,
|
|
PERIC0_GATE_PCLK_HSI2C10,
|
|
PERIC0_GATE_PCLK_HSI2C9,
|
|
PERIC0_GATE_PCLK_HSI2C5,
|
|
PERIC0_GATE_PCLK_HSI2C4,
|
|
PERIC0_GATE_PCLK_HSI2C1,
|
|
PERIC0_GATE_PCLK_HSI2C0,
|
|
PERIC0_GATE_PCLK_PWM,
|
|
PERIC0_GATE_PCLK_ADCIF,
|
|
PERIC0_GATE_PCLK_UART0,
|
|
PERIC0_GATE_PCLK_GPIO_BUS0,
|
|
PERIC0_GATE_PCLK_SYSREG_PERIC0,
|
|
PERIC0_GATE_PCLK_PMU_PERIC0,
|
|
PERIC0_GATE_PCLK_CMU_PERIC0,
|
|
PERIC0_GATE_ACLK_AXI2APB_PERIC0P,
|
|
PERIC0_GATE_ACLK_AXILHASYNCM_PERIC0,
|
|
PERIC0_GATE_SCLK_UART0,
|
|
PERIC0_GATE_SCLK_PWM,
|
|
PERIC1_GATE_PCLK_SPI7,
|
|
PERIC1_GATE_PCLK_SPI6,
|
|
PERIC1_GATE_PCLK_SPI5,
|
|
PERIC1_GATE_PCLK_SPI4,
|
|
PERIC1_GATE_PCLK_SPI3,
|
|
PERIC1_GATE_PCLK_SPI2,
|
|
PERIC1_GATE_PCLK_SPI1,
|
|
PERIC1_GATE_PCLK_SPI0,
|
|
PERIC1_GATE_PCLK_UART5,
|
|
PERIC1_GATE_PCLK_UART4,
|
|
PERIC1_GATE_PCLK_UART3,
|
|
PERIC1_GATE_PCLK_UART2,
|
|
PERIC1_GATE_PCLK_UART1,
|
|
PERIC1_GATE_PCLK_GPIO_ESE,
|
|
PERIC1_GATE_PCLK_GPIO_FF,
|
|
PERIC1_GATE_PCLK_GPIO_TOUCH,
|
|
PERIC1_GATE_PCLK_GPIO_NFC,
|
|
PERIC1_GATE_PCLK_GPIO_PERIC1,
|
|
PERIC1_GATE_PCLK_SYSREG_PERIC1,
|
|
PERIC1_GATE_PCLK_PMU_PERIC1,
|
|
PERIC1_GATE_PCLK_CMU_PERIC1,
|
|
PERIC1_GATE_ACLK_AXI2APB_PERIC1_2P,
|
|
PERIC1_GATE_ACLK_AXI2APB_PERIC1_1P,
|
|
PERIC1_GATE_ACLK_AXI2APB_PERIC1_0P,
|
|
PERIC1_GATE_ACLK_XIU_PERIC1SFRX,
|
|
PERIC1_GATE_ACLK_AXILHASYNCM_PERIC1,
|
|
PERIC1_GATE_PCLK_HSI2C14,
|
|
PERIC1_GATE_PCLK_HSI2C13,
|
|
PERIC1_GATE_PCLK_HSI2C12,
|
|
PERIC1_GATE_PCLK_HSI2C8,
|
|
PERIC1_GATE_PCLK_HSI2C7,
|
|
PERIC1_GATE_PCLK_HSI2C6,
|
|
PERIC1_GATE_PCLK_HSI2C3,
|
|
PERIC1_GATE_PCLK_HSI2C2,
|
|
PERIC1_GATE_SCLK_SPI0,
|
|
PERIC1_GATE_SCLK_SPI1,
|
|
PERIC1_GATE_SCLK_SPI2,
|
|
PERIC1_GATE_SCLK_SPI3,
|
|
PERIC1_GATE_SCLK_SPI4,
|
|
PERIC1_GATE_SCLK_SPI5,
|
|
PERIC1_GATE_SCLK_SPI6,
|
|
PERIC1_GATE_SCLK_SPI7,
|
|
PERIC1_GATE_SCLK_UART1,
|
|
PERIC1_GATE_SCLK_UART2,
|
|
PERIC1_GATE_SCLK_UART3,
|
|
PERIC1_GATE_SCLK_UART4,
|
|
PERIC1_GATE_SCLK_UART5,
|
|
PERIS_GATE_PCLK_SFR_APBIF_HDMI_CEC,
|
|
PERIS_GATE_PCLK_SFR_APBIF_TMU,
|
|
PERIS_GATE_PCLK_RTC_APBIF,
|
|
PERIS_GATE_PCLK_MONOCNT_APBIF,
|
|
PERIS_GATE_PCLK_WDT_APOLLO,
|
|
PERIS_GATE_PCLK_WDT_MNGS,
|
|
PERIS_GATE_PCLK_MCT,
|
|
PERIS_GATE_PCLK_SYSREG_PERIS,
|
|
PERIS_GATE_PCLK_PMU_PERIS,
|
|
PERIS_GATE_PCLK_CMU_PERIS,
|
|
PERIS_GATE_ACLK_AXI2APB_PERIS1,
|
|
PERIS_GATE_ACLK_AXI2APB_PERIS0,
|
|
PERIS_GATE_ACLK_XIU_PERIS,
|
|
PERIS_GATE_ACLK_AXI_LH_ASYNC,
|
|
PERIS_GATE_PCLK_HPM_APBIF_PERIS,
|
|
PERIS_GATE_PCLK_TZPC_15,
|
|
PERIS_GATE_PCLK_TZPC_14,
|
|
PERIS_GATE_PCLK_TZPC_13,
|
|
PERIS_GATE_PCLK_TZPC_12,
|
|
PERIS_GATE_PCLK_TZPC_11,
|
|
PERIS_GATE_PCLK_TZPC_10,
|
|
PERIS_GATE_PCLK_TZPC_9,
|
|
PERIS_GATE_PCLK_TZPC_8,
|
|
PERIS_GATE_PCLK_TZPC_7,
|
|
PERIS_GATE_PCLK_TZPC_6,
|
|
PERIS_GATE_PCLK_TZPC_5,
|
|
PERIS_GATE_PCLK_TZPC_4,
|
|
PERIS_GATE_PCLK_TZPC_3,
|
|
PERIS_GATE_PCLK_TZPC_2,
|
|
PERIS_GATE_PCLK_TZPC_1,
|
|
PERIS_GATE_PCLK_TZPC_0,
|
|
PERIS_GATE_PCLK_TOP_RTC,
|
|
PERIS_GATE_PCLK_SFR_APBIF_CHIPID,
|
|
PERIS_GATE_SCLK_OTP_CON_TOP,
|
|
PERIS_GATE_SCLK_CHIPID,
|
|
PERIS_GATE_SCLK_TMU,
|
|
PERIS_GATE_SCLK_PROMISE_PERIS,
|
|
TOP_GATE_ACLK_CCORE_800,
|
|
TOP_GATE_ACLK_CCORE_264,
|
|
TOP_GATE_ACLK_CCORE_G3D_800,
|
|
TOP_GATE_ACLK_CCORE_528,
|
|
TOP_GATE_ACLK_CCORE_132,
|
|
TOP_GATE_PCLK_CCORE_66,
|
|
TOP_GATE_ACLK_BUS0_528,
|
|
TOP_GATE_ACLK_BUS0_200,
|
|
TOP_GATE_PCLK_BUS0_132,
|
|
TOP_GATE_ACLK_BUS1_528,
|
|
TOP_GATE_PCLK_BUS1_132,
|
|
TOP_GATE_ACLK_DISP0_0_400,
|
|
TOP_GATE_ACLK_DISP0_1_400,
|
|
TOP_GATE_ACLK_DISP1_0_400,
|
|
TOP_GATE_ACLK_DISP1_1_400,
|
|
TOP_GATE_ACLK_MFC_600,
|
|
TOP_GATE_ACLK_MSCL0_528,
|
|
TOP_GATE_ACLK_MSCL1_528,
|
|
TOP_GATE_ACLK_IMEM_266,
|
|
TOP_GATE_ACLK_IMEM_200,
|
|
TOP_GATE_ACLK_IMEM_100,
|
|
TOP_GATE_ACLK_FSYS0_200,
|
|
TOP_GATE_ACLK_FSYS1_200,
|
|
TOP_GATE_ACLK_PERIS_66,
|
|
TOP_GATE_ACLK_PERIC0_66,
|
|
TOP_GATE_ACLK_PERIC1_66,
|
|
TOP_GATE_ACLK_ISP0_ISP0_528,
|
|
TOP_GATE_ACLK_ISP0_TPU_400,
|
|
TOP_GATE_ACLK_ISP0_TREX_528,
|
|
TOP_GATE_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D,
|
|
TOP_GATE_ACLK_ISP1_ISP1_468,
|
|
TOP_GATE_ACLK_CAM0_CSIS0_414,
|
|
TOP_GATE_ACLK_CAM0_CSIS1_168,
|
|
TOP_GATE_ACLK_CAM0_CSIS2_234,
|
|
TOP_GATE_ACLK_CAM0_3AA0_414,
|
|
TOP_GATE_ACLK_CAM0_3AA1_414,
|
|
TOP_GATE_ACLK_CAM0_CSIS3_132,
|
|
TOP_GATE_ACLK_CAM0_TREX_528,
|
|
TOP_GATE_ACLK_CAM1_ARM_672,
|
|
TOP_GATE_ACLK_CAM1_TREX_VRA_528,
|
|
TOP_GATE_ACLK_CAM1_TREX_B_528,
|
|
TOP_GATE_ACLK_CAM1_BUS_264,
|
|
TOP_GATE_ACLK_CAM1_PERI_84,
|
|
TOP_GATE_ACLK_CAM1_CSIS2_414,
|
|
TOP_GATE_ACLK_CAM1_CSIS3_132,
|
|
TOP_GATE_ACLK_CAM1_SCL_566,
|
|
TOP_GATE_SCLK_DISP0_DECON0_ECLK0,
|
|
TOP_GATE_SCLK_DISP0_DECON0_VCLK0,
|
|
TOP_GATE_SCLK_DISP0_DECON0_VCLK1,
|
|
TOP_GATE_SCLK_DISP0_HDMI_AUDIO,
|
|
TOP_GATE_SCLK_DISP1_DECON1_ECLK0,
|
|
TOP_GATE_SCLK_DISP1_DECON1_ECLK1,
|
|
TOP_GATE_SCLK_FSYS0_USBDRD30,
|
|
TOP_GATE_SCLK_FSYS0_MMC0,
|
|
TOP_GATE_SCLK_FSYS0_UFSUNIPRO20,
|
|
TOP_GATE_SCLK_FSYS0_PHY_24M,
|
|
TOP_GATE_SCLK_FSYS0_UFSUNIPRO_CFG,
|
|
TOP_GATE_SCLK_FSYS1_MMC2,
|
|
TOP_GATE_SCLK_FSYS1_UFSUNIPRO20,
|
|
TOP_GATE_SCLK_FSYS1_PCIE_PHY,
|
|
TOP_GATE_SCLK_FSYS1_UFSUNIPRO_CFG,
|
|
TOP_GATE_SCLK_PERIC0_UART0,
|
|
TOP_GATE_SCLK_PERIC1_SPI0,
|
|
TOP_GATE_SCLK_PERIC1_SPI1,
|
|
TOP_GATE_SCLK_PERIC1_SPI2,
|
|
TOP_GATE_SCLK_PERIC1_SPI3,
|
|
TOP_GATE_SCLK_PERIC1_SPI4,
|
|
TOP_GATE_SCLK_PERIC1_SPI5,
|
|
TOP_GATE_SCLK_PERIC1_SPI6,
|
|
TOP_GATE_SCLK_PERIC1_SPI7,
|
|
TOP_GATE_SCLK_PERIC1_UART1,
|
|
TOP_GATE_SCLK_PERIC1_UART2,
|
|
TOP_GATE_SCLK_PERIC1_UART3,
|
|
TOP_GATE_SCLK_PERIC1_UART4,
|
|
TOP_GATE_SCLK_PERIC1_UART5,
|
|
TOP_GATE_SCLK_CAM1_ISP_SPI0,
|
|
TOP_GATE_SCLK_CAM1_ISP_SPI1,
|
|
TOP_GATE_SCLK_CAM1_ISP_UART,
|
|
TOP_GATE_SCLK_AP2CP_MIF_PLL_OUT,
|
|
TOP_GATE_ACLK_PSCDC_400,
|
|
TOP_GATE_SCLK_BUS_PLL_MNGS,
|
|
TOP_GATE_SCLK_BUS_PLL_APOLLO,
|
|
TOP_GATE_SCLK_BUS_PLL_MIF,
|
|
TOP_GATE_SCLK_BUS_PLL_G3D,
|
|
TOP_GATE_SCLK_ISP_SENSOR0,
|
|
TOP_GATE_SCLK_ISP_SENSOR1,
|
|
TOP_GATE_SCLK_ISP_SENSOR2,
|
|
TOP_GATE_SCLK_ISP_SENSOR3,
|
|
TOP_GATE_SCLK_PROMISE_INT,
|
|
TOP_GATE_SCLK_PROMISE_DISP,
|
|
|
|
DISP0_HWACG_DSIM0,
|
|
DISP0_HWACG_DSIM1,
|
|
DISP0_HWACG_DSIM2,
|
|
DISP0_HWACG_HDMI,
|
|
DISP0_HWACG_HDMI_AUDIO,
|
|
DISP0_HWACG_DP,
|
|
DISP0_HWACG_DISP0_MUX,
|
|
DISP0_HWACG_HDMI_PHY,
|
|
DISP0_HWACG_DISP1_400,
|
|
DISP0_HWACG_DECON0,
|
|
DISP0_HWACG_HPM_APBIF_DISP0,
|
|
DISP0_HWACG_PROMISE_DISP0,
|
|
DISP0_HWACG_DPTX_PHY,
|
|
DISP0_HWACG_MIPI_DPHY_M1S0,
|
|
DISP0_HWACG_MIPI_DPHY_M4S0,
|
|
DISP0_HWACG_MIPI_DPHY_M4S4,
|
|
DISP1_HWACG_DECON1_ECLK_0,
|
|
DISP1_HWACG_DECON1_ECLK_1,
|
|
DISP1_HWACG_HPM_APBIF_DISP1,
|
|
DISP1_HWACG_PROMISE_DISP1,
|
|
FSYS0_HWACG_USBDRD30,
|
|
FSYS0_HWACG_QCH_USBDRD30,
|
|
FSYS0_HWACG_UFS_LINK_EMBEDDED,
|
|
FSYS0_HWACG_USBHOST20,
|
|
FSYS0_HWACG_USBHOST20_PHY,
|
|
FSYS0_HWACG_GPIO_FSYS0,
|
|
FSYS0_HWACG_HPM_APBIF_FSYS0,
|
|
FSYS0_HWACG_PROMISE_FSYS0,
|
|
FSYS1_HWACG_SROMC_FSYS1,
|
|
FSYS1_HWACG_GPIO_FSYS1,
|
|
FSYS1_HWACG_HPM_APBIF_FSYS1,
|
|
FSYS1_HWACG_PROMISE_FSYS1,
|
|
FSYS1_HWACG_PCIE_RC_LINK_WIFI0,
|
|
FSYS1_HWACG_PCIE_RC_LINK_WIFI1,
|
|
FSYS1_HWACG_PCIE_PCS_WIFI0,
|
|
FSYS1_HWACG_PCIE_PCS_WIFI1,
|
|
FSYS1_HWACG_PCIE_PHY_FSYS1_WIFI0,
|
|
FSYS1_HWACG_PCIE_PHY_FSYS1_WIFI1,
|
|
FSYS1_HWACG_UFS_LINK_SDCARD,
|
|
IMEM_HWACG_GIC,
|
|
IMEM_HWACG_ASYNCAHBM_SSS_ATLAS,
|
|
MFC_HWACG_HPM_APBIF_MFC,
|
|
MFC_HWACG_PROMISE_MFC,
|
|
PERIC0_HWACG_GPIO_BUS0,
|
|
PERIC0_HWACG_UART0,
|
|
PERIC0_HWACG_ADCIF,
|
|
PERIC0_HWACG_PWM,
|
|
PERIC0_HWACG_HSI2C0,
|
|
PERIC0_HWACG_HSI2C1,
|
|
PERIC0_HWACG_HSI2C4,
|
|
PERIC0_HWACG_HSI2C5,
|
|
PERIC0_HWACG_HSI2C9,
|
|
PERIC0_HWACG_HSI2C10,
|
|
PERIC0_HWACG_HSI2C11,
|
|
PERIC1_HWACG_GPIO_PERIC1,
|
|
PERIC1_HWACG_GPIO_NFC,
|
|
PERIC1_HWACG_GPIO_TOUCH,
|
|
PERIC1_HWACG_GPIO_FF,
|
|
PERIC1_HWACG_GPIO_ESE,
|
|
PERIC1_HWACG_UART1,
|
|
PERIC1_HWACG_UART2,
|
|
PERIC1_HWACG_UART3,
|
|
PERIC1_HWACG_UART4,
|
|
PERIC1_HWACG_UART5,
|
|
PERIC1_HWACG_SPI0,
|
|
PERIC1_HWACG_SPI1,
|
|
PERIC1_HWACG_SPI2,
|
|
PERIC1_HWACG_SPI3,
|
|
PERIC1_HWACG_SPI4,
|
|
PERIC1_HWACG_SPI5,
|
|
PERIC1_HWACG_SPI6,
|
|
PERIC1_HWACG_SPI7,
|
|
PERIC1_HWACG_HSI2C2,
|
|
PERIC1_HWACG_HSI2C3,
|
|
PERIC1_HWACG_HSI2C6,
|
|
PERIC1_HWACG_HSI2C7,
|
|
PERIC1_HWACG_HSI2C8,
|
|
PERIC1_HWACG_HSI2C12,
|
|
PERIC1_HWACG_HSI2C13,
|
|
PERIC1_HWACG_HSI2C14,
|
|
PERIS_HWACG_MCT,
|
|
PERIS_HWACG_WDT_MNGS,
|
|
PERIS_HWACG_WDT_APOLLO,
|
|
PERIS_HWACG_RTC_APBIF,
|
|
PERIS_HWACG_SFR_APBIF_TMU,
|
|
PERIS_HWACG_SFR_APBIF_HDMI_CEC,
|
|
PERIS_HWACG_HPM_APBIF_PERIS,
|
|
PERIS_HWACG_TZPC_0,
|
|
PERIS_HWACG_TZPC_1,
|
|
PERIS_HWACG_TZPC_2,
|
|
PERIS_HWACG_TZPC_3,
|
|
PERIS_HWACG_TZPC_4,
|
|
PERIS_HWACG_TZPC_5,
|
|
PERIS_HWACG_TZPC_6,
|
|
PERIS_HWACG_TZPC_7,
|
|
PERIS_HWACG_TZPC_8,
|
|
PERIS_HWACG_TZPC_9,
|
|
PERIS_HWACG_TZPC_10,
|
|
PERIS_HWACG_TZPC_11,
|
|
PERIS_HWACG_TZPC_12,
|
|
PERIS_HWACG_TZPC_13,
|
|
PERIS_HWACG_TZPC_14,
|
|
PERIS_HWACG_TZPC_15,
|
|
PERIS_HWACG_TOP_RTC,
|
|
PERIS_HWACG_OTP_CON_TOP,
|
|
PERIS_HWACG_SFR_APBIF_CHIPID,
|
|
PERIS_HWACG_TMU,
|
|
PERIS_HWACG_CHIPID,
|
|
PERIS_HWACG_PROMISE_PERIS,
|
|
CLKOUT_OSCCLK_NFC,
|
|
CLKOUT_TCXO_26M,
|
|
CLKOUT_TCXO_IN0,
|
|
CLKOUT_TCXO_IN1,
|
|
CLKOUT_TCXO_IN2,
|
|
CLKOUT_TCXO_IN3,
|
|
CLKOUT_TCXO_IN4,
|
|
CLKOUT_CLKOUT0_DISABLE,
|
|
|
|
NUM_OF_GATE_TYPE = CLKOUT_CLKOUT0_DISABLE - gate_type + 1,
|
|
};
|
|
|
|
FIXEDRATE_EXTERN(OSCCLK)
|
|
FIXEDRATE_EXTERN(OSCCLK_26M)
|
|
FIXEDRATE_EXTERN(SCAN_CLK_OSC)
|
|
FIXEDRATE_EXTERN(I_CP2AP_MIF_CLK)
|
|
FIXEDRATE_EXTERN(OSCCLK_PHY)
|
|
FIXEDRATE_EXTERN(SCLK_CP2AP_AUD_CLK)
|
|
FIXEDRATE_EXTERN(IOCLK_AUDIOCDCLK0)
|
|
FIXEDRATE_EXTERN(IOCLK_SLIMBUS_CLK)
|
|
FIXEDRATE_EXTERN(IOCLK_I2S_BCLK)
|
|
FIXEDRATE_EXTERN(RTC_CLKIN)
|
|
FIXEDRATE_EXTERN(IOCLK_SPI0)
|
|
FIXEDRATE_EXTERN(IOCLK_SPI1)
|
|
FIXEDRATE_EXTERN(IOCLK_SPI2)
|
|
FIXEDRATE_EXTERN(IOCLK_SPI3)
|
|
FIXEDRATE_EXTERN(IOCLK_SPI4)
|
|
FIXEDRATE_EXTERN(IOCLK_SPI5)
|
|
FIXEDRATE_EXTERN(IOCLK_SPI6)
|
|
FIXEDRATE_EXTERN(IOCLK_SPI7)
|
|
FIXEDRATE_EXTERN(PHYCLK_USB30_12MOHCI)
|
|
FIXEDRATE_EXTERN(PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_UFS_TX0_SYMBOL_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_UFS_RX0_SYMBOL_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_UFS_RX_PWM_CLK_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_UFS_TX_PWM_CLK_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_UFS_REFCLK_OUT_SOC_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_USBHOST20_PHYCLOCK_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_USBHOST20_FREECLK_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_USBHOST20_CLK48MOHCI_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_UFS_LINK_SDCARD_TX1_SYMBOL_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_UFS_LINK_SDCARD_RX1_SYMBOL_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_UFS_LINK_SDCARD_RX_PWM_CLK_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_UFS_LINK_SDCARD_TX_PWM_CLK_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_UFS_LINK_SDCARD_REFCLK_OUT_SOC_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_PCIE_WIFI0_TX0_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_PCIE_WIFI0_RX0_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_PCIE_WIFI1_TX0_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_PCIE_WIFI1_RX0_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_PCIE_WIFI0_DIG_REFCLK_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_PCIE_WIFI1_DIG_REFCLK_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_MIPIDPHY0_BITCLKDIV2_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_MIPIDPHY1_BITCLKDIV2_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_MIPIDPHY2_BITCLKDIV2_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_HDMIPHY_PIXEL_CLKO_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_HDMIPHY_TMDS_CLKO_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_MIPIDPHY0_RXCLKESC0_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_MIPIDPHY1_RXCLKESC0_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_MIPIDPHY1_BITCLKDIV8_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_MIPIDPHY2_RXCLKESC0_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_MIPIDPHY2_BITCLKDIV8_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_DPPHY_CH0_TXD_CLK_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_DPPHY_CH1_TXD_CLK_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_DPPHY_CH2_TXD_CLK_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_DPPHY_CH3_TXD_CLK_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_PHY)
|
|
FIXEDRATE_EXTERN(PHYCLK_RXBYTECLKHS0_CSIS0)
|
|
FIXEDRATE_EXTERN(PHYCLK_RXBYTECLKHS1_CSIS0)
|
|
FIXEDRATE_EXTERN(PHYCLK_RXBYTECLKHS2_CSIS0)
|
|
FIXEDRATE_EXTERN(PHYCLK_RXBYTECLKHS3_CSIS0)
|
|
FIXEDRATE_EXTERN(PHYCLK_RXBYTECLKHS0_CSIS1)
|
|
FIXEDRATE_EXTERN(PHYCLK_RXBYTECLKHS1_CSIS1)
|
|
FIXEDRATE_EXTERN(PHYCLK_RXBYTECLKHS0_CSIS2)
|
|
FIXEDRATE_EXTERN(PHYCLK_RXBYTECLKHS1_CSIS2)
|
|
FIXEDRATE_EXTERN(PHYCLK_RXBYTECLKHS2_CSIS2)
|
|
FIXEDRATE_EXTERN(PHYCLK_RXBYTECLKHS3_CSIS2)
|
|
FIXEDRATE_EXTERN(PHYCLK_RXBYTECLKHS0_CSIS3)
|
|
|
|
|
|
FIXEDFACTOR_EXTERN(TOP_FF_BUS0_PLL_DIV2)
|
|
FIXEDFACTOR_EXTERN(TOP_FF_BUS1_PLL_DIV2)
|
|
FIXEDFACTOR_EXTERN(TOP_FF_BUS2_PLL_DIV2)
|
|
FIXEDFACTOR_EXTERN(TOP_FF_BUS3_PLL_DIV2)
|
|
FIXEDFACTOR_EXTERN(TOP_FF_BUS3_PLL_DIV4)
|
|
FIXEDFACTOR_EXTERN(TOP_FF_MFC_PLL_DIV2)
|
|
FIXEDFACTOR_EXTERN(TOP_FF_ISP_PLL_DIV2)
|
|
FIXEDFACTOR_EXTERN(MIF0_FF_ACLK_MIF_PLL_DIV2)
|
|
FIXEDFACTOR_EXTERN(MIF0_FF_ACLK_MIF_PLL_DIV4)
|
|
FIXEDFACTOR_EXTERN(MIF1_FF_ACLK_MIF_PLL_DIV2)
|
|
FIXEDFACTOR_EXTERN(MIF1_FF_ACLK_MIF_PLL_DIV4)
|
|
FIXEDFACTOR_EXTERN(MIF2_FF_ACLK_MIF_PLL_DIV2)
|
|
FIXEDFACTOR_EXTERN(MIF2_FF_ACLK_MIF_PLL_DIV4)
|
|
FIXEDFACTOR_EXTERN(MIF3_FF_ACLK_MIF_PLL_DIV2)
|
|
FIXEDFACTOR_EXTERN(MIF3_FF_ACLK_MIF_PLL_DIV4)
|
|
FIXEDFACTOR_EXTERN(U_DFI_CLK_GEN_MIF0)
|
|
FIXEDFACTOR_EXTERN(U_DFI_CLK_GEN_MIF1)
|
|
FIXEDFACTOR_EXTERN(U_DFI_CLK_GEN_MIF2)
|
|
FIXEDFACTOR_EXTERN(U_DFI_CLK_GEN_MIF3)
|
|
|
|
|
|
PLL_EXTERN(MNGS_PLL)
|
|
PLL_EXTERN(APOLLO_PLL)
|
|
PLL_EXTERN(G3D_PLL)
|
|
PLL_EXTERN(MIF_PLL)
|
|
PLL_EXTERN(BUS0_PLL)
|
|
PLL_EXTERN(BUS1_PLL)
|
|
PLL_EXTERN(BUS2_PLL)
|
|
PLL_EXTERN(BUS3_PLL)
|
|
PLL_EXTERN(MFC_PLL)
|
|
PLL_EXTERN(ISP_PLL)
|
|
PLL_EXTERN(DISP_PLL)
|
|
PLL_EXTERN(AUD_PLL)
|
|
PLL_EXTERN(PCIE_PLL)
|
|
|
|
MUX_EXTERN(APOLLO_MUX_APOLLO_PLL)
|
|
MUX_EXTERN(APOLLO_MUX_BUS_PLL_APOLLO_USER)
|
|
MUX_EXTERN(APOLLO_MUX_APOLLO)
|
|
MUX_EXTERN(AUD_MUX_AUD_PLL_USER)
|
|
MUX_EXTERN(AUD_MUX_SCLK_I2S)
|
|
MUX_EXTERN(AUD_MUX_SCLK_PCM)
|
|
MUX_EXTERN(AUD_MUX_CP2AP_AUD_CLK_USER)
|
|
MUX_EXTERN(AUD_MUX_ACLK_CA5)
|
|
MUX_EXTERN(AUD_MUX_CDCLK_AUD)
|
|
MUX_EXTERN(BUS0_MUX_ACLK_BUS0_528_USER)
|
|
MUX_EXTERN(BUS0_MUX_ACLK_BUS0_200_USER)
|
|
MUX_EXTERN(BUS0_MUX_PCLK_BUS0_132_USER)
|
|
MUX_EXTERN(BUS1_MUX_ACLK_BUS1_528_USER)
|
|
MUX_EXTERN(BUS1_MUX_PCLK_BUS1_132_USER)
|
|
MUX_EXTERN(CAM0_MUX_ACLK_CAM0_CSIS0_414_USER)
|
|
MUX_EXTERN(CAM0_MUX_ACLK_CAM0_CSIS1_168_USER)
|
|
MUX_EXTERN(CAM0_MUX_ACLK_CAM0_CSIS2_234_USER)
|
|
MUX_EXTERN(CAM0_MUX_ACLK_CAM0_CSIS3_132_USER)
|
|
MUX_EXTERN(CAM0_MUX_ACLK_CAM0_3AA0_414_USER)
|
|
MUX_EXTERN(CAM0_MUX_ACLK_CAM0_3AA1_414_USER)
|
|
MUX_EXTERN(CAM0_MUX_ACLK_CAM0_TREX_528_USER)
|
|
MUX_EXTERN(CAM0_MUX_PHYCLK_RXBYTECLKHS0_CSIS0_USER)
|
|
MUX_EXTERN(CAM0_MUX_PHYCLK_RXBYTECLKHS1_CSIS0_USER)
|
|
MUX_EXTERN(CAM0_MUX_PHYCLK_RXBYTECLKHS2_CSIS0_USER)
|
|
MUX_EXTERN(CAM0_MUX_PHYCLK_RXBYTECLKHS3_CSIS0_USER)
|
|
MUX_EXTERN(CAM0_MUX_PHYCLK_RXBYTECLKHS0_CSIS1_USER)
|
|
MUX_EXTERN(CAM0_MUX_PHYCLK_RXBYTECLKHS1_CSIS1_USER)
|
|
MUX_EXTERN(CAM1_MUX_ACLK_CAM1_ARM_672_USER)
|
|
MUX_EXTERN(CAM1_MUX_ACLK_CAM1_TREX_VRA_528_USER)
|
|
MUX_EXTERN(CAM1_MUX_ACLK_CAM1_TREX_B_528_USER)
|
|
MUX_EXTERN(CAM1_MUX_ACLK_CAM1_BUS_264_USER)
|
|
MUX_EXTERN(CAM1_MUX_ACLK_CAM1_PERI_84_USER)
|
|
MUX_EXTERN(CAM1_MUX_ACLK_CAM1_CSIS2_414_USER)
|
|
MUX_EXTERN(CAM1_MUX_ACLK_CAM1_CSIS3_132_USER)
|
|
MUX_EXTERN(CAM1_MUX_ACLK_CAM1_SCL_566_USER)
|
|
MUX_EXTERN(CAM1_MUX_SCLK_CAM1_ISP_SPI0_USER)
|
|
MUX_EXTERN(CAM1_MUX_SCLK_CAM1_ISP_SPI1_USER)
|
|
MUX_EXTERN(CAM1_MUX_SCLK_CAM1_ISP_UART_USER)
|
|
MUX_EXTERN(CAM1_MUX_PHYCLK_RXBYTECLKHS0_CSIS2_USER)
|
|
MUX_EXTERN(CAM1_MUX_PHYCLK_RXBYTECLKHS1_CSIS2_USER)
|
|
MUX_EXTERN(CAM1_MUX_PHYCLK_RXBYTECLKHS2_CSIS2_USER)
|
|
MUX_EXTERN(CAM1_MUX_PHYCLK_RXBYTECLKHS3_CSIS2_USER)
|
|
MUX_EXTERN(CAM1_MUX_PHYCLK_RXBYTECLKHS0_CSIS3_USER)
|
|
MUX_EXTERN(CCORE_MUX_ACLK_CCORE_800_USER)
|
|
MUX_EXTERN(CCORE_MUX_ACLK_CCORE_264_USER)
|
|
MUX_EXTERN(CCORE_MUX_ACLK_CCORE_G3D_800_USER)
|
|
MUX_EXTERN(CCORE_MUX_ACLK_CCORE_528_USER)
|
|
MUX_EXTERN(CCORE_MUX_ACLK_CCORE_132_USER)
|
|
MUX_EXTERN(CCORE_MUX_PCLK_CCORE_66_USER)
|
|
MUX_EXTERN(DISP0_MUX_DISP_PLL)
|
|
MUX_EXTERN(DISP0_MUX_ACLK_DISP0_0_400_USER)
|
|
MUX_EXTERN(DISP0_MUX_ACLK_DISP0_1_400_USER)
|
|
MUX_EXTERN(DISP0_MUX_SCLK_DISP0_DECON0_ECLK0_USER)
|
|
MUX_EXTERN(DISP0_MUX_SCLK_DISP0_DECON0_VCLK0_USER)
|
|
MUX_EXTERN(DISP0_MUX_SCLK_DISP0_DECON0_VCLK1_USER)
|
|
MUX_EXTERN(DISP0_MUX_SCLK_DISP0_HDMI_AUDIO_USER)
|
|
MUX_EXTERN(DISP0_MUX_PHYCLK_HDMIPHY_PIXEL_CLKO_USER)
|
|
MUX_EXTERN(DISP0_MUX_PHYCLK_HDMIPHY_TMDS_CLKO_USER)
|
|
MUX_EXTERN(DISP0_MUX_PHYCLK_MIPIDPHY0_RXCLKESC0_USER)
|
|
MUX_EXTERN(DISP0_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER)
|
|
MUX_EXTERN(DISP0_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER)
|
|
MUX_EXTERN(DISP0_MUX_PHYCLK_MIPIDPHY1_RXCLKESC0_USER)
|
|
MUX_EXTERN(DISP0_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER)
|
|
MUX_EXTERN(DISP0_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER)
|
|
MUX_EXTERN(DISP0_MUX_PHYCLK_MIPIDPHY2_RXCLKESC0_USER)
|
|
MUX_EXTERN(DISP0_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER)
|
|
MUX_EXTERN(DISP0_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV8_USER)
|
|
MUX_EXTERN(DISP0_MUX_PHYCLK_DPPHY_CH0_TXD_CLK_USER)
|
|
MUX_EXTERN(DISP0_MUX_PHYCLK_DPPHY_CH1_TXD_CLK_USER)
|
|
MUX_EXTERN(DISP0_MUX_PHYCLK_DPPHY_CH2_TXD_CLK_USER)
|
|
MUX_EXTERN(DISP0_MUX_PHYCLK_DPPHY_CH3_TXD_CLK_USER)
|
|
MUX_EXTERN(DISP0_MUX_ACLK_DISP0_1_400)
|
|
MUX_EXTERN(DISP0_MUX_SCLK_DISP0_DECON0_ECLK0)
|
|
MUX_EXTERN(DISP0_MUX_SCLK_DISP0_DECON0_VCLK0)
|
|
MUX_EXTERN(DISP0_MUX_SCLK_DISP0_DECON0_VCLK1)
|
|
MUX_EXTERN(DISP0_MUX_SCLK_DISP0_HDMI_AUDIO)
|
|
MUX_EXTERN(DISP1_MUX_ACLK_DISP1_0_400_USER)
|
|
MUX_EXTERN(DISP1_MUX_ACLK_DISP1_1_400_USER)
|
|
MUX_EXTERN(DISP1_MUX_SCLK_DISP1_DECON1_ECLK0_USER)
|
|
MUX_EXTERN(DISP1_MUX_SCLK_DISP1_DECON1_ECLK1_USER)
|
|
MUX_EXTERN(DISP1_MUX_SCLK_DISP1_600_USER)
|
|
MUX_EXTERN(DISP1_MUX_PHYCLK_MIPIDPHY0_BITCLKDIV2_USER)
|
|
MUX_EXTERN(DISP1_MUX_PHYCLK_MIPIDPHY1_BITCLKDIV2_USER)
|
|
MUX_EXTERN(DISP1_MUX_PHYCLK_MIPIDPHY2_BITCLKDIV2_USER)
|
|
MUX_EXTERN(DISP1_MUX_PHYCLK_DISP1_HDMIPHY_PIXEL_CLKO_USER)
|
|
MUX_EXTERN(DISP1_MUX_ACLK_DISP1_1_400)
|
|
MUX_EXTERN(DISP1_MUX_SCLK_DISP1_DECON1_ECLK0)
|
|
MUX_EXTERN(DISP1_MUX_SCLK_DISP1_DECON1_ECLK1)
|
|
MUX_EXTERN(DISP1_MUX_SCLK_DECON1_ECLK1)
|
|
MUX_EXTERN(FSYS0_MUX_ACLK_FSYS0_200_USER)
|
|
MUX_EXTERN(FSYS0_MUX_SCLK_FSYS0_USBDRD30_USER)
|
|
MUX_EXTERN(FSYS0_MUX_SCLK_FSYS0_MMC0_USER)
|
|
MUX_EXTERN(FSYS0_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_USER)
|
|
MUX_EXTERN(FSYS0_MUX_SCLK_FSYS0_24M_USER)
|
|
MUX_EXTERN(FSYS0_MUX_SCLK_FSYS0_UFSUNIPRO_EMBEDDED_CFG_USER)
|
|
MUX_EXTERN(FSYS0_MUX_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER)
|
|
MUX_EXTERN(FSYS0_MUX_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER)
|
|
MUX_EXTERN(FSYS0_MUX_PHYCLK_UFS_TX0_SYMBOL_USER)
|
|
MUX_EXTERN(FSYS0_MUX_PHYCLK_UFS_RX0_SYMBOL_USER)
|
|
MUX_EXTERN(FSYS0_MUX_PHYCLK_USBHOST20_PHYCLOCK_USER)
|
|
MUX_EXTERN(FSYS0_MUX_PHYCLK_USBHOST20PHY_REF_CLK)
|
|
MUX_EXTERN(FSYS1_MUX_ACLK_FSYS1_200_USER)
|
|
MUX_EXTERN(FSYS1_MUX_SCLK_FSYS1_MMC2_USER)
|
|
MUX_EXTERN(FSYS1_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_USER)
|
|
MUX_EXTERN(FSYS1_MUX_SCLK_FSYS1_UFSUNIPRO_SDCARD_CFG_USER)
|
|
MUX_EXTERN(FSYS1_MUX_SCLK_FSYS1_PCIE_PHY_USER)
|
|
MUX_EXTERN(FSYS1_MUX_PCIE_PLL)
|
|
MUX_EXTERN(FSYS1_MUX_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL_USER)
|
|
MUX_EXTERN(FSYS1_MUX_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL_USER)
|
|
MUX_EXTERN(FSYS1_MUX_PHYCLK_PCIE_WIFI0_TX0_USER)
|
|
MUX_EXTERN(FSYS1_MUX_PHYCLK_PCIE_WIFI0_RX0_USER)
|
|
MUX_EXTERN(FSYS1_MUX_PHYCLK_PCIE_WIFI1_TX0_USER)
|
|
MUX_EXTERN(FSYS1_MUX_PHYCLK_PCIE_WIFI1_RX0_USER)
|
|
MUX_EXTERN(FSYS1_MUX_PHYCLK_PCIE_WIFI0_DIG_REFCLK_USER)
|
|
MUX_EXTERN(FSYS1_MUX_PHYCLK_PCIE_WIFI1_DIG_REFCLK_USER)
|
|
MUX_EXTERN(G3D_MUX_G3D_PLL_USER)
|
|
MUX_EXTERN(G3D_MUX_BUS_PLL_USER)
|
|
MUX_EXTERN(G3D_MUX_G3D)
|
|
MUX_EXTERN(IMEM_MUX_ACLK_IMEM_266_USER)
|
|
MUX_EXTERN(IMEM_MUX_ACLK_IMEM_200_USER)
|
|
MUX_EXTERN(IMEM_MUX_ACLK_IMEM_100_USER)
|
|
MUX_EXTERN(ISP0_MUX_ACLK_ISP0_528_USER)
|
|
MUX_EXTERN(ISP0_MUX_ACLK_ISP0_TPU_400_USER)
|
|
MUX_EXTERN(ISP0_MUX_ACLK_ISP0_TREX_528_USER)
|
|
MUX_EXTERN(ISP0_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D_USER)
|
|
MUX_EXTERN(ISP1_MUX_ACLK_ISP1_468_USER)
|
|
MUX_EXTERN(MFC_MUX_ACLK_MFC_600_USER)
|
|
MUX_EXTERN(MIF0_MUX_MIF_PLL)
|
|
MUX_EXTERN(MIF0_MUX_BUS_PLL_USER)
|
|
MUX_EXTERN(MIF0_MUX_ACLK_MIF_PLL)
|
|
MUX_EXTERN(MIF0_MUX_PCLK_MIF)
|
|
MUX_EXTERN(MIF0_MUX_SCLK_HPM_MIF)
|
|
MUX_EXTERN(MIF1_MUX_MIF_PLL)
|
|
MUX_EXTERN(MIF1_MUX_BUS_PLL_USER)
|
|
MUX_EXTERN(MIF1_MUX_ACLK_MIF_PLL)
|
|
MUX_EXTERN(MIF1_MUX_PCLK_MIF)
|
|
MUX_EXTERN(MIF1_MUX_SCLK_HPM_MIF)
|
|
MUX_EXTERN(MIF2_MUX_MIF_PLL)
|
|
MUX_EXTERN(MIF2_MUX_BUS_PLL_USER)
|
|
MUX_EXTERN(MIF2_MUX_ACLK_MIF_PLL)
|
|
MUX_EXTERN(MIF2_MUX_PCLK_MIF)
|
|
MUX_EXTERN(MIF2_MUX_SCLK_HPM_MIF)
|
|
MUX_EXTERN(MIF3_MUX_MIF_PLL)
|
|
MUX_EXTERN(MIF3_MUX_BUS_PLL_USER)
|
|
MUX_EXTERN(MIF3_MUX_ACLK_MIF_PLL)
|
|
MUX_EXTERN(MIF3_MUX_PCLK_MIF)
|
|
MUX_EXTERN(MIF3_MUX_SCLK_HPM_MIF)
|
|
MUX_EXTERN(MIF0_MUX_PCLK_SMC)
|
|
MUX_EXTERN(MIF1_MUX_PCLK_SMC)
|
|
MUX_EXTERN(MIF2_MUX_PCLK_SMC)
|
|
MUX_EXTERN(MIF3_MUX_PCLK_SMC)
|
|
MUX_EXTERN(MNGS_MUX_MNGS_PLL)
|
|
MUX_EXTERN(MNGS_MUX_BUS_PLL_MNGS_USER)
|
|
MUX_EXTERN(MNGS_MUX_MNGS)
|
|
MUX_EXTERN(MSCL_MUX_ACLK_MSCL0_528_USER)
|
|
MUX_EXTERN(MSCL_MUX_ACLK_MSCL1_528_USER)
|
|
MUX_EXTERN(MSCL_MUX_ACLK_MSCL1_528)
|
|
MUX_EXTERN(PERIC0_MUX_ACLK_PERIC0_66_USER)
|
|
MUX_EXTERN(PERIC0_MUX_SCLK_UART0_USER)
|
|
MUX_EXTERN(PERIC1_MUX_ACLK_PERIC1_66_USER)
|
|
MUX_EXTERN(PERIC1_MUX_SCLK_SPI0_USER)
|
|
MUX_EXTERN(PERIC1_MUX_SCLK_SPI1_USER)
|
|
MUX_EXTERN(PERIC1_MUX_SCLK_SPI2_USER)
|
|
MUX_EXTERN(PERIC1_MUX_SCLK_SPI3_USER)
|
|
MUX_EXTERN(PERIC1_MUX_SCLK_SPI4_USER)
|
|
MUX_EXTERN(PERIC1_MUX_SCLK_SPI5_USER)
|
|
MUX_EXTERN(PERIC1_MUX_SCLK_SPI6_USER)
|
|
MUX_EXTERN(PERIC1_MUX_SCLK_SPI7_USER)
|
|
MUX_EXTERN(PERIC1_MUX_SCLK_UART1_USER)
|
|
MUX_EXTERN(PERIC1_MUX_SCLK_UART2_USER)
|
|
MUX_EXTERN(PERIC1_MUX_SCLK_UART3_USER)
|
|
MUX_EXTERN(PERIC1_MUX_SCLK_UART4_USER)
|
|
MUX_EXTERN(PERIC1_MUX_SCLK_UART5_USER)
|
|
MUX_EXTERN(PERIS_MUX_ACLK_PERIS_66_USER)
|
|
MUX_EXTERN(TOP_MUX_BUS0_PLL)
|
|
MUX_EXTERN(TOP_MUX_BUS1_PLL)
|
|
MUX_EXTERN(TOP_MUX_BUS2_PLL)
|
|
MUX_EXTERN(TOP_MUX_BUS3_PLL)
|
|
MUX_EXTERN(TOP_MUX_MFC_PLL)
|
|
MUX_EXTERN(TOP_MUX_ISP_PLL)
|
|
MUX_EXTERN(TOP_MUX_AUD_PLL)
|
|
MUX_EXTERN(TOP_MUX_G3D_PLL)
|
|
MUX_EXTERN(TOP_MUX_SCLK_BUS0_PLL)
|
|
MUX_EXTERN(TOP_MUX_SCLK_BUS1_PLL)
|
|
MUX_EXTERN(TOP_MUX_SCLK_BUS2_PLL)
|
|
MUX_EXTERN(TOP_MUX_SCLK_BUS3_PLL)
|
|
MUX_EXTERN(TOP_MUX_SCLK_MFC_PLL)
|
|
MUX_EXTERN(TOP_MUX_SCLK_ISP_PLL)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CCORE_800)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CCORE_264)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CCORE_G3D_800)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CCORE_528)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CCORE_132)
|
|
MUX_EXTERN(TOP_MUX_PCLK_CCORE_66)
|
|
MUX_EXTERN(TOP_MUX_ACLK_BUS0_528)
|
|
MUX_EXTERN(TOP_MUX_ACLK_BUS0_200)
|
|
MUX_EXTERN(TOP_MUX_PCLK_BUS0_132)
|
|
MUX_EXTERN(TOP_MUX_ACLK_BUS1_528)
|
|
MUX_EXTERN(TOP_MUX_PCLK_BUS1_132)
|
|
MUX_EXTERN(TOP_MUX_ACLK_DISP0_0_400)
|
|
MUX_EXTERN(TOP_MUX_ACLK_DISP0_1_400)
|
|
MUX_EXTERN(TOP_MUX_ACLK_DISP1_0_400)
|
|
MUX_EXTERN(TOP_MUX_ACLK_DISP1_1_400)
|
|
MUX_EXTERN(TOP_MUX_ACLK_MFC_600)
|
|
MUX_EXTERN(TOP_MUX_ACLK_MSCL0_528)
|
|
MUX_EXTERN(TOP_MUX_ACLK_MSCL1_528)
|
|
MUX_EXTERN(TOP_MUX_ACLK_IMEM_266)
|
|
MUX_EXTERN(TOP_MUX_ACLK_IMEM_200)
|
|
MUX_EXTERN(TOP_MUX_ACLK_IMEM_100)
|
|
MUX_EXTERN(TOP_MUX_ACLK_FSYS0_200)
|
|
MUX_EXTERN(TOP_MUX_ACLK_FSYS1_200)
|
|
MUX_EXTERN(TOP_MUX_ACLK_PERIS_66)
|
|
MUX_EXTERN(TOP_MUX_ACLK_PERIC0_66)
|
|
MUX_EXTERN(TOP_MUX_ACLK_PERIC1_66)
|
|
MUX_EXTERN(TOP_MUX_ACLK_ISP0_ISP0_528)
|
|
MUX_EXTERN(TOP_MUX_ACLK_ISP0_TPU_400)
|
|
MUX_EXTERN(TOP_MUX_ACLK_ISP0_TREX_528)
|
|
MUX_EXTERN(TOP_MUX_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D)
|
|
MUX_EXTERN(TOP_MUX_ACLK_ISP1_ISP1_468)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CAM0_CSIS0_414)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CAM0_CSIS1_168)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CAM0_CSIS2_234)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CAM0_3AA0_414)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CAM0_3AA1_414)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CAM0_CSIS3_132)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CAM0_TREX_528)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CAM1_ARM_672)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CAM1_TREX_VRA_528)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CAM1_TREX_B_528)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CAM1_BUS_264)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CAM1_PERI_84)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CAM1_CSIS2_414)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CAM1_CSIS3_132)
|
|
MUX_EXTERN(TOP_MUX_ACLK_CAM1_SCL_566)
|
|
MUX_EXTERN(TOP_MUX_SCLK_DISP0_DECON0_ECLK0)
|
|
MUX_EXTERN(TOP_MUX_SCLK_DISP0_DECON0_VCLK0)
|
|
MUX_EXTERN(TOP_MUX_SCLK_DISP0_DECON0_VCLK1)
|
|
MUX_EXTERN(TOP_MUX_SCLK_DISP0_HDMI_AUDIO)
|
|
MUX_EXTERN(TOP_MUX_SCLK_DISP1_DECON1_ECLK0)
|
|
MUX_EXTERN(TOP_MUX_SCLK_DISP1_DECON1_ECLK1)
|
|
MUX_EXTERN(TOP_MUX_SCLK_FSYS0_USBDRD30)
|
|
MUX_EXTERN(TOP_MUX_SCLK_FSYS0_MMC0)
|
|
MUX_EXTERN(TOP_MUX_SCLK_FSYS0_UFSUNIPRO20)
|
|
MUX_EXTERN(TOP_MUX_SCLK_FSYS0_PHY_24M)
|
|
MUX_EXTERN(TOP_MUX_SCLK_FSYS0_UFSUNIPRO_CFG)
|
|
MUX_EXTERN(TOP_MUX_SCLK_FSYS1_MMC2)
|
|
MUX_EXTERN(TOP_MUX_SCLK_FSYS1_UFSUNIPRO20)
|
|
MUX_EXTERN(TOP_MUX_SCLK_FSYS1_PCIE_PHY)
|
|
MUX_EXTERN(TOP_MUX_SCLK_FSYS1_UFSUNIPRO_CFG)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PERIC0_UART0)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PERIC1_SPI0)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PERIC1_SPI1)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PERIC1_SPI2)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PERIC1_SPI3)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PERIC1_SPI4)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PERIC1_SPI5)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PERIC1_SPI6)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PERIC1_SPI7)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PERIC1_UART1)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PERIC1_UART2)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PERIC1_UART3)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PERIC1_UART4)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PERIC1_UART5)
|
|
MUX_EXTERN(TOP_MUX_SCLK_CAM1_ISP_SPI0)
|
|
MUX_EXTERN(TOP_MUX_SCLK_CAM1_ISP_SPI1)
|
|
MUX_EXTERN(TOP_MUX_SCLK_CAM1_ISP_UART)
|
|
MUX_EXTERN(TOP_MUX_SCLK_AP2CP_MIF_PLL_OUT)
|
|
MUX_EXTERN(TOP_MUX_ACLK_PSCDC_400)
|
|
MUX_EXTERN(TOP_MUX_SCLK_BUS_PLL_MNGS)
|
|
MUX_EXTERN(TOP_MUX_SCLK_BUS_PLL_APOLLO)
|
|
MUX_EXTERN(TOP_MUX_SCLK_BUS_PLL_MIF)
|
|
MUX_EXTERN(TOP_MUX_SCLK_BUS_PLL_G3D)
|
|
MUX_EXTERN(TOP_MUX_SCLK_ISP_SENSOR0)
|
|
MUX_EXTERN(TOP_MUX_SCLK_ISP_SENSOR1)
|
|
MUX_EXTERN(TOP_MUX_SCLK_ISP_SENSOR2)
|
|
MUX_EXTERN(TOP_MUX_SCLK_ISP_SENSOR3)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PROMISE_INT)
|
|
MUX_EXTERN(TOP_MUX_SCLK_PROMISE_DISP)
|
|
MUX_EXTERN(TOP_MUX_CP2AP_MIF_CLK_USER)
|
|
MUX_EXTERN(TOP_MUX_MIF_PLL)
|
|
MUX_EXTERN(TOP_MUX_BUS_PLL_MIF)
|
|
MUX_EXTERN(TOP_MUX_ACLK_MIF_PLL)
|
|
|
|
|
|
DIV_EXTERN(APOLLO_DIV_APOLLO)
|
|
DIV_EXTERN(APOLLO_DIV_ACLK_APOLLO)
|
|
DIV_EXTERN(APOLLO_DIV_ATCLK_APOLLO)
|
|
DIV_EXTERN(APOLLO_DIV_PCLK_DBG_APOLLO)
|
|
DIV_EXTERN(APOLLO_DIV_PCLK_APOLLO)
|
|
DIV_EXTERN(APOLLO_DIV_CNTCLK_APOLLO)
|
|
DIV_EXTERN(APOLLO_DIV_APOLLO_RUN_MONITOR)
|
|
DIV_EXTERN(APOLLO_DIV_SCLK_PROMISE_APOLLO)
|
|
DIV_EXTERN(APOLLO_DIV_APOLLO_PLL)
|
|
DIV_EXTERN(AUD_DIV_AUD_CA5)
|
|
DIV_EXTERN(AUD_DIV_ACLK_AUD)
|
|
DIV_EXTERN(AUD_DIV_PCLK_DBG)
|
|
DIV_EXTERN(AUD_DIV_ATCLK_AUD)
|
|
DIV_EXTERN(AUD_DIV_AUD_CDCLK)
|
|
DIV_EXTERN(AUD_DIV_SCLK_I2S)
|
|
DIV_EXTERN(AUD_DIV_SCLK_PCM)
|
|
DIV_EXTERN(AUD_DIV_SCLK_SLIMBUS)
|
|
DIV_EXTERN(AUD_DIV_SCLK_CP_I2S)
|
|
DIV_EXTERN(AUD_DIV_SCLK_ASRC)
|
|
DIV_EXTERN(AUD_DIV_CP_CA5)
|
|
DIV_EXTERN(AUD_DIV_CP_CDCLK)
|
|
DIV_EXTERN(CAM0_DIV_PCLK_CAM0_CSIS0_207)
|
|
DIV_EXTERN(CAM0_DIV_PCLK_CAM0_3AA0_207)
|
|
DIV_EXTERN(CAM0_DIV_PCLK_CAM0_3AA1_207)
|
|
DIV_EXTERN(CAM0_DIV_PCLK_CAM0_TREX_264)
|
|
DIV_EXTERN(CAM0_DIV_PCLK_CAM0_TREX_132)
|
|
DIV_EXTERN(CAM1_DIV_PCLK_CAM1_ARM_168)
|
|
DIV_EXTERN(CAM1_DIV_PCLK_CAM1_TREX_VRA_264)
|
|
DIV_EXTERN(CAM1_DIV_PCLK_CAM1_BUS_132)
|
|
DIV_EXTERN(CCORE_DIV_SCLK_HPM_CCORE)
|
|
DIV_EXTERN(DISP0_DIV_PCLK_DISP0_0_133)
|
|
DIV_EXTERN(DISP0_DIV_SCLK_DECON0_ECLK0)
|
|
DIV_EXTERN(DISP0_DIV_SCLK_DECON0_VCLK0)
|
|
DIV_EXTERN(DISP0_DIV_SCLK_DECON0_VCLK1)
|
|
DIV_EXTERN(DISP0_DIV_PHYCLK_HDMIPHY_PIXEL_CLKO)
|
|
DIV_EXTERN(DISP0_DIV_PHYCLK_HDMIPHY_TMDS_20B_CLKO)
|
|
DIV_EXTERN(DISP1_DIV_PCLK_DISP1_0_133)
|
|
DIV_EXTERN(DISP1_DIV_SCLK_DECON1_ECLK0)
|
|
DIV_EXTERN(DISP1_DIV_SCLK_DECON1_ECLK1)
|
|
DIV_EXTERN(FSYS1_DIV_PCLK_COMBO_PHY_WIFI)
|
|
DIV_EXTERN(G3D_DIV_ACLK_G3D)
|
|
DIV_EXTERN(G3D_DIV_PCLK_G3D)
|
|
DIV_EXTERN(G3D_DIV_SCLK_HPM_G3D)
|
|
DIV_EXTERN(G3D_DIV_SCLK_ATE_G3D)
|
|
DIV_EXTERN(ISP0_DIV_PCLK_ISP0)
|
|
DIV_EXTERN(ISP0_DIV_PCLK_ISP0_TPU)
|
|
DIV_EXTERN(ISP0_DIV_PCLK_ISP0_TREX_264)
|
|
DIV_EXTERN(ISP0_DIV_PCLK_ISP0_TREX_132)
|
|
DIV_EXTERN(ISP1_DIV_PCLK_ISP1_234)
|
|
DIV_EXTERN(MFC_DIV_PCLK_MFC_150)
|
|
DIV_EXTERN(MIF0_DIV_PCLK_MIF)
|
|
DIV_EXTERN(MIF0_DIV_SCLK_HPM_MIF)
|
|
DIV_EXTERN(MIF1_DIV_PCLK_MIF)
|
|
DIV_EXTERN(MIF1_DIV_SCLK_HPM_MIF)
|
|
DIV_EXTERN(MIF2_DIV_PCLK_MIF)
|
|
DIV_EXTERN(MIF2_DIV_SCLK_HPM_MIF)
|
|
DIV_EXTERN(MIF3_DIV_PCLK_MIF)
|
|
DIV_EXTERN(MIF3_DIV_SCLK_HPM_MIF)
|
|
DIV_EXTERN(MIF0_DIV_PCLK_SMC)
|
|
DIV_EXTERN(MIF1_DIV_PCLK_SMC)
|
|
DIV_EXTERN(MIF2_DIV_PCLK_SMC)
|
|
DIV_EXTERN(MIF3_DIV_PCLK_SMC)
|
|
DIV_EXTERN(MNGS_DIV_MNGS)
|
|
DIV_EXTERN(MNGS_DIV_ACLK_MNGS)
|
|
DIV_EXTERN(MNGS_DIV_ATCLK_MNGS_CORE)
|
|
DIV_EXTERN(MNGS_DIV_ATCLK_MNGS_SOC)
|
|
DIV_EXTERN(MNGS_DIV_ATCLK_MNGS_CSSYS_TRACECLK)
|
|
DIV_EXTERN(MNGS_DIV_ATCLK_MNGS_ASYNCATB_CAM1)
|
|
DIV_EXTERN(MNGS_DIV_ATCLK_MNGS_ASYNCATB_AUD)
|
|
DIV_EXTERN(MNGS_DIV_PCLK_DBG_MNGS)
|
|
DIV_EXTERN(MNGS_DIV_PCLK_RUN_MONITOR)
|
|
DIV_EXTERN(MNGS_DIV_PCLK_MNGS)
|
|
DIV_EXTERN(MNGS_DIV_CNTCLK_MNGS)
|
|
DIV_EXTERN(MNGS_DIV_MNGS_RUN_MONITOR)
|
|
DIV_EXTERN(MNGS_DIV_SCLK_PROMISE_MNGS)
|
|
DIV_EXTERN(MNGS_DIV_MNGS_PLL)
|
|
DIV_EXTERN(MSCL_DIV_PCLK_MSCL)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CCORE_800)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CCORE_264)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CCORE_G3D_800)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CCORE_528)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CCORE_132)
|
|
DIV_EXTERN(TOP_DIV_PCLK_CCORE_66)
|
|
DIV_EXTERN(TOP_DIV_ACLK_BUS0_528)
|
|
DIV_EXTERN(TOP_DIV_ACLK_BUS0_200)
|
|
DIV_EXTERN(TOP_DIV_PCLK_BUS0_132)
|
|
DIV_EXTERN(TOP_DIV_ACLK_BUS1_528)
|
|
DIV_EXTERN(TOP_DIV_PCLK_BUS1_132)
|
|
DIV_EXTERN(TOP_DIV_ACLK_DISP0_0_400)
|
|
DIV_EXTERN(TOP_DIV_ACLK_DISP0_1_400)
|
|
DIV_EXTERN(TOP_DIV_ACLK_DISP1_0_400)
|
|
DIV_EXTERN(TOP_DIV_ACLK_DISP1_1_400)
|
|
DIV_EXTERN(TOP_DIV_ACLK_MFC_600)
|
|
DIV_EXTERN(TOP_DIV_ACLK_MSCL0_528)
|
|
DIV_EXTERN(TOP_DIV_ACLK_MSCL1_528)
|
|
DIV_EXTERN(TOP_DIV_ACLK_IMEM_266)
|
|
DIV_EXTERN(TOP_DIV_ACLK_IMEM_200)
|
|
DIV_EXTERN(TOP_DIV_ACLK_IMEM_100)
|
|
DIV_EXTERN(TOP_DIV_ACLK_FSYS0_200)
|
|
DIV_EXTERN(TOP_DIV_ACLK_FSYS1_200)
|
|
DIV_EXTERN(TOP_DIV_ACLK_PERIS_66)
|
|
DIV_EXTERN(TOP_DIV_ACLK_PERIC0_66)
|
|
DIV_EXTERN(TOP_DIV_ACLK_PERIC1_66)
|
|
DIV_EXTERN(TOP_DIV_ACLK_ISP0_ISP0_528)
|
|
DIV_EXTERN(TOP_DIV_ACLK_ISP0_TPU_400)
|
|
DIV_EXTERN(TOP_DIV_ACLK_ISP0_TREX_528)
|
|
DIV_EXTERN(TOP_DIV_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D)
|
|
DIV_EXTERN(TOP_DIV_ACLK_ISP1_ISP1_468)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CAM0_CSIS0_414)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CAM0_CSIS1_168)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CAM0_CSIS2_234)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CAM0_3AA0_414)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CAM0_3AA1_414)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CAM0_CSIS3_132)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CAM0_TREX_528)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CAM1_ARM_672)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CAM1_TREX_VRA_528)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CAM1_TREX_B_528)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CAM1_BUS_264)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CAM1_PERI_84)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CAM1_CSIS2_414)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CAM1_CSIS3_132)
|
|
DIV_EXTERN(TOP_DIV_ACLK_CAM1_SCL_566)
|
|
DIV_EXTERN(TOP_DIV_SCLK_DISP0_DECON0_ECLK0)
|
|
DIV_EXTERN(TOP_DIV_SCLK_DISP0_DECON0_VCLK0)
|
|
DIV_EXTERN(TOP_DIV_SCLK_DISP0_DECON0_VCLK1)
|
|
DIV_EXTERN(TOP_DIV_SCLK_DISP0_HDMI_AUDIO)
|
|
DIV_EXTERN(TOP_DIV_SCLK_DISP1_DECON1_ECLK0)
|
|
DIV_EXTERN(TOP_DIV_SCLK_DISP1_DECON1_ECLK1)
|
|
DIV_EXTERN(TOP_DIV_SCLK_FSYS0_USBDRD30)
|
|
DIV_EXTERN(TOP_DIV_SCLK_FSYS0_MMC0)
|
|
DIV_EXTERN(TOP_DIV_SCLK_FSYS0_UFSUNIPRO20)
|
|
DIV_EXTERN(TOP_DIV_SCLK_FSYS0_PHY_24M)
|
|
DIV_EXTERN(TOP_DIV_SCLK_FSYS0_UFSUNIPRO_CFG)
|
|
DIV_EXTERN(TOP_DIV_SCLK_FSYS1_MMC2)
|
|
DIV_EXTERN(TOP_DIV_SCLK_FSYS1_UFSUNIPRO20)
|
|
DIV_EXTERN(TOP_DIV_SCLK_FSYS1_PCIE_PHY)
|
|
DIV_EXTERN(TOP_DIV_SCLK_FSYS1_UFSUNIPRO_CFG)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PERIC0_UART0)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PERIC1_SPI0)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PERIC1_SPI1)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PERIC1_SPI2)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PERIC1_SPI3)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PERIC1_SPI4)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PERIC1_SPI5)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PERIC1_SPI6)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PERIC1_SPI7)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PERIC1_UART1)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PERIC1_UART2)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PERIC1_UART3)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PERIC1_UART4)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PERIC1_UART5)
|
|
DIV_EXTERN(TOP_DIV_SCLK_CAM1_ISP_SPI0)
|
|
DIV_EXTERN(TOP_DIV_SCLK_CAM1_ISP_SPI1)
|
|
DIV_EXTERN(TOP_DIV_SCLK_CAM1_ISP_UART)
|
|
DIV_EXTERN(TOP_DIV_SCLK_AP2CP_MIF_PLL_OUT)
|
|
DIV_EXTERN(TOP_DIV_ACLK_PSCDC_400)
|
|
DIV_EXTERN(TOP_DIV_SCLK_BUS_PLL_MNGS)
|
|
DIV_EXTERN(TOP_DIV_SCLK_BUS_PLL_APOLLO)
|
|
DIV_EXTERN(TOP_DIV_SCLK_BUS_PLL_MIF)
|
|
DIV_EXTERN(TOP_DIV_SCLK_BUS_PLL_G3D)
|
|
DIV_EXTERN(TOP_DIV_SCLK_ISP_SENSOR0)
|
|
DIV_EXTERN(TOP_DIV_SCLK_ISP_SENSOR1)
|
|
DIV_EXTERN(TOP_DIV_SCLK_ISP_SENSOR2)
|
|
DIV_EXTERN(TOP_DIV_SCLK_ISP_SENSOR3)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PROMISE_INT)
|
|
DIV_EXTERN(TOP_DIV_SCLK_PROMISE_DISP)
|
|
|
|
|
|
|
|
GATE_EXTERN(APOLLO_GATE_ACLK_ASYNCACES_APOLLO_CCI)
|
|
GATE_EXTERN(APOLLO_GATE_ACLK_ASATBSLV_APOLLO3_CSSYS)
|
|
GATE_EXTERN(APOLLO_GATE_ACLK_ASATBSLV_APOLLO2_CSSYS)
|
|
GATE_EXTERN(APOLLO_GATE_ACLK_ASATBSLV_APOLLO1_CSSYS)
|
|
GATE_EXTERN(APOLLO_GATE_ACLK_ASATBSLV_APOLLO0_CSSYS)
|
|
GATE_EXTERN(APOLLO_GATE_PCLKDBG_DUMP_PC_APOLLO)
|
|
GATE_EXTERN(APOLLO_GATE_PCLKDBG_ASAPBMST_CSSYS_APOLLO)
|
|
GATE_EXTERN(APOLLO_GATE_PCLK_SYSREG_APOLLO)
|
|
GATE_EXTERN(APOLLO_GATE_PCLK_PMU_APOLLO)
|
|
GATE_EXTERN(APOLLO_GATE_PCLK_AXI2APB_APOLLO_ACLK)
|
|
GATE_EXTERN(APOLLO_GATE_PCLK_XIU_PERI_APOLLO_ACLK)
|
|
GATE_EXTERN(APOLLO_GATE_PCLK_HPM_APOLLO)
|
|
GATE_EXTERN(APOLLO_GATE_SCLK_APOLLO)
|
|
GATE_EXTERN(APOLLO_GATE_SCLK_PROMISE_APOLLO)
|
|
GATE_EXTERN(AUD_GATE_SCLK_CA5)
|
|
GATE_EXTERN(AUD_GATE_PCLK_PPMU_AUD)
|
|
GATE_EXTERN(AUD_GATE_PCLK_CP_I2S)
|
|
GATE_EXTERN(AUD_GATE_PCLK_SYSREG_AUD)
|
|
GATE_EXTERN(AUD_GATE_PCLK_GPIO_AUD)
|
|
GATE_EXTERN(AUD_GATE_PCLK_PMU_AUD)
|
|
GATE_EXTERN(AUD_GATE_PCLK_SLIMBUS)
|
|
GATE_EXTERN(AUD_GATE_PCLK_PCM)
|
|
GATE_EXTERN(AUD_GATE_PCLK_I2S)
|
|
GATE_EXTERN(AUD_GATE_PCLK_TIMER)
|
|
GATE_EXTERN(AUD_GATE_PCLK_SFR1)
|
|
GATE_EXTERN(AUD_GATE_PCLK_SFR0)
|
|
GATE_EXTERN(AUD_GATE_PCLK_SMMU)
|
|
GATE_EXTERN(AUD_GATE_ACLK_PPMU_AUD)
|
|
GATE_EXTERN(AUD_GATE_ACLK_INTR)
|
|
GATE_EXTERN(AUD_GATE_ACLK_XIU_LPASSX)
|
|
GATE_EXTERN(AUD_GATE_ACLK_SMMU)
|
|
GATE_EXTERN(AUD_GATE_ACLK_AXI_LH_ASYNC_SI_TOP)
|
|
GATE_EXTERN(AUD_GATE_ACLK_AXI_LH_ASYNC_MI_TOP)
|
|
GATE_EXTERN(AUD_GATE_ACLK_AXI_US_32TO64)
|
|
GATE_EXTERN(AUD_GATE_ACLK_SRAMC)
|
|
GATE_EXTERN(AUD_GATE_ACLK_DMAC)
|
|
GATE_EXTERN(AUD_GATE_PCLK_DBG)
|
|
GATE_EXTERN(AUD_GATE_ACLK_ATCLK_AUD)
|
|
GATE_EXTERN(AUD_GATE_SCLK_I2S)
|
|
GATE_EXTERN(AUD_GATE_SCLK_PCM)
|
|
GATE_EXTERN(AUD_GATE_SCLK_SLIMBUS)
|
|
GATE_EXTERN(AUD_GATE_SCLK_CP_I2S)
|
|
GATE_EXTERN(AUD_GATE_SCLK_ASRC)
|
|
GATE_EXTERN(AUD_GATE_SCLK_SLIMBUS_CLKIN)
|
|
GATE_EXTERN(AUD_GATE_SCLK_I2S_BCLK)
|
|
GATE_EXTERN(BUS0_GATE_ACLK_ACE_FSYS1)
|
|
GATE_EXTERN(BUS0_GATE_ACLK_LH_ISP0)
|
|
GATE_EXTERN(BUS0_GATE_ACLK_LH_DISP11)
|
|
GATE_EXTERN(BUS0_GATE_ACLK_LH_DISP10)
|
|
GATE_EXTERN(BUS0_GATE_ACLK_LH_DISP01)
|
|
GATE_EXTERN(BUS0_GATE_ACLK_LH_DISP00)
|
|
GATE_EXTERN(BUS0_GATE_ACLK_LH_CAM1)
|
|
GATE_EXTERN(BUS0_GATE_ACLK_LH_CAM0)
|
|
GATE_EXTERN(BUS0_GATE_ACLK_TREX_BUS0)
|
|
GATE_EXTERN(BUS0_GATE_ACLK_LH_FSYS1)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_CMU_BUS0)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_TREX_BUS0)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_PMU_BUS0)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_SYSREG_BUS0)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_LH_FSYS1SFRX)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_LH_PERIC1P)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_LH_PERIC0P)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_LH_PERISFRX)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_LH_DISP1SFRX)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_LH_DISP0SFRX)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_LH_ISPHX)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_LH_IS0X)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_AXI2APB_2MB_BUS0_TP)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_AHB2APB_BUS0P)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_AXI2APB_2MB_BUS0_TD)
|
|
GATE_EXTERN(BUS0_GATE_PCLK_TREX_P_BUS0)
|
|
GATE_EXTERN(BUS0_GATE_ACLK_TREX_P_BUS0)
|
|
GATE_EXTERN(BUS1_GATE_ACLK_LH_MSCL1)
|
|
GATE_EXTERN(BUS1_GATE_ACLK_LH_MSCL0)
|
|
GATE_EXTERN(BUS1_GATE_ACLK_LH_MFC1)
|
|
GATE_EXTERN(BUS1_GATE_ACLK_LH_MFC0)
|
|
GATE_EXTERN(BUS1_GATE_ACLK_LH_FSYS0)
|
|
GATE_EXTERN(BUS1_GATE_ACLK_TREX_BUS1)
|
|
GATE_EXTERN(BUS1_GATE_PCLK_CMU_BUS1)
|
|
GATE_EXTERN(BUS1_GATE_PCLK_TREX_BUS1)
|
|
GATE_EXTERN(BUS1_GATE_PCLK_SYSREG_BUS1)
|
|
GATE_EXTERN(BUS1_GATE_PCLK_PMU_BUS1)
|
|
GATE_EXTERN(BUS1_GATE_PCLK_LH_MSCLSFRX)
|
|
GATE_EXTERN(BUS1_GATE_PCLK_LH_MFCP)
|
|
GATE_EXTERN(BUS1_GATE_PCLK_LH_FSYS0SFRX)
|
|
GATE_EXTERN(BUS1_GATE_PCLK_AHB2APB_BUS1P)
|
|
GATE_EXTERN(BUS1_GATE_PCLK_AXI2APB_2MB_BUS1_TP)
|
|
GATE_EXTERN(BUS1_GATE_PCLK_AXI2APB_2MB_BUS1_TD)
|
|
GATE_EXTERN(BUS1_GATE_PCLK_TREX_P_BUS1)
|
|
GATE_EXTERN(BUS1_GATE_ACLK_TREX_P_BUS1)
|
|
GATE_EXTERN(CAM0_GATE_ACLK_BNS)
|
|
GATE_EXTERN(CAM0_GATE_ACLK_PXL_ASBS_CSIS2_int)
|
|
GATE_EXTERN(CAM0_GATE_ACLK_CSIS0)
|
|
GATE_EXTERN(CAM0_GATE_PCLK_BNS)
|
|
GATE_EXTERN(CAM0_GATE_ACLK_CSIS1)
|
|
GATE_EXTERN(CAM0_GATE_ACLK_CSIS2)
|
|
GATE_EXTERN(CAM0_GATE_ACLK_CSIS3)
|
|
GATE_EXTERN(CAM0_GATE_ACLK_3AA0)
|
|
GATE_EXTERN(CAM0_GATE_PCLK_3AA0)
|
|
GATE_EXTERN(CAM0_GATE_ACLK_3AA1)
|
|
GATE_EXTERN(CAM0_GATE_PCLK_3AA1)
|
|
GATE_EXTERN(CAM0_GATE_ACLK_SFW110_IS_A)
|
|
GATE_EXTERN(CAM0_GATE_ACLK_SysMMU6_IS_A)
|
|
GATE_EXTERN(CAM0_GATE_ACLK_TREX_A_5x1_IS_A)
|
|
GATE_EXTERN(CAM0_GATE_ACLK_LH_ASYNC_SI_CAM0)
|
|
GATE_EXTERN(CAM0_GATE_PCLK_PMU_CAM0)
|
|
GATE_EXTERN(CAM0_GATE_PCLK_SYSREG_CAM0)
|
|
GATE_EXTERN(CAM0_GATE_ACLK_LH_ASYNC_MI_CAM0)
|
|
GATE_EXTERN(CAM0_GATE_ACLK_XIUASYNC_MI_CAM0)
|
|
GATE_EXTERN(CAM0_GATE_PCLK_CAM0)
|
|
GATE_EXTERN(CAM0_GATE_PCLK_CSIS1)
|
|
GATE_EXTERN(CAM0_GATE_PCLK_CSIS0)
|
|
GATE_EXTERN(CAM0_GATE_PCLK_XIUASYNC_MI_CAM0)
|
|
GATE_EXTERN(CAM0_GATE_PCLK_TREX_A_5x1_IS_A)
|
|
GATE_EXTERN(CAM0_GATE_PCLK_SysMMU6_IS_A)
|
|
GATE_EXTERN(CAM0_GATE_PCLK_SFW110_IS_A_IS_A)
|
|
GATE_EXTERN(CAM0_GATE_SCLK_PROMISE_CAM0)
|
|
GATE_EXTERN(CAM0_GATE_PHYCLK_HS0_CSIS0_RX_BYTE)
|
|
GATE_EXTERN(CAM0_GATE_PHYCLK_HS1_CSIS0_RX_BYTE)
|
|
GATE_EXTERN(CAM0_GATE_PHYCLK_HS2_CSIS0_RX_BYTE)
|
|
GATE_EXTERN(CAM0_GATE_PHYCLK_HS3_CSIS0_RX_BYTE)
|
|
GATE_EXTERN(CAM0_GATE_PHYCLK_HS0_CSIS1_RX_BYTE)
|
|
GATE_EXTERN(CAM0_GATE_PHYCLK_HS1_CSIS1_RX_BYTE)
|
|
GATE_EXTERN(CAM0_GATE_PCLK_HPM_APBIF_CAM0)
|
|
GATE_EXTERN(CAM0_LOCAL_GATE_ACLK_BNS)
|
|
GATE_EXTERN(CAM0_LOCAL_GATE_ACLK_PXL_ASBS_CSIS2_int)
|
|
GATE_EXTERN(CAM0_LOCAL_GATE_ACLK_CSIS0)
|
|
GATE_EXTERN(CAM0_LOCAL_GATE_PCLK_BNS)
|
|
GATE_EXTERN(CAM0_LOCAL_GATE_ACLK_CSIS1)
|
|
GATE_EXTERN(CAM0_LOCAL_GATE_ACLK_CSIS2)
|
|
GATE_EXTERN(CAM0_LOCAL_GATE_ACLK_CSIS3)
|
|
GATE_EXTERN(CAM0_LOCAL_GATE_ACLK_3AA0)
|
|
GATE_EXTERN(CAM0_LOCAL_GATE_PCLK_3AA0)
|
|
GATE_EXTERN(CAM0_LOCAL_GATE_ACLK_3AA1)
|
|
GATE_EXTERN(CAM0_LOCAL_GATE_PCLK_3AA1)
|
|
GATE_EXTERN(CAM0_LOCAL_GATE_PCLK_CSIS1)
|
|
GATE_EXTERN(CAM0_LOCAL_GATE_PCLK_CSIS0)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_ARM)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_ARM)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_SMMU_VRA)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_VRA)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_VRA)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_LH_SI)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_TREX_CAM1)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_XIU_from_ISP1)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_SMMU_IS_B)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_SFW)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_ASYNC_CA7_TO_DRAM)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_SMMU_ISPCPU)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_TREX_B)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_LH_MI)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_PERI)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_CSIS3)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_CSIS2)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_XIU_to_CAM0)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_XIU_to_ISP1)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_XIU_to_ISP0)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_CMU_LOCAL)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_SYSREG_CAM1)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_PMU_CAM1)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_TREX_CAM1)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_XIU_from_ISP1)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_PERI)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_SMMU_ISPCPU)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_SMMU_VRA)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_SMMU_IS_B)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_SFW)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_TREX_B)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_WDT)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_UART)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_SPI1)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_SPI0)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_PWM)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_MCUCTL)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_I2C3)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_I2C2)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_I2C1)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_I2C0)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_PDMA)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_BRIDGE_PERI)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_CSIS2)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_CSIS3)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_SMMU_MC_SC)
|
|
GATE_EXTERN(CAM1_GATE_ACLK_MC_SC)
|
|
GATE_EXTERN(CAM1_GATE_PCLK_SMMU_MC_SC)
|
|
GATE_EXTERN(CAM1_GATE_SCLK_ISP_PERI_IS_B_SPI0_EXT_CLK_ISP)
|
|
GATE_EXTERN(CAM1_GATE_SCLK_ISP_PERI_IS_B_SPI1_EXT_CLK_ISP)
|
|
GATE_EXTERN(CAM1_GATE_SCLK_ISP_PERI_IS_B_UART_EXT_CLK_ISP)
|
|
GATE_EXTERN(CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C3_ISP)
|
|
GATE_EXTERN(CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C2_ISP)
|
|
GATE_EXTERN(CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C1_ISP)
|
|
GATE_EXTERN(CAM1_GATE_SCLK_CAM1_ISP_IS_B_OSCCLK_I2C0_ISP)
|
|
GATE_EXTERN(CAM1_GATE_SCLK_ISP_PERI_IS_B_PWM_ISP)
|
|
GATE_EXTERN(CAM1_GATE_PHYCLK_HS0_CSIS2_RX_BYTE)
|
|
GATE_EXTERN(CAM1_GATE_PHYCLK_HS1_CSIS2_RX_BYTE)
|
|
GATE_EXTERN(CAM1_GATE_PHYCLK_HS2_CSIS2_RX_BYTE)
|
|
GATE_EXTERN(CAM1_GATE_PHYCLK_HS3_CSIS2_RX_BYTE)
|
|
GATE_EXTERN(CAM1_GATE_PHYCLK_HS0_CSIS3_RX_BYTE)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_ACLK_VRA)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_PCLK_VRA)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_PCLK_CSIS3)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_PCLK_CSIS2)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_PCLK_WDT)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_PCLK_UART)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_PCLK_SPI1)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_PCLK_SPI0)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_PCLK_PWM)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_PCLK_MCUCTL)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_PCLK_I2C3)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_PCLK_I2C2)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_PCLK_I2C1)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_PCLK_I2C0)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_ACLK_PDMA)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_ACLK_CSIS2)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_ACLK_CSIS3)
|
|
GATE_EXTERN(CAM1_LOCAL_GATE_ACLK_MC_SC)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_AS_SI_IRPM)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_MPACEBRIDGE)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_PULSE2HS)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_DBG_LH_MI_MIF_CCORE)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_SCI_PPC_WRAPPER)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_ACE_AS_MI_APL_CCORE)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_MPACE_SI)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_CPACE_MI)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_ATB_SI_CCOREBDU_MNGSCS)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_BDU)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_TREX_CCORE_SCI)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_SCI)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_CLEANY_CPPERI)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_US_CPPERI)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_LH_MI_CPPERI_CCORE)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_LH_SI_CCORESFRX_IMEMX)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_LH_MI_G3DXIRAM_CCORESFR)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_DS_IRPM)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_XIU_CCORESFRX)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_TREX_P_CCORE_BUS)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_TREX_CCORE_PERI)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_AS_MI_IRPM)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_TREX_CCORE_G3D)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_ACEL_LH_MI_G3DX1_CCORETD)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_ACEL_LH_MI_G3DX0_CCORETD)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_ATB_APL_MNGS)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_XIU_CPX)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_CLEANY_CPDATA)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_LH_MI_CPDATA_CCORE)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_LH_MI_IMEMX_CCORETD)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_LH_MI_AUDX_CCORETD)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_AS_MI_MNGSCS_CCORETD)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_TREX_CCORE)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_CMU)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_HPM_APBIF)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_SCI)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_GPIO_CCORE)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_S_MAILBOX)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_MAILBOX)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_SYSREG_CCORE)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_GPIO_APBIF_ALIVE)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_SCI_PPC_WRAPPER)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_VT_MON_APB)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_PMU_CCORE)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_PMU_APBIF)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_CMU_TOPC_APBIF)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_AXI2APB_CORESIGHT)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_AXI2APB_TREX_P_CCORE)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_AXI2APB_TREX_CCORE)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_AXI2APB_CCORE)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_TREX_P_CCORE)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_TREX_CCORE)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_BDU)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF3P)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF2P)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF1P)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_MIF0P)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_G3DP)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_LH_SI_CCORETP_AUDX)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_AS_SI_CCORETP_APL)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_AXI_AS_SI_CCORETP_MNGS)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_APB_AS_MI_CCORETP_MNGSCS)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_APB_AS_MI_MNGSCS_CCOREBDU)
|
|
GATE_EXTERN(CCORE_GATE_ACLK_TREX_P_CCORE)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_APBASYNC_BAT_AP)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_APBASYNC_BAT_CP)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_HSI2C_BAT_AP)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_HSI2C)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_HSI2C_BAT_CP)
|
|
GATE_EXTERN(CCORE_GATE_PCLK_HSI2C_CP)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_PPMU_DISP0_0)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_SMMU_DISP0_0)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_XIU_DISP0_0)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_LH_ASYNC_SI_R_TOP_DISP)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_VPP0_ACLK_0)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_PPMU_DISP0_1)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_SMMU_DISP0_1)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_XIU_DISP0_1)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_LH_ASYNC_SI_TOP_DISP)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_VPP0_ACLK_1)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_SFW_DISP0_0)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_SFW_DISP0_1)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_SMMU_DISP0_1)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_SMMU_DISP0_0)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_PPMU_DISP0_1)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_PPMU_DISP0_0)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_HDMI_PHY)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_DISP0_MUX)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_DP)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_HDMI_AUDIO)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_HDMI)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_DSIM2)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_DSIM1)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_DSIM0)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_SYSREG_DISP0)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_PMU_DISP0)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_CMU_DISP0)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_XIU_DISP0SFRX)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_AXI2APB_DISP0_1P)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_AXI2APB_DISP0_0P)
|
|
GATE_EXTERN(DISP0_GATE_ACLK_AXI_LH_ASYNC_MI_DISP0SFR)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_HPM_APBIF_DISP0)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_DECON0)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_VPP0_0)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_VPP0_1)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_SFW_DISP0_0)
|
|
GATE_EXTERN(DISP0_GATE_PCLK_SFW_DISP0_1)
|
|
GATE_EXTERN(DISP0_GATE_SCLK_DISP1_400)
|
|
GATE_EXTERN(DISP0_GATE_SCLK_DECON0_ECLK0)
|
|
GATE_EXTERN(DISP0_GATE_SCLK_DECON0_VCLK0)
|
|
GATE_EXTERN(DISP0_GATE_SCLK_DECON0_VCLK1)
|
|
GATE_EXTERN(DISP0_GATE_SCLK_HDMI_AUDIO)
|
|
GATE_EXTERN(DISP0_GATE_SCLK_PROMISE_DISP0)
|
|
GATE_EXTERN(DISP0_GATE_PHYCLK_HDMIPHY_TMDS_20B_CLKO)
|
|
GATE_EXTERN(DISP0_GATE_PHYCLK_HDMIPHY_TMDS_10B_CLKO)
|
|
GATE_EXTERN(DISP0_GATE_PHYCLK_HDMIPHY_PIXEL_CLKO)
|
|
GATE_EXTERN(DISP0_GATE_PHYCLK_MIPIDPHY0_BITCLKDIV8)
|
|
GATE_EXTERN(DISP0_GATE_PHYCLK_MIPIDPHY0_RXCLKESC0)
|
|
GATE_EXTERN(DISP0_GATE_PHYCLK_MIPIDPHY1_BITCLKDIV8)
|
|
GATE_EXTERN(DISP0_GATE_PHYCLK_MIPIDPHY1_RXCLKESC0)
|
|
GATE_EXTERN(DISP0_GATE_PHYCLK_MIPIDPHY2_BITCLKDIV8)
|
|
GATE_EXTERN(DISP0_GATE_PHYCLK_MIPIDPHY2_RXCLKESC0)
|
|
GATE_EXTERN(DISP0_GATE_PHYCLK_DPPHY_CH3_TXD_CLK)
|
|
GATE_EXTERN(DISP0_GATE_PHYCLK_DPPHY_CH2_TXD_CLK)
|
|
GATE_EXTERN(DISP0_GATE_PHYCLK_DPPHY_CH1_TXD_CLK)
|
|
GATE_EXTERN(DISP0_GATE_PHYCLK_DPPHY_CH0_TXD_CLK)
|
|
GATE_EXTERN(DISP0_GATE_OSCCLK_I_MIPI_DPHY_M4S4_M_XI)
|
|
GATE_EXTERN(DISP0_GATE_OSCCLK_I_MIPI_DPHY_M4S0_M_XI)
|
|
GATE_EXTERN(DISP0_GATE_OSCCLK_I_MIPI_DPHY_M1S0_M_XI)
|
|
GATE_EXTERN(DISP0_GATE_OSCCLK_I_DPTX_PHY_I_REF_CLK_24M)
|
|
GATE_EXTERN(DISP0_GATE_OSCCLK_DP_I_CLK_24M)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_XIU_DISP1X0)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_AXI_LH_ASYNC_SI_DISP1_0)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_PPMU_DISP1_0)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_SMMU_DISP1_0)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_VPP1_0)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_XIU_DISP1X1)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_AXI_LH_ASYNC_SI_DISP1_1)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_QE_DISP1_WDMA)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_PPMU_DISP1_1)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_SMMU_DISP1_1)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_VPP1_1)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_SFW_DISP1_0)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_SFW_DISP1_1)
|
|
GATE_EXTERN(DISP1_GATE_PCLK_DECON1_1)
|
|
GATE_EXTERN(DISP1_GATE_PCLK_DECON1_0)
|
|
GATE_EXTERN(DISP1_GATE_PCLK_QE_DISP1_WDMA)
|
|
GATE_EXTERN(DISP1_GATE_PCLK_PPMU_DISP1_1)
|
|
GATE_EXTERN(DISP1_GATE_PCLK_PPMU_DISP1_0)
|
|
GATE_EXTERN(DISP1_GATE_PCLK_SMMU_DISP1_1)
|
|
GATE_EXTERN(DISP1_GATE_PCLK_SMMU_DISP1_0)
|
|
GATE_EXTERN(DISP1_GATE_PCLK_SYSREG_DISP1)
|
|
GATE_EXTERN(DISP1_GATE_PCLK_PMU_DISP1)
|
|
GATE_EXTERN(DISP1_GATE_PCLK_CMU_DISP1)
|
|
GATE_EXTERN(DISP1_GATE_PCLK_VPP1_0)
|
|
GATE_EXTERN(DISP1_GATE_PCLK_VPP1_1)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_AXI2APB_DISP1_1X)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_AXI2APB_DISP1_0X)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_XIU_DISP1SFRX)
|
|
GATE_EXTERN(DISP1_GATE_ACLK_AXI_LH_ASYNC_MI_DISP1SFR)
|
|
GATE_EXTERN(DISP1_GATE_PCLK_HPM_APBIF_DISP1)
|
|
GATE_EXTERN(DISP1_GATE_PCLK_SFW_DISP1_0)
|
|
GATE_EXTERN(DISP1_GATE_PCLK_SFW_DISP1_1)
|
|
GATE_EXTERN(DISP1_GATE_SCLK_DECON1_ECLK_0)
|
|
GATE_EXTERN(DISP1_GATE_SCLK_DECON1_ECLK_1)
|
|
GATE_EXTERN(DISP1_GATE_SCLK_PROMISE_DISP1)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_AXI2ACEL_FSYS0X)
|
|
GATE_EXTERN(FSYS0_GATE_PCLK_CMU_FSYS0)
|
|
GATE_EXTERN(FSYS0_GATE_PCLK_GPIO_FSYS0)
|
|
GATE_EXTERN(FSYS0_GATE_PCLK_SYSREG_FSYS0)
|
|
GATE_EXTERN(FSYS0_GATE_PCLK_PPMU_FSYS0)
|
|
GATE_EXTERN(FSYS0_GATE_PCLK_PMU_FSYS0)
|
|
GATE_EXTERN(FSYS0_GATE_PCLK_ETR_USB_FSYS0)
|
|
GATE_EXTERN(FSYS0_GATE_HCLK_USBHOST20)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_AXI_US_USBHS_FSYS0X)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_ETR_USB_FSYS0)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_UFS_LINK_EMBEDDED)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_USBDRD30)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_MMC0)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_PDMAS)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_PDMA0)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_PPMU_FSYS0)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_XIU_FSYS0SFRX)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_AXI_US_USBDRD30X_FSYS0X)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_AXI_US_PDMAX_FSYS0X)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_AXI2AHB_FSYS0H)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_AXI2AHB_USBDRD30H)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_AXI_LH_ASYNC_MI_ETR_USB_FSYS0)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_XIU_PDMAX)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_XIU_USBX)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_XIU_EMBEDDEDX)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_XIU_FSYS0X)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_AXI2APB_FSYS0P)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_AHB_BRIDGE_FSYS0H)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_AXI_LH_ASYNC_MI_TOP_FSYS0)
|
|
GATE_EXTERN(FSYS0_GATE_ACLK_ACEL_LH_ASYNC_SI_TOP_FSYS0)
|
|
GATE_EXTERN(FSYS0_GATE_PCLK_HPM_APBIF_FSYS0)
|
|
GATE_EXTERN(FSYS0_GATE_SCLK_USBDRD30_SUSPEND_CLK)
|
|
GATE_EXTERN(FSYS0_GATE_SCLK_MMC0)
|
|
GATE_EXTERN(FSYS0_GATE_SCLK_UFSUNIPRO_EMBEDDED)
|
|
GATE_EXTERN(FSYS0_GATE_SCLK_USBDRD30_REF_CLK)
|
|
GATE_EXTERN(FSYS0_GATE_PHYCLK_USBDRD30_UDRD30_PHYCLOCK)
|
|
GATE_EXTERN(FSYS0_GATE_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK)
|
|
GATE_EXTERN(FSYS0_GATE_PHYCLK_UFS_TX0_SYMBOL)
|
|
GATE_EXTERN(FSYS0_GATE_PHYCLK_UFS_RX0_SYMBOL)
|
|
GATE_EXTERN(FSYS0_GATE_PHYCLK_USBHOST20_PHYCLOCK)
|
|
GATE_EXTERN(FSYS0_GATE_PHYCLK_USBHOST20_FREECLK)
|
|
GATE_EXTERN(FSYS0_GATE_PHYCLK_USBHOST20_CLK48MOHCI)
|
|
GATE_EXTERN(FSYS0_GATE_PHYCLK_UFS_RX_PWM_CLK)
|
|
GATE_EXTERN(FSYS0_GATE_PHYCLK_UFS_TX_PWM_CLK)
|
|
GATE_EXTERN(FSYS0_GATE_PHYCLK_UFS_REFCLK_OUT_SOC)
|
|
GATE_EXTERN(FSYS0_GATE_SCLK_PROMISE_FSYS0)
|
|
GATE_EXTERN(FSYS0_GATE_SCLK_USBHOST20PHY_REF_CLK)
|
|
GATE_EXTERN(FSYS0_GATE_SCLK_UFSUNIPRO_EMBEDDED_CFG)
|
|
GATE_EXTERN(FSYS0_GATE_SCLK_USBHOST20_REF_CLK)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_AXI2ACEL_FSYS1X)
|
|
GATE_EXTERN(FSYS1_GATE_PCLK_CMU_FSYS1)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_COMBO_PHY_PCS_PCLK_WIFI1)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_COMBO_PHY_PCS_PCLK_WIFI0)
|
|
GATE_EXTERN(FSYS1_GATE_PCLK_PMU_FSYS1)
|
|
GATE_EXTERN(FSYS1_GATE_PCLK_PPMU_FSYS1)
|
|
GATE_EXTERN(FSYS1_GATE_PCLK_GPIO_FSYS1)
|
|
GATE_EXTERN(FSYS1_GATE_PCLK_SYSREG_FSYS1)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_SROMC_FSYS1)
|
|
GATE_EXTERN(FSYS1_GATE_PCLK_PCIE_WIFI1)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_PCIE_WIFI1_DBI)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_PCIE_WIFI1_SLV)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_PCIE_WIFI1_MSTR)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_AHB2AXI_PCIE_WIFI1)
|
|
GATE_EXTERN(FSYS1_GATE_PCLK_PCIE_WIFI0)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_PCIE_WIFI0_DBI)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_PCIE_WIFI0_SLV)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_PCIE_WIFI0_MSTR)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_AHB2AXI_PCIE_WIFI0)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_PPMU_FSYS1)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_AHB_BRIDGE_FSYS1_S4)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_AXI2AHB_FSYS1_S4)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_AXI2APB_FSYS1_S1)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_AXI2AHB_FSYS1_S0)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_XIU_FSYS1SFRX)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_XIU_SDCARDX)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_XIU_FSYS1X)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_AXI_LH_ASYNC_MI_TOP_FSYS1)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_ACEL_LH_ASYNC_SI_TOP_FSYS1)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_UFS_LINK_SDCARD)
|
|
GATE_EXTERN(FSYS1_GATE_ACLK_MMC2)
|
|
GATE_EXTERN(FSYS1_GATE_PCLK_HPM_APBIF_FSYS1)
|
|
GATE_EXTERN(FSYS1_GATE_PCLK_COMBO_PHY_WIFI1)
|
|
GATE_EXTERN(FSYS1_GATE_PCLK_COMBO_PHY_WIFI0)
|
|
GATE_EXTERN(FSYS1_GATE_SCLK_MMC2)
|
|
GATE_EXTERN(FSYS1_GATE_SCLK_UFSUNIPRO_SDCARD)
|
|
GATE_EXTERN(FSYS1_GATE_SCLK_UFSUNIPRO_SDCARD_CFG)
|
|
GATE_EXTERN(FSYS1_GATE_SCLK_PCIE_LINK_WIFI0)
|
|
GATE_EXTERN(FSYS1_GATE_SCLK_PCIE_LINK_WIFI1)
|
|
GATE_EXTERN(FSYS1_GATE_PHYCLK_UFS_LINK_SDCARD_TX0_SYMBOL)
|
|
GATE_EXTERN(FSYS1_GATE_PHYCLK_UFS_LINK_SDCARD_RX0_SYMBOL)
|
|
GATE_EXTERN(FSYS1_GATE_PHYCLK_PCIE_WIFI0_TX0)
|
|
GATE_EXTERN(FSYS1_GATE_PHYCLK_PCIE_WIFI0_RX0)
|
|
GATE_EXTERN(FSYS1_GATE_PHYCLK_PCIE_WIFI1_TX0)
|
|
GATE_EXTERN(FSYS1_GATE_PHYCLK_PCIE_WIFI1_RX0)
|
|
GATE_EXTERN(FSYS1_GATE_PHYCLK_PCIE_WIFI0_DIG_REFCLK)
|
|
GATE_EXTERN(FSYS1_GATE_PHYCLK_PCIE_WIFI1_DIG_REFCLK)
|
|
GATE_EXTERN(FSYS1_GATE_PHYCLK_UFS_LINK_SDCARD_RX_PWM_CLK)
|
|
GATE_EXTERN(FSYS1_GATE_PHYCLK_UFS_LINK_SDCARD_TX_PWM_CLK)
|
|
GATE_EXTERN(FSYS1_GATE_PHYCLK_UFS_LINK_SDCARD_REFCLK_OUT_SOC)
|
|
GATE_EXTERN(FSYS1_GATE_SCLK_PROMISE_FSYS1)
|
|
GATE_EXTERN(G3D_GATE_ACLK_G3D)
|
|
GATE_EXTERN(G3D_GATE_ACLK_GRAY_DEC)
|
|
GATE_EXTERN(G3D_GATE_ACLK_SFW100_ACEL_G3D1)
|
|
GATE_EXTERN(G3D_GATE_ACLK_SFW100_ACEL_G3D0)
|
|
GATE_EXTERN(G3D_GATE_ACLK_XIU_G3D)
|
|
GATE_EXTERN(G3D_GATE_ACLK_PPMU_G3D1)
|
|
GATE_EXTERN(G3D_GATE_ACLK_PPMU_G3D0)
|
|
GATE_EXTERN(G3D_GATE_ACLK_ASYNCAPBM_G3D)
|
|
GATE_EXTERN(G3D_GATE_ACLK_ASYNCAXI_G3D)
|
|
GATE_EXTERN(G3D_GATE_ACLK_AXI_DS_G3D)
|
|
GATE_EXTERN(G3D_GATE_ACLK_ACEL_LH_ASYNC_SI_G3D1)
|
|
GATE_EXTERN(G3D_GATE_ACLK_ACEL_LH_ASYNC_SI_G3D0)
|
|
GATE_EXTERN(G3D_GATE_PCLK_SFW100_ACEL_G3D1)
|
|
GATE_EXTERN(G3D_GATE_PCLK_SFW100_ACEL_G3D0)
|
|
GATE_EXTERN(G3D_GATE_PCLK_HPM_G3D)
|
|
GATE_EXTERN(G3D_GATE_PCLK_PPMU_G3D1)
|
|
GATE_EXTERN(G3D_GATE_PCLK_PPMU_G3D0)
|
|
GATE_EXTERN(G3D_GATE_PCLK_PMU_G3D)
|
|
GATE_EXTERN(G3D_GATE_ACLK_ASYNCAPBS_G3D)
|
|
GATE_EXTERN(G3D_GATE_PCLK_SYSREG_G3D)
|
|
GATE_EXTERN(G3D_GATE_ACLK_AXI2APB_G3DP)
|
|
GATE_EXTERN(G3D_GATE_ACLK_AXI_LH_ASYNC_MI_G3DP)
|
|
GATE_EXTERN(G3D_GATE_SCLK_HPM2_G3D)
|
|
GATE_EXTERN(G3D_GATE_SCLK_HPM1_G3D)
|
|
GATE_EXTERN(G3D_GATE_SCLK_HPM0_G3D)
|
|
GATE_EXTERN(G3D_GATE_SCLK_AXI_LH_ASYNC_SI_G3DIRAM)
|
|
GATE_EXTERN(G3D_GATE_SCLK_ASYNCAXI_G3D)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_MC)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_XIU_3X1_SSS)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_AXI_US_APM)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_ASYNCAHBMSTM_APM)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_ASYNCAHBM_SSS_ATLAS)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_LH_ASYNC_SI_IMEM)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_PPMU_SSSX)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_XIU_IMEMX)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_SSS)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_RTIC)
|
|
GATE_EXTERN(IMEM_GATE_PCLK_CMU_IMEM)
|
|
GATE_EXTERN(IMEM_GATE_PCLK_SYSREG_IMEM)
|
|
GATE_EXTERN(IMEM_GATE_PCLK_MC)
|
|
GATE_EXTERN(IMEM_GATE_PCLK_PPMU_SSSX)
|
|
GATE_EXTERN(IMEM_GATE_PCLK_PMU_IMEM)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_ASYNCAHBSS_APM)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_AXI2AHB_APM)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_INT_MEM_ALV)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_INT_MEM)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_AXIDS_PIMEMX_IMEM)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_AXILHASYNCM_PIMEMX)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_AXI2APB_IMEM_1)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_AXI2APB_IMEM_0)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_XIU_PIMEMX1)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_XIU_PIMEMX0)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_GIC)
|
|
GATE_EXTERN(IMEM_GATE_PCLK_SSS)
|
|
GATE_EXTERN(IMEM_GATE_PCLK_RTIC)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_ASYNCAHBSM_APM)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_AHB2AXI_APM)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_ASYNCAHBMSTS_APM)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_CM3_APM)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_AHB_BUSMATRIX_APM)
|
|
GATE_EXTERN(IMEM_GATE_SCLK_CM3_APM)
|
|
GATE_EXTERN(IMEM_GATE_ACLK_APM)
|
|
GATE_EXTERN(ISP0_GATE_ACLK_FIMC_ISP0)
|
|
GATE_EXTERN(ISP0_GATE_PCLK_FIMC_ISP0)
|
|
GATE_EXTERN(ISP0_GATE_ACLK_FIMC_TPU)
|
|
GATE_EXTERN(ISP0_GATE_PCLK_FIMC_TPU)
|
|
GATE_EXTERN(ISP0_GATE_ACLK_SysMMU601)
|
|
GATE_EXTERN(ISP0_GATE_CLK_C_TREX_C)
|
|
GATE_EXTERN(ISP0_GATE_CLK_AXI_LH_ASYNC_SI_TOP_ISP0)
|
|
GATE_EXTERN(ISP0_GATE_PCLK_SYSREG_ISP0)
|
|
GATE_EXTERN(ISP0_GATE_PCLK_PMU_ISP0)
|
|
GATE_EXTERN(ISP0_GATE_ACLK_XIU_N_ASYNC_MI)
|
|
GATE_EXTERN(ISP0_GATE_PCLK_ISP0)
|
|
GATE_EXTERN(ISP0_GATE_PCLK_HPM_APBIF_ISP0)
|
|
GATE_EXTERN(ISP0_GATE_PCLK_SysMMU601)
|
|
GATE_EXTERN(ISP0_GATE_PCLK_TREX_C)
|
|
GATE_EXTERN(ISP0_GATE_SCLK_PROMISE_ISP0)
|
|
GATE_EXTERN(ISP0_GATE_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D)
|
|
GATE_EXTERN(ISP0_LOCAL_GATE_ACLK_FIMC_ISP0)
|
|
GATE_EXTERN(ISP0_LOCAL_GATE_PCLK_FIMC_ISP0)
|
|
GATE_EXTERN(ISP0_LOCAL_GATE_ACLK_FIMC_TPU)
|
|
GATE_EXTERN(ISP0_LOCAL_GATE_PCLK_FIMC_TPU)
|
|
GATE_EXTERN(ISP0_LOCAL_GATE_CLK_C_TREX_C)
|
|
GATE_EXTERN(ISP0_LOCAL_GATE_PCLK_TREX_C)
|
|
GATE_EXTERN(ISP1_GATE_ACLK_XIU_N_ASYNC_SI)
|
|
GATE_EXTERN(ISP1_GATE_ACLK_FIMC_ISP1)
|
|
GATE_EXTERN(ISP1_GATE_PCLK_SYSREG_ISP1)
|
|
GATE_EXTERN(ISP1_GATE_PCLK_PMU_ISP1)
|
|
GATE_EXTERN(ISP1_GATE_ACLK_AXI2APB_BRIDGE_IS2P)
|
|
GATE_EXTERN(ISP1_GATE_ACLK_XIU_N_ASYNC_MI)
|
|
GATE_EXTERN(ISP1_GATE_PCLK_FIMC_ISP1)
|
|
GATE_EXTERN(ISP1_GATE_PCLK_HPM_APBIF_ISP1)
|
|
GATE_EXTERN(ISP1_GATE_SCLK_PROMISE_ISP1)
|
|
GATE_EXTERN(ISP1_LOCAL_GATE_ACLK_FIMC_ISP1)
|
|
GATE_EXTERN(ISP1_LOCAL_GATE_PCLK_FIMC_ISP1)
|
|
GATE_EXTERN(MFC_GATE_ACLK_ASYNCAPB_MFC)
|
|
GATE_EXTERN(MFC_GATE_ACLK_SMMU_MFC_1)
|
|
GATE_EXTERN(MFC_GATE_ACLK_SMMU_MFC_0)
|
|
GATE_EXTERN(MFC_GATE_ACLK_MFC)
|
|
GATE_EXTERN(MFC_GATE_ACLK_PPMU_MFC_1)
|
|
GATE_EXTERN(MFC_GATE_ACLK_PPMU_MFC_0)
|
|
GATE_EXTERN(MFC_GATE_ACLK_LH_S_MFC_1)
|
|
GATE_EXTERN(MFC_GATE_ACLK_LH_S_MFC_0)
|
|
GATE_EXTERN(MFC_GATE_ACLK_SFW_MFC_0)
|
|
GATE_EXTERN(MFC_GATE_ACLK_SFW_MFC_1)
|
|
GATE_EXTERN(MFC_GATE_PCLK_SYSREG_MFC)
|
|
GATE_EXTERN(MFC_GATE_PCLK_SMMU_MFC_1)
|
|
GATE_EXTERN(MFC_GATE_PCLK_SMMU_MFC_0)
|
|
GATE_EXTERN(MFC_GATE_PCLK_PPMU_MFC_1)
|
|
GATE_EXTERN(MFC_GATE_PCLK_PPMU_MFC_0)
|
|
GATE_EXTERN(MFC_GATE_PCLK_PMU_MFC)
|
|
GATE_EXTERN(MFC_GATE_PCLK_CMU_MFC)
|
|
GATE_EXTERN(MFC_GATE_PCLK_ASYNCAPB_MFC)
|
|
GATE_EXTERN(MFC_GATE_ACLK_AXI2APB_MFCSFR)
|
|
GATE_EXTERN(MFC_GATE_ACLK_LH_M_MFC)
|
|
GATE_EXTERN(MFC_GATE_PCLK_HPM_APBIF_MFC)
|
|
GATE_EXTERN(MFC_GATE_PCLK_SFW_MFC_0)
|
|
GATE_EXTERN(MFC_GATE_PCLK_SFW_MFC_1)
|
|
GATE_EXTERN(MFC_GATE_SCLK_PROMISE_MFC)
|
|
GATE_EXTERN(MIF0_GATE_ACLK_APSCDC)
|
|
GATE_EXTERN(MIF0_GATE_ACLK_PPC_DEBUG)
|
|
GATE_EXTERN(MIF0_GATE_ACLK_PPC_DVFS)
|
|
GATE_EXTERN(MIF0_GATE_ACLK_SMC)
|
|
GATE_EXTERN(MIF0_GATE_PCLK_SMC1)
|
|
GATE_EXTERN(MIF0_GATE_PCLK_DMC_MISC)
|
|
GATE_EXTERN(MIF0_GATE_PCLK_PPC_DEBUG)
|
|
GATE_EXTERN(MIF0_GATE_PCLK_PPC_DVFS)
|
|
GATE_EXTERN(MIF0_GATE_PCLK_SYSREG_MIF)
|
|
GATE_EXTERN(MIF0_GATE_PCLK_HPM)
|
|
GATE_EXTERN(MIF0_GATE_ACLK_AXI_ASYNC)
|
|
GATE_EXTERN(MIF0_GATE_PCLK_MIFP)
|
|
GATE_EXTERN(MIF0_GATE_PCLK_PMU_MIF)
|
|
GATE_EXTERN(MIF0_GATE_PCLK_LPDDR4PHY)
|
|
GATE_EXTERN(MIF0_GATE_PCLK_SMC2)
|
|
GATE_EXTERN(MIF0_GATE_SCLK_PROMISE)
|
|
GATE_EXTERN(MIF0_GATE_RCLK_DREX)
|
|
GATE_EXTERN(MIF1_GATE_ACLK_APSCDC)
|
|
GATE_EXTERN(MIF1_GATE_ACLK_PPC_DEBUG)
|
|
GATE_EXTERN(MIF1_GATE_ACLK_PPC_DVFS)
|
|
GATE_EXTERN(MIF1_GATE_ACLK_SMC)
|
|
GATE_EXTERN(MIF1_GATE_PCLK_SMC1)
|
|
GATE_EXTERN(MIF1_GATE_PCLK_DMC_MISC)
|
|
GATE_EXTERN(MIF1_GATE_PCLK_PPC_DEBUG)
|
|
GATE_EXTERN(MIF1_GATE_PCLK_PPC_DVFS)
|
|
GATE_EXTERN(MIF1_GATE_PCLK_SYSREG_MIF)
|
|
GATE_EXTERN(MIF1_GATE_PCLK_HPM)
|
|
GATE_EXTERN(MIF1_GATE_ACLK_AXI_ASYNC)
|
|
GATE_EXTERN(MIF1_GATE_PCLK_MIFP)
|
|
GATE_EXTERN(MIF1_GATE_PCLK_PMU_MIF)
|
|
GATE_EXTERN(MIF1_GATE_PCLK_LPDDR4PHY)
|
|
GATE_EXTERN(MIF1_GATE_PCLK_SMC2)
|
|
GATE_EXTERN(MIF1_GATE_SCLK_PROMISE)
|
|
GATE_EXTERN(MIF1_GATE_RCLK_DREX)
|
|
GATE_EXTERN(MIF2_GATE_ACLK_APSCDC)
|
|
GATE_EXTERN(MIF2_GATE_ACLK_PPC_DEBUG)
|
|
GATE_EXTERN(MIF2_GATE_ACLK_PPC_DVFS)
|
|
GATE_EXTERN(MIF2_GATE_ACLK_SMC)
|
|
GATE_EXTERN(MIF2_GATE_PCLK_SMC1)
|
|
GATE_EXTERN(MIF2_GATE_PCLK_DMC_MISC)
|
|
GATE_EXTERN(MIF2_GATE_PCLK_PPC_DEBUG)
|
|
GATE_EXTERN(MIF2_GATE_PCLK_PPC_DVFS)
|
|
GATE_EXTERN(MIF2_GATE_PCLK_SYSREG_MIF)
|
|
GATE_EXTERN(MIF2_GATE_PCLK_HPM)
|
|
GATE_EXTERN(MIF2_GATE_ACLK_AXI_ASYNC)
|
|
GATE_EXTERN(MIF2_GATE_PCLK_MIFP)
|
|
GATE_EXTERN(MIF2_GATE_PCLK_PMU_MIF)
|
|
GATE_EXTERN(MIF2_GATE_PCLK_LPDDR4PHY)
|
|
GATE_EXTERN(MIF2_GATE_PCLK_SMC2)
|
|
GATE_EXTERN(MIF2_GATE_SCLK_PROMISE)
|
|
GATE_EXTERN(MIF2_GATE_RCLK_DREX)
|
|
GATE_EXTERN(MIF3_GATE_ACLK_APSCDC)
|
|
GATE_EXTERN(MIF3_GATE_ACLK_PPC_DEBUG)
|
|
GATE_EXTERN(MIF3_GATE_ACLK_PPC_DVFS)
|
|
GATE_EXTERN(MIF3_GATE_ACLK_SMC)
|
|
GATE_EXTERN(MIF3_GATE_PCLK_SMC1)
|
|
GATE_EXTERN(MIF3_GATE_PCLK_DMC_MISC)
|
|
GATE_EXTERN(MIF3_GATE_PCLK_PPC_DEBUG)
|
|
GATE_EXTERN(MIF3_GATE_PCLK_PPC_DVFS)
|
|
GATE_EXTERN(MIF3_GATE_PCLK_SYSREG_MIF)
|
|
GATE_EXTERN(MIF3_GATE_PCLK_HPM)
|
|
GATE_EXTERN(MIF3_GATE_ACLK_AXI_ASYNC)
|
|
GATE_EXTERN(MIF3_GATE_PCLK_MIFP)
|
|
GATE_EXTERN(MIF3_GATE_PCLK_PMU_MIF)
|
|
GATE_EXTERN(MIF3_GATE_PCLK_LPDDR4PHY)
|
|
GATE_EXTERN(MIF3_GATE_PCLK_SMC2)
|
|
GATE_EXTERN(MIF3_GATE_SCLK_PROMISE)
|
|
GATE_EXTERN(MIF3_GATE_RCLK_DREX)
|
|
GATE_EXTERN(MNGS_GATE_ACLK_ASYNCPACES_MNGS_SCI)
|
|
GATE_EXTERN(MNGS_GATE_ATCLKS_ATB_MNGS3_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLKS_ATB_MNGS2_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLKS_ATB_MNGS1_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLKS_ATB_MNGS0_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_XIU_MNGSX_2x1)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_STM_TXACTOR)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_ATB_BDU_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_ATB_AUD_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_ATB_CAM1_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_ATB_APOLLO3_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_ATB_APOLLO2_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_ATB_APOLLO1_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_ATB_APOLLO0_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLKM_ATB_MNGS3_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLKM_ATB_MNGS2_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLKM_ATB_MNGS1_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLKM_ATB_MNGS0_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_ASYNCAHB_CSSYS_SSS_ACLK)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_ASYNCLHAXI_CSSYS_ETR_ACLK)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_CSSYS_HCLK)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_CSSYS_TRACECLK)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_ASYNCATB_CAM1)
|
|
GATE_EXTERN(MNGS_GATE_ATCLK_ASYNCATB_AUD)
|
|
GATE_EXTERN(MNGS_GATE_PCLKDBG_ASAPBMST_CCORE_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_BDU)
|
|
GATE_EXTERN(MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_CAM1)
|
|
GATE_EXTERN(MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_AUD)
|
|
GATE_EXTERN(MNGS_GATE_PCLKDBG_ASAPBSLV_CSSYS_APOLLO)
|
|
GATE_EXTERN(MNGS_GATE_PCLKDBG_DUMP_PC_MNGS)
|
|
GATE_EXTERN(MNGS_GATE_PCLKDBG_SECJTAG)
|
|
GATE_EXTERN(MNGS_GATE_PCLKDBG_AXIAP)
|
|
GATE_EXTERN(MNGS_GATE_PCLKDBG_CSSYS_CTMCLK)
|
|
GATE_EXTERN(MNGS_GATE_PCLKDBG_CSSYS)
|
|
GATE_EXTERN(MNGS_GATE_PCLKDBG_MNGS)
|
|
GATE_EXTERN(MNGS_GATE_PCLKDBG_ASYNCDAPSLV)
|
|
GATE_EXTERN(MNGS_GATE_PCLK_SYSREG_MNGS)
|
|
GATE_EXTERN(MNGS_GATE_PCLK_STM_TXACTOR)
|
|
GATE_EXTERN(MNGS_GATE_PCLK_XIU_PERI_MNGS_ACLK)
|
|
GATE_EXTERN(MNGS_GATE_PCLK_PMU_MNGS)
|
|
GATE_EXTERN(MNGS_GATE_PCLK_XIU_MNGSSFRX_1x2)
|
|
GATE_EXTERN(MNGS_GATE_PCLK_AXI2APB_MNGS_ACLK)
|
|
GATE_EXTERN(MNGS_GATE_PCLK_HPM_MNGS)
|
|
GATE_EXTERN(MNGS_GATE_SCLK_MNGS)
|
|
GATE_EXTERN(MNGS_GATE_SCLK_PROMISE2_MNGS)
|
|
GATE_EXTERN(MNGS_GATE_SCLK_PROMISE1_MNGS)
|
|
GATE_EXTERN(MNGS_GATE_SCLK_PROMISE0_MNGS)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_ASYNCAPB_JPEG)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_PPMU_MSCL_0)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_SMMU_JPEG)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_SMMU_MSCL_0)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_QE_JPEG)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_QE_MSCL_0)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_XIU_MSCLX_0)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_LH_ASYNC_SI_MSCL_0)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_JPEG)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_MSCL_0)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_SFW_MSCL_0)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_ASYNCAPB_G2D)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_PPMU_MSCL_1)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_SMMU_G2D)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_SMMU_MSCL_1)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_QE_G2D)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_QE_MSCL_1)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_AXI2ACEL)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_XIU_MSCLX_1)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_LH_ASYNC_SI_MSCL_1)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_G2D)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_MSCL_1)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_SFW_MSCL_1)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_LH_ASYNC_MI_MSCLSFR)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_PMU_MSCL)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_SYSREG_MSCL)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_CMU_MSCL)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_PPMU_MSCL_1)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_PPMU_MSCL_0)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_SMMU_G2D)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_SMMU_JPEG)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_SMMU_MSCL_1)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_SMMU_MSCL_0)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_QE_G2D)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_QE_JPEG)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_QE_MSCL_1)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_QE_MSCL_0)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_ASYNCAPB_G2D)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_ASYNCAPB_JPEG)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_MSCL_1)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_MSCL_0)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_AXI2APB_MSCLSFR_1P)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_AXI2APB_MSCLSFR_0P)
|
|
GATE_EXTERN(MSCL_GATE_ACLK_XIU_MSCLSFRX)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_SFW_MSCL_0)
|
|
GATE_EXTERN(MSCL_GATE_PCLK_SFW_MSCL_1)
|
|
GATE_EXTERN(PERIC0_GATE_PCLK_HSI2C11)
|
|
GATE_EXTERN(PERIC0_GATE_PCLK_HSI2C10)
|
|
GATE_EXTERN(PERIC0_GATE_PCLK_HSI2C9)
|
|
GATE_EXTERN(PERIC0_GATE_PCLK_HSI2C5)
|
|
GATE_EXTERN(PERIC0_GATE_PCLK_HSI2C4)
|
|
GATE_EXTERN(PERIC0_GATE_PCLK_HSI2C1)
|
|
GATE_EXTERN(PERIC0_GATE_PCLK_HSI2C0)
|
|
GATE_EXTERN(PERIC0_GATE_PCLK_PWM)
|
|
GATE_EXTERN(PERIC0_GATE_PCLK_ADCIF)
|
|
GATE_EXTERN(PERIC0_GATE_PCLK_UART0)
|
|
GATE_EXTERN(PERIC0_GATE_PCLK_GPIO_BUS0)
|
|
GATE_EXTERN(PERIC0_GATE_PCLK_SYSREG_PERIC0)
|
|
GATE_EXTERN(PERIC0_GATE_PCLK_PMU_PERIC0)
|
|
GATE_EXTERN(PERIC0_GATE_PCLK_CMU_PERIC0)
|
|
GATE_EXTERN(PERIC0_GATE_ACLK_AXI2APB_PERIC0P)
|
|
GATE_EXTERN(PERIC0_GATE_ACLK_AXILHASYNCM_PERIC0)
|
|
GATE_EXTERN(PERIC0_GATE_SCLK_UART0)
|
|
GATE_EXTERN(PERIC0_GATE_SCLK_PWM)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_SPI7)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_SPI6)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_SPI5)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_SPI4)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_SPI3)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_SPI2)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_SPI1)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_SPI0)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_UART5)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_UART4)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_UART3)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_UART2)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_UART1)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_GPIO_ESE)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_GPIO_FF)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_GPIO_TOUCH)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_GPIO_NFC)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_GPIO_PERIC1)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_SYSREG_PERIC1)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_PMU_PERIC1)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_CMU_PERIC1)
|
|
GATE_EXTERN(PERIC1_GATE_ACLK_AXI2APB_PERIC1_2P)
|
|
GATE_EXTERN(PERIC1_GATE_ACLK_AXI2APB_PERIC1_1P)
|
|
GATE_EXTERN(PERIC1_GATE_ACLK_AXI2APB_PERIC1_0P)
|
|
GATE_EXTERN(PERIC1_GATE_ACLK_XIU_PERIC1SFRX)
|
|
GATE_EXTERN(PERIC1_GATE_ACLK_AXILHASYNCM_PERIC1)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_HSI2C14)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_HSI2C13)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_HSI2C12)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_HSI2C8)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_HSI2C7)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_HSI2C6)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_HSI2C3)
|
|
GATE_EXTERN(PERIC1_GATE_PCLK_HSI2C2)
|
|
GATE_EXTERN(PERIC1_GATE_SCLK_SPI0)
|
|
GATE_EXTERN(PERIC1_GATE_SCLK_SPI1)
|
|
GATE_EXTERN(PERIC1_GATE_SCLK_SPI2)
|
|
GATE_EXTERN(PERIC1_GATE_SCLK_SPI3)
|
|
GATE_EXTERN(PERIC1_GATE_SCLK_SPI4)
|
|
GATE_EXTERN(PERIC1_GATE_SCLK_SPI5)
|
|
GATE_EXTERN(PERIC1_GATE_SCLK_SPI6)
|
|
GATE_EXTERN(PERIC1_GATE_SCLK_SPI7)
|
|
GATE_EXTERN(PERIC1_GATE_SCLK_UART1)
|
|
GATE_EXTERN(PERIC1_GATE_SCLK_UART2)
|
|
GATE_EXTERN(PERIC1_GATE_SCLK_UART3)
|
|
GATE_EXTERN(PERIC1_GATE_SCLK_UART4)
|
|
GATE_EXTERN(PERIC1_GATE_SCLK_UART5)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_SFR_APBIF_HDMI_CEC)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_SFR_APBIF_TMU)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_RTC_APBIF)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_MONOCNT_APBIF)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_WDT_APOLLO)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_WDT_MNGS)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_MCT)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_SYSREG_PERIS)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_PMU_PERIS)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_CMU_PERIS)
|
|
GATE_EXTERN(PERIS_GATE_ACLK_AXI2APB_PERIS1)
|
|
GATE_EXTERN(PERIS_GATE_ACLK_AXI2APB_PERIS0)
|
|
GATE_EXTERN(PERIS_GATE_ACLK_XIU_PERIS)
|
|
GATE_EXTERN(PERIS_GATE_ACLK_AXI_LH_ASYNC)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_HPM_APBIF_PERIS)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_15)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_14)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_13)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_12)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_11)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_10)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_9)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_8)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_7)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_6)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_5)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_4)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_3)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_2)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_1)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TZPC_0)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_TOP_RTC)
|
|
GATE_EXTERN(PERIS_GATE_PCLK_SFR_APBIF_CHIPID)
|
|
GATE_EXTERN(PERIS_GATE_SCLK_OTP_CON_TOP)
|
|
GATE_EXTERN(PERIS_GATE_SCLK_CHIPID)
|
|
GATE_EXTERN(PERIS_GATE_SCLK_TMU)
|
|
GATE_EXTERN(PERIS_GATE_SCLK_PROMISE_PERIS)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CCORE_800)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CCORE_264)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CCORE_G3D_800)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CCORE_528)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CCORE_132)
|
|
GATE_EXTERN(TOP_GATE_PCLK_CCORE_66)
|
|
GATE_EXTERN(TOP_GATE_ACLK_BUS0_528)
|
|
GATE_EXTERN(TOP_GATE_ACLK_BUS0_200)
|
|
GATE_EXTERN(TOP_GATE_PCLK_BUS0_132)
|
|
GATE_EXTERN(TOP_GATE_ACLK_BUS1_528)
|
|
GATE_EXTERN(TOP_GATE_PCLK_BUS1_132)
|
|
GATE_EXTERN(TOP_GATE_ACLK_DISP0_0_400)
|
|
GATE_EXTERN(TOP_GATE_ACLK_DISP0_1_400)
|
|
GATE_EXTERN(TOP_GATE_ACLK_DISP1_0_400)
|
|
GATE_EXTERN(TOP_GATE_ACLK_DISP1_1_400)
|
|
GATE_EXTERN(TOP_GATE_ACLK_MFC_600)
|
|
GATE_EXTERN(TOP_GATE_ACLK_MSCL0_528)
|
|
GATE_EXTERN(TOP_GATE_ACLK_MSCL1_528)
|
|
GATE_EXTERN(TOP_GATE_ACLK_IMEM_266)
|
|
GATE_EXTERN(TOP_GATE_ACLK_IMEM_200)
|
|
GATE_EXTERN(TOP_GATE_ACLK_IMEM_100)
|
|
GATE_EXTERN(TOP_GATE_ACLK_FSYS0_200)
|
|
GATE_EXTERN(TOP_GATE_ACLK_FSYS1_200)
|
|
GATE_EXTERN(TOP_GATE_ACLK_PERIS_66)
|
|
GATE_EXTERN(TOP_GATE_ACLK_PERIC0_66)
|
|
GATE_EXTERN(TOP_GATE_ACLK_PERIC1_66)
|
|
GATE_EXTERN(TOP_GATE_ACLK_ISP0_ISP0_528)
|
|
GATE_EXTERN(TOP_GATE_ACLK_ISP0_TPU_400)
|
|
GATE_EXTERN(TOP_GATE_ACLK_ISP0_TREX_528)
|
|
GATE_EXTERN(TOP_GATE_ACLK_ISP0_PXL_ASBS_IS_C_FROM_IS_D)
|
|
GATE_EXTERN(TOP_GATE_ACLK_ISP1_ISP1_468)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CAM0_CSIS0_414)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CAM0_CSIS1_168)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CAM0_CSIS2_234)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CAM0_3AA0_414)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CAM0_3AA1_414)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CAM0_CSIS3_132)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CAM0_TREX_528)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CAM1_ARM_672)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CAM1_TREX_VRA_528)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CAM1_TREX_B_528)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CAM1_BUS_264)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CAM1_PERI_84)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CAM1_CSIS2_414)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CAM1_CSIS3_132)
|
|
GATE_EXTERN(TOP_GATE_ACLK_CAM1_SCL_566)
|
|
GATE_EXTERN(TOP_GATE_SCLK_DISP0_DECON0_ECLK0)
|
|
GATE_EXTERN(TOP_GATE_SCLK_DISP0_DECON0_VCLK0)
|
|
GATE_EXTERN(TOP_GATE_SCLK_DISP0_DECON0_VCLK1)
|
|
GATE_EXTERN(TOP_GATE_SCLK_DISP0_HDMI_AUDIO)
|
|
GATE_EXTERN(TOP_GATE_SCLK_DISP1_DECON1_ECLK0)
|
|
GATE_EXTERN(TOP_GATE_SCLK_DISP1_DECON1_ECLK1)
|
|
GATE_EXTERN(TOP_GATE_SCLK_FSYS0_USBDRD30)
|
|
GATE_EXTERN(TOP_GATE_SCLK_FSYS0_MMC0)
|
|
GATE_EXTERN(TOP_GATE_SCLK_FSYS0_UFSUNIPRO20)
|
|
GATE_EXTERN(TOP_GATE_SCLK_FSYS0_PHY_24M)
|
|
GATE_EXTERN(TOP_GATE_SCLK_FSYS0_UFSUNIPRO_CFG)
|
|
GATE_EXTERN(TOP_GATE_SCLK_FSYS1_MMC2)
|
|
GATE_EXTERN(TOP_GATE_SCLK_FSYS1_UFSUNIPRO20)
|
|
GATE_EXTERN(TOP_GATE_SCLK_FSYS1_PCIE_PHY)
|
|
GATE_EXTERN(TOP_GATE_SCLK_FSYS1_UFSUNIPRO_CFG)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PERIC0_UART0)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PERIC1_SPI0)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PERIC1_SPI1)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PERIC1_SPI2)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PERIC1_SPI3)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PERIC1_SPI4)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PERIC1_SPI5)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PERIC1_SPI6)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PERIC1_SPI7)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PERIC1_UART1)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PERIC1_UART2)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PERIC1_UART3)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PERIC1_UART4)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PERIC1_UART5)
|
|
GATE_EXTERN(TOP_GATE_SCLK_CAM1_ISP_SPI0)
|
|
GATE_EXTERN(TOP_GATE_SCLK_CAM1_ISP_SPI1)
|
|
GATE_EXTERN(TOP_GATE_SCLK_CAM1_ISP_UART)
|
|
GATE_EXTERN(TOP_GATE_SCLK_AP2CP_MIF_PLL_OUT)
|
|
GATE_EXTERN(TOP_GATE_ACLK_PSCDC_400)
|
|
GATE_EXTERN(TOP_GATE_SCLK_BUS_PLL_MNGS)
|
|
GATE_EXTERN(TOP_GATE_SCLK_BUS_PLL_APOLLO)
|
|
GATE_EXTERN(TOP_GATE_SCLK_BUS_PLL_MIF)
|
|
GATE_EXTERN(TOP_GATE_SCLK_BUS_PLL_G3D)
|
|
GATE_EXTERN(TOP_GATE_SCLK_ISP_SENSOR0)
|
|
GATE_EXTERN(TOP_GATE_SCLK_ISP_SENSOR1)
|
|
GATE_EXTERN(TOP_GATE_SCLK_ISP_SENSOR2)
|
|
GATE_EXTERN(TOP_GATE_SCLK_ISP_SENSOR3)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PROMISE_INT)
|
|
GATE_EXTERN(TOP_GATE_SCLK_PROMISE_DISP)
|
|
|
|
|
|
GATE_EXTERN(DISP0_HWACG_DSIM0)
|
|
GATE_EXTERN(DISP0_HWACG_DSIM1)
|
|
GATE_EXTERN(DISP0_HWACG_DSIM2)
|
|
GATE_EXTERN(DISP0_HWACG_HDMI)
|
|
GATE_EXTERN(DISP0_HWACG_HDMI_AUDIO)
|
|
GATE_EXTERN(DISP0_HWACG_DP)
|
|
GATE_EXTERN(DISP0_HWACG_DISP0_MUX)
|
|
GATE_EXTERN(DISP0_HWACG_HDMI_PHY)
|
|
GATE_EXTERN(DISP0_HWACG_DISP1_400)
|
|
GATE_EXTERN(DISP0_HWACG_DECON0)
|
|
GATE_EXTERN(DISP0_HWACG_HPM_APBIF_DISP0)
|
|
GATE_EXTERN(DISP0_HWACG_PROMISE_DISP0)
|
|
GATE_EXTERN(DISP0_HWACG_DPTX_PHY)
|
|
GATE_EXTERN(DISP0_HWACG_MIPI_DPHY_M1S0)
|
|
GATE_EXTERN(DISP0_HWACG_MIPI_DPHY_M4S0)
|
|
GATE_EXTERN(DISP0_HWACG_MIPI_DPHY_M4S4)
|
|
GATE_EXTERN(DISP1_HWACG_DECON1_ECLK_0)
|
|
GATE_EXTERN(DISP1_HWACG_DECON1_ECLK_1)
|
|
GATE_EXTERN(DISP1_HWACG_HPM_APBIF_DISP1)
|
|
GATE_EXTERN(DISP1_HWACG_PROMISE_DISP1)
|
|
GATE_EXTERN(FSYS0_HWACG_USBDRD30)
|
|
GATE_EXTERN(FSYS0_HWACG_QCH_USBDRD30)
|
|
GATE_EXTERN(FSYS0_HWACG_UFS_LINK_EMBEDDED)
|
|
GATE_EXTERN(FSYS0_HWACG_USBHOST20)
|
|
GATE_EXTERN(FSYS0_HWACG_USBHOST20_PHY)
|
|
GATE_EXTERN(FSYS0_HWACG_GPIO_FSYS0)
|
|
GATE_EXTERN(FSYS0_HWACG_HPM_APBIF_FSYS0)
|
|
GATE_EXTERN(FSYS0_HWACG_PROMISE_FSYS0)
|
|
GATE_EXTERN(FSYS1_HWACG_SROMC_FSYS1)
|
|
GATE_EXTERN(FSYS1_HWACG_GPIO_FSYS1)
|
|
GATE_EXTERN(FSYS1_HWACG_HPM_APBIF_FSYS1)
|
|
GATE_EXTERN(FSYS1_HWACG_PROMISE_FSYS1)
|
|
GATE_EXTERN(FSYS1_HWACG_PCIE_RC_LINK_WIFI0)
|
|
GATE_EXTERN(FSYS1_HWACG_PCIE_RC_LINK_WIFI1)
|
|
GATE_EXTERN(FSYS1_HWACG_PCIE_PCS_WIFI0)
|
|
GATE_EXTERN(FSYS1_HWACG_PCIE_PCS_WIFI1)
|
|
GATE_EXTERN(FSYS1_HWACG_PCIE_PHY_FSYS1_WIFI0)
|
|
GATE_EXTERN(FSYS1_HWACG_PCIE_PHY_FSYS1_WIFI1)
|
|
GATE_EXTERN(FSYS1_HWACG_UFS_LINK_SDCARD)
|
|
GATE_EXTERN(IMEM_HWACG_GIC)
|
|
GATE_EXTERN(IMEM_HWACG_ASYNCAHBM_SSS_ATLAS)
|
|
GATE_EXTERN(MFC_HWACG_HPM_APBIF_MFC)
|
|
GATE_EXTERN(MFC_HWACG_PROMISE_MFC)
|
|
GATE_EXTERN(PERIC0_HWACG_GPIO_BUS0)
|
|
GATE_EXTERN(PERIC0_HWACG_UART0)
|
|
GATE_EXTERN(PERIC0_HWACG_ADCIF)
|
|
GATE_EXTERN(PERIC0_HWACG_PWM)
|
|
GATE_EXTERN(PERIC0_HWACG_HSI2C0)
|
|
GATE_EXTERN(PERIC0_HWACG_HSI2C1)
|
|
GATE_EXTERN(PERIC0_HWACG_HSI2C4)
|
|
GATE_EXTERN(PERIC0_HWACG_HSI2C5)
|
|
GATE_EXTERN(PERIC0_HWACG_HSI2C9)
|
|
GATE_EXTERN(PERIC0_HWACG_HSI2C10)
|
|
GATE_EXTERN(PERIC0_HWACG_HSI2C11)
|
|
GATE_EXTERN(PERIC1_HWACG_GPIO_PERIC1)
|
|
GATE_EXTERN(PERIC1_HWACG_GPIO_NFC)
|
|
GATE_EXTERN(PERIC1_HWACG_GPIO_TOUCH)
|
|
GATE_EXTERN(PERIC1_HWACG_GPIO_FF)
|
|
GATE_EXTERN(PERIC1_HWACG_GPIO_ESE)
|
|
GATE_EXTERN(PERIC1_HWACG_UART1)
|
|
GATE_EXTERN(PERIC1_HWACG_UART2)
|
|
GATE_EXTERN(PERIC1_HWACG_UART3)
|
|
GATE_EXTERN(PERIC1_HWACG_UART4)
|
|
GATE_EXTERN(PERIC1_HWACG_UART5)
|
|
GATE_EXTERN(PERIC1_HWACG_SPI0)
|
|
GATE_EXTERN(PERIC1_HWACG_SPI1)
|
|
GATE_EXTERN(PERIC1_HWACG_SPI2)
|
|
GATE_EXTERN(PERIC1_HWACG_SPI3)
|
|
GATE_EXTERN(PERIC1_HWACG_SPI4)
|
|
GATE_EXTERN(PERIC1_HWACG_SPI5)
|
|
GATE_EXTERN(PERIC1_HWACG_SPI6)
|
|
GATE_EXTERN(PERIC1_HWACG_SPI7)
|
|
GATE_EXTERN(PERIC1_HWACG_HSI2C2)
|
|
GATE_EXTERN(PERIC1_HWACG_HSI2C3)
|
|
GATE_EXTERN(PERIC1_HWACG_HSI2C6)
|
|
GATE_EXTERN(PERIC1_HWACG_HSI2C7)
|
|
GATE_EXTERN(PERIC1_HWACG_HSI2C8)
|
|
GATE_EXTERN(PERIC1_HWACG_HSI2C12)
|
|
GATE_EXTERN(PERIC1_HWACG_HSI2C13)
|
|
GATE_EXTERN(PERIC1_HWACG_HSI2C14)
|
|
GATE_EXTERN(PERIS_HWACG_MCT)
|
|
GATE_EXTERN(PERIS_HWACG_WDT_MNGS)
|
|
GATE_EXTERN(PERIS_HWACG_WDT_APOLLO)
|
|
GATE_EXTERN(PERIS_HWACG_RTC_APBIF)
|
|
GATE_EXTERN(PERIS_HWACG_SFR_APBIF_TMU)
|
|
GATE_EXTERN(PERIS_HWACG_SFR_APBIF_HDMI_CEC)
|
|
GATE_EXTERN(PERIS_HWACG_HPM_APBIF_PERIS)
|
|
GATE_EXTERN(PERIS_HWACG_TZPC_0)
|
|
GATE_EXTERN(PERIS_HWACG_TZPC_1)
|
|
GATE_EXTERN(PERIS_HWACG_TZPC_2)
|
|
GATE_EXTERN(PERIS_HWACG_TZPC_3)
|
|
GATE_EXTERN(PERIS_HWACG_TZPC_4)
|
|
GATE_EXTERN(PERIS_HWACG_TZPC_5)
|
|
GATE_EXTERN(PERIS_HWACG_TZPC_6)
|
|
GATE_EXTERN(PERIS_HWACG_TZPC_7)
|
|
GATE_EXTERN(PERIS_HWACG_TZPC_8)
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GATE_EXTERN(PERIS_HWACG_TZPC_9)
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GATE_EXTERN(PERIS_HWACG_TZPC_10)
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GATE_EXTERN(PERIS_HWACG_TZPC_11)
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GATE_EXTERN(PERIS_HWACG_TZPC_12)
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GATE_EXTERN(PERIS_HWACG_TZPC_13)
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GATE_EXTERN(PERIS_HWACG_TZPC_14)
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GATE_EXTERN(PERIS_HWACG_TZPC_15)
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GATE_EXTERN(PERIS_HWACG_TOP_RTC)
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GATE_EXTERN(PERIS_HWACG_OTP_CON_TOP)
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GATE_EXTERN(PERIS_HWACG_SFR_APBIF_CHIPID)
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GATE_EXTERN(PERIS_HWACG_TMU)
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GATE_EXTERN(PERIS_HWACG_CHIPID)
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GATE_EXTERN(PERIS_HWACG_PROMISE_PERIS)
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GATE_EXTERN(CLKOUT_OSCCLK_NFC)
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GATE_EXTERN(CLKOUT_TCXO_26M)
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GATE_EXTERN(CLKOUT_TCXO_IN0)
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GATE_EXTERN(CLKOUT_TCXO_IN1)
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GATE_EXTERN(CLKOUT_TCXO_IN2)
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GATE_EXTERN(CLKOUT_TCXO_IN3)
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GATE_EXTERN(CLKOUT_TCXO_IN4)
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GATE_EXTERN(CLKOUT_CLKOUT0_DISABLE)
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#endif
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