mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-01 08:38:52 +01:00
502 lines
21 KiB
C
502 lines
21 KiB
C
#include "../pwrcal-env.h"
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#include "../pwrcal-rae.h"
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#include "S5E8890-sfrbase.h"
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#include "S5E8890-vclk-internal.h"
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#ifdef PWRCAL_TARGET_LINUX
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#include <soc/samsung/ect_parser.h>
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#else
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#include <mach/ect_parser.h>
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#endif
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#ifndef MHZ
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#define MHZ ((unsigned long long)1000000)
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#endif
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#define __SMC_ALL (DMC_MISC_CCORE_BASE + 0x8000)
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#define __PHY_ALL (DMC_MISC_CCORE_BASE + 0x4000)
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#define __DMC_MISC_ALL (DMC_MISC_CCORE_BASE + 0x0000)
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#define ModeRegAddr ((void *)(__SMC_ALL + 0x0000))
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#define MprMrCtl ((void *)(__SMC_ALL + 0x0004))
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#define ModeRegWrData ((void *)(__SMC_ALL + 0x0008))
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#define DramTiming0_0 ((void *)(__SMC_ALL + 0x0058))
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#define DramTiming1_0 ((void *)(__SMC_ALL + 0x005C))
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#define DramTiming2_0 ((void *)(__SMC_ALL + 0x0060))
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#define DramTiming3_0 ((void *)(__SMC_ALL + 0x0064))
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#define DramTiming4_0 ((void *)(__SMC_ALL + 0x0068))
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#define DramTiming5_0 ((void *)(__SMC_ALL + 0x006C))
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#define DramTiming6_0 ((void *)(__SMC_ALL + 0x0070))
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#define DramTiming7_0 ((void *)(__SMC_ALL + 0x0074))
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#define DramTiming8_0 ((void *)(__SMC_ALL + 0x0078))
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#define DramTiming9_0 ((void *)(__SMC_ALL + 0x007C))
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#define DramDerateTiming0_0 ((void *)(__SMC_ALL + 0x0088))
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#define DramDerateTiming1_0 ((void *)(__SMC_ALL + 0x008C))
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#define Dimm0AutoRefTiming1_0 ((void *)(__SMC_ALL + 0x009C))
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#define Dimm1AutoRefTiming1_0 ((void *)(__SMC_ALL + 0x00A4))
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#define AutoRefTiming2_0 ((void *)(__SMC_ALL + 0x00A8))
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#define PwrMgmtTiming0_0 ((void *)(__SMC_ALL + 0x00B8))
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#define PwrMgmtTiming1_0 ((void *)(__SMC_ALL + 0x00BC))
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#define PwrMgmtTiming2_0 ((void *)(__SMC_ALL + 0x00C0))
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#define PwrMgmtTiming3_0 ((void *)(__SMC_ALL + 0x00C4))
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#define TmrTrnInterval_0 ((void *)(__SMC_ALL + 0x00C8))
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#define DvfsTrnCtl_0 ((void *)(__SMC_ALL + 0x00CC))
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#define TrnTiming0_0 ((void *)(__SMC_ALL + 0x00D0))
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#define TrnTiming1_0 ((void *)(__SMC_ALL + 0x00D4))
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#define TrnTiming2_0 ((void *)(__SMC_ALL + 0x00D8))
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#define DFIDelay1_0 ((void *)(__SMC_ALL + 0x00E0))
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#define DFIDelay2_0 ((void *)(__SMC_ALL + 0x00E4))
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#define DramTiming0_1 ((void *)(__SMC_ALL + 0x0108))
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#define DramTiming1_1 ((void *)(__SMC_ALL + 0x010C))
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#define DramTiming2_1 ((void *)(__SMC_ALL + 0x0110))
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#define DramTiming3_1 ((void *)(__SMC_ALL + 0x0114))
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#define DramTiming4_1 ((void *)(__SMC_ALL + 0x0118))
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#define DramTiming5_1 ((void *)(__SMC_ALL + 0x011C))
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#define DramTiming6_1 ((void *)(__SMC_ALL + 0x0120))
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#define DramTiming7_1 ((void *)(__SMC_ALL + 0x0124))
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#define DramTiming8_1 ((void *)(__SMC_ALL + 0x0128))
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#define DramTiming9_1 ((void *)(__SMC_ALL + 0x012C))
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#define DramDerateTiming0_1 ((void *)(__SMC_ALL + 0x0138))
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#define DramDerateTiming1_1 ((void *)(__SMC_ALL + 0x013C))
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#define Dimm0AutoRefTiming1_1 ((void *)(__SMC_ALL + 0x014C))
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#define Dimm1AutoRefTiming1_1 ((void *)(__SMC_ALL + 0x0154))
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#define AutoRefTiming2_1 ((void *)(__SMC_ALL + 0x0158))
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#define PwrMgmtTiming0_1 ((void *)(__SMC_ALL + 0x0168))
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#define PwrMgmtTiming1_1 ((void *)(__SMC_ALL + 0x016C))
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#define PwrMgmtTiming2_1 ((void *)(__SMC_ALL + 0x0170))
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#define PwrMgmtTiming3_1 ((void *)(__SMC_ALL + 0x0174))
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#define TmrTrnInterval_1 ((void *)(__SMC_ALL + 0x0178))
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#define DvfsTrnCtl_1 ((void *)(__SMC_ALL + 0x017C))
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#define TrnTiming0_1 ((void *)(__SMC_ALL + 0x0180))
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#define TrnTiming1_1 ((void *)(__SMC_ALL + 0x0184))
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#define TrnTiming2_1 ((void *)(__SMC_ALL + 0x0188))
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#define DFIDelay1_1 ((void *)(__SMC_ALL + 0x0190))
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#define DFIDelay2_1 ((void *)(__SMC_ALL + 0x0194))
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#define PHY_DVFS_CON_CH0 ((void *)(LPDDR4_PHY0_BASE + 0x00B8))
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#define PHY_DVFS_CON ((void *)(__PHY_ALL + 0x00B8))
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#define PHY_DVFS0_CON0 ((void *)(__PHY_ALL + 0x00BC))
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#define PHY_DVFS0_CON1 ((void *)(__PHY_ALL + 0x00C4))
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#define PHY_DVFS0_CON2 ((void *)(__PHY_ALL + 0x00CC))
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#define PHY_DVFS0_CON3 ((void *)(__PHY_ALL + 0x00D4))
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#define PHY_DVFS0_CON4 ((void *)(__PHY_ALL + 0x00DC))
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#define PHY_DVFS1_CON0 ((void *)(__PHY_ALL + 0x00C0))
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#define PHY_DVFS1_CON1 ((void *)(__PHY_ALL + 0x00C8))
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#define PHY_DVFS1_CON2 ((void *)(__PHY_ALL + 0x00D0))
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#define PHY_DVFS1_CON3 ((void *)(__PHY_ALL + 0x00D8))
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#define PHY_DVFS1_CON4 ((void *)(__PHY_ALL + 0x00E0))
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#define DMC_MISC_CON0 ((void *)(__DMC_MISC_ALL + 0x0014))
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#define DMC_MISC_CON1 ((void *)(__DMC_MISC_ALL + 0x003C))
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#define MRS_DATA1 ((void *)(__DMC_MISC_ALL + 0x0054))
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enum mif_timing_set_idx {
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MIF_TIMING_SET_0,
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MIF_TIMING_SET_1
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};
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enum smc_dram_mode_register {
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DRAM_MR0,
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DRAM_MR1,
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DRAM_MR2,
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DRAM_MR3,
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DRAM_MR4,
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DRAM_MR5,
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DRAM_MR6,
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DRAM_MR7,
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DRAM_MR8,
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DRAM_MR9,
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DRAM_MR10,
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DRAM_MR11,
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DRAM_MR12,
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DRAM_MR13,
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DRAM_MR14,
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DRAM_MR15,
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DRAM_MR16,
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DRAM_MR17,
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DRAM_MR18,
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DRAM_MR19,
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DRAM_MR20,
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DRAM_MR21,
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DRAM_MR22,
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DRAM_MR23,
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DRAM_MR24,
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DRAM_MR25,
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DRAM_MR32 = 32,
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DRAM_MR40 = 40,
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};
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enum timing_parameter_column {
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DramTiming0,
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DramTiming1,
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DramTiming2,
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DramTiming3,
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DramTiming4,
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DramTiming5,
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DramTiming6,
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DramTiming7,
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DramTiming8,
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DramTiming9,
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DramDerateTiming0,
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DramDerateTiming1,
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Dimm0AutoRefTiming1,
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Dimm1AutoRefTiming1,
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AutoRefTiming2,
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PwrMgmtTiming0,
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PwrMgmtTiming1,
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PwrMgmtTiming2,
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PwrMgmtTiming3,
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TmrTrnInterval,
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DFIDelay1,
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DFIDelay2,
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DvfsTrnCtl,
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TrnTiming0,
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TrnTiming1,
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TrnTiming2,
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DVFSn_CON0,
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DVFSn_CON1,
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DVFSn_CON2,
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DVFSn_CON3,
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DVFSn_CON4,
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DirectCmd_MR1,
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DirectCmd_MR2,
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DirectCmd_MR3,
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DirectCmd_MR11,
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DirectCmd_MR12,
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DirectCmd_MR14,
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DirectCmd_MR22,
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num_of_g_smc_dfs_table_column = TrnTiming2 - DramTiming0 + 1,
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num_of_g_phy_dfs_table_column = DVFSn_CON4 - DVFSn_CON0 + 1,
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num_of_g_dram_dfs_table_column = DirectCmd_MR22 - DirectCmd_MR1 + 1,
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num_of_dram_parameter = num_of_g_smc_dfs_table_column + num_of_g_phy_dfs_table_column + num_of_g_dram_dfs_table_column,
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};
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struct smc_dfs_table {
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unsigned int DramTiming0;
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unsigned int DramTiming1;
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unsigned int DramTiming2;
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unsigned int DramTiming3;
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unsigned int DramTiming4;
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unsigned int DramTiming5;
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unsigned int DramTiming6;
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unsigned int DramTiming7;
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unsigned int DramTiming8;
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unsigned int DramTiming9;
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unsigned int DramDerateTiming0;
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unsigned int DramDerateTiming1;
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unsigned int Dimm0AutoRefTiming1;
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unsigned int Dimm1AutoRefTiming1;
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unsigned int AutoRefTiming2;
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unsigned int PwrMgmtTiming0;
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unsigned int PwrMgmtTiming1;
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unsigned int PwrMgmtTiming2;
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unsigned int PwrMgmtTiming3;
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unsigned int TmrTrnInterval;
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unsigned int DFIDelay1;
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unsigned int DFIDelay2;
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unsigned int DvfsTrnCtl;
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unsigned int TrnTiming0;
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unsigned int TrnTiming1;
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unsigned int TrnTiming2;
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};
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struct phy_dfs_table {
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unsigned int DVFSn_CON0;
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unsigned int DVFSn_CON1;
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unsigned int DVFSn_CON2;
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unsigned int DVFSn_CON3;
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unsigned int DVFSn_CON4;
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};
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struct dram_dfs_table {
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unsigned int DirectCmd_MR1;
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unsigned int DirectCmd_MR2;
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unsigned int DirectCmd_MR3;
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unsigned int DirectCmd_MR11;
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unsigned int DirectCmd_MR12;
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unsigned int DirectCmd_MR14;
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unsigned int DirectCmd_MR22;
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};
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static struct smc_dfs_table *g_smc_dfs_table;
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static struct phy_dfs_table *g_phy_dfs_table;
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static struct dram_dfs_table *g_dram_dfs_table;
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static unsigned long long *mif_freq_to_level;
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static int num_mif_freq_to_level;
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static const unsigned long long mif_freq_to_level_switch[] = {
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/* BUS3_PLL SW 936 */ 936 * MHZ,
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/* BUS0_PLL SW 468 */ 468 * MHZ
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};
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void dmc_misc_direct_dmc_enable(int enable)
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{
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pwrcal_writel(DMC_MISC_CON0, (enable<<24)|(0x2<<20));
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}
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void smc_mode_register_write(int mr, int op)
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{
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pwrcal_writel(ModeRegAddr, ((0x3<<28)|(mr<<20)));
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pwrcal_writel(ModeRegWrData, op);
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pwrcal_writel(MprMrCtl, 0x10);
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}
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static unsigned int convert_to_level(unsigned long long freq)
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{
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int idx;
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int tablesize = num_mif_freq_to_level;
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for (idx = tablesize - 1; idx >= 0; idx--)
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if (freq <= mif_freq_to_level[idx])
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return (unsigned int)idx;
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return 0;
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}
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static unsigned int convert_to_level_switch(unsigned long long freq)
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{
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int idx;
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int tablesize = sizeof(mif_freq_to_level_switch) / sizeof(mif_freq_to_level_switch[0]);
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for (idx = tablesize - 1; idx >= 0; idx--)
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if (freq <= mif_freq_to_level_switch[idx])
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return (unsigned int)idx;
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return 0;
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}
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void pwrcal_dmc_set_dvfs(unsigned long long target_mif_freq, unsigned int timing_set_idx)
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{
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unsigned int uReg;
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unsigned int target_mif_level_idx, target_mif_level_switch_idx;
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unsigned int mr13;
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target_mif_level_idx = convert_to_level(target_mif_freq);
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target_mif_level_switch_idx = convert_to_level_switch(target_mif_freq);
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target_mif_level_switch_idx += num_mif_freq_to_level;
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/* 1. Configure parameter */
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if (timing_set_idx == MIF_TIMING_SET_0) {
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pwrcal_writel(DMC_MISC_CON1, 0x0); //timing_set_sw_r=0x0
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pwrcal_writel(DramTiming0_0, g_smc_dfs_table[target_mif_level_idx].DramTiming0);
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pwrcal_writel(DramTiming1_0, g_smc_dfs_table[target_mif_level_idx].DramTiming1);
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pwrcal_writel(DramTiming2_0, g_smc_dfs_table[target_mif_level_idx].DramTiming2);
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pwrcal_writel(DramTiming3_0, g_smc_dfs_table[target_mif_level_idx].DramTiming3);
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pwrcal_writel(DramTiming4_0, g_smc_dfs_table[target_mif_level_idx].DramTiming4);
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pwrcal_writel(DramTiming5_0, g_smc_dfs_table[target_mif_level_idx].DramTiming5);
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pwrcal_writel(DramTiming6_0, g_smc_dfs_table[target_mif_level_idx].DramTiming6);
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pwrcal_writel(DramTiming7_0, g_smc_dfs_table[target_mif_level_idx].DramTiming7);
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pwrcal_writel(DramTiming8_0, g_smc_dfs_table[target_mif_level_idx].DramTiming8);
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pwrcal_writel(DramTiming9_0, g_smc_dfs_table[target_mif_level_idx].DramTiming9);
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pwrcal_writel(DramDerateTiming0_0, g_smc_dfs_table[target_mif_level_idx].DramDerateTiming0);
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pwrcal_writel(DramDerateTiming1_0, g_smc_dfs_table[target_mif_level_idx].DramDerateTiming1);
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pwrcal_writel(Dimm0AutoRefTiming1_0, g_smc_dfs_table[target_mif_level_idx].Dimm0AutoRefTiming1);
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pwrcal_writel(Dimm1AutoRefTiming1_0, g_smc_dfs_table[target_mif_level_idx].Dimm1AutoRefTiming1);
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pwrcal_writel(AutoRefTiming2_0, g_smc_dfs_table[target_mif_level_idx].AutoRefTiming2);
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pwrcal_writel(PwrMgmtTiming0_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming0);
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pwrcal_writel(PwrMgmtTiming1_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming1);
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pwrcal_writel(PwrMgmtTiming2_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming2);
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pwrcal_writel(PwrMgmtTiming3_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming3);
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pwrcal_writel(TmrTrnInterval_0, g_smc_dfs_table[target_mif_level_idx].TmrTrnInterval);
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pwrcal_writel(DFIDelay1_0, g_smc_dfs_table[target_mif_level_idx].DFIDelay1);
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pwrcal_writel(DFIDelay2_0, g_smc_dfs_table[target_mif_level_idx].DFIDelay2);
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pwrcal_writel(DvfsTrnCtl_0, g_smc_dfs_table[target_mif_level_idx].DvfsTrnCtl);
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pwrcal_writel(TrnTiming0_0, g_smc_dfs_table[target_mif_level_idx].TrnTiming0);
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pwrcal_writel(TrnTiming1_0, g_smc_dfs_table[target_mif_level_idx].TrnTiming1);
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pwrcal_writel(TrnTiming2_0, g_smc_dfs_table[target_mif_level_idx].TrnTiming2);
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uReg = pwrcal_readl((void *)PHY_DVFS_CON_CH0);
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uReg &= ~(0x3<<30);
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uReg |= (0x1<<30); //0x1 = DVFS 1 mode
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pwrcal_writel(PHY_DVFS_CON, uReg);
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pwrcal_writel(PHY_DVFS0_CON0, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON0);
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pwrcal_writel(PHY_DVFS0_CON1, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON1);
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pwrcal_writel(PHY_DVFS0_CON2, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON2);
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pwrcal_writel(PHY_DVFS0_CON3, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON3);
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pwrcal_writel(PHY_DVFS0_CON4, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON4);
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mr13 = (0x1<<7)|(0x0<<6)|(0x0<<5)|(0x1<<3); //FSP-OP=0x1, FSP-WR=0x0, DMD=0x0, VRCG=0x1
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smc_mode_register_write(DRAM_MR13, mr13);
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smc_mode_register_write(DRAM_MR1, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR1);
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smc_mode_register_write(DRAM_MR2, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR2);
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smc_mode_register_write(DRAM_MR3, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR3);
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smc_mode_register_write(DRAM_MR11, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR11);
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smc_mode_register_write(DRAM_MR12, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR12);
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smc_mode_register_write(DRAM_MR14, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR14);
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smc_mode_register_write(DRAM_MR22, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR22);
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mr13 &= ~(0x1<<7); // clear FSP-OP[7]
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pwrcal_writel(MRS_DATA1, mr13);
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} else if (timing_set_idx == MIF_TIMING_SET_1) {
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pwrcal_writel(DMC_MISC_CON1, 0x1); //timing_set_sw_r=0x1
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pwrcal_writel(DramTiming0_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming0);
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pwrcal_writel(DramTiming1_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming1);
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pwrcal_writel(DramTiming2_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming2);
|
|
pwrcal_writel(DramTiming3_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming3);
|
|
pwrcal_writel(DramTiming4_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming4);
|
|
pwrcal_writel(DramTiming5_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming5);
|
|
pwrcal_writel(DramTiming6_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming6);
|
|
pwrcal_writel(DramTiming7_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming7);
|
|
pwrcal_writel(DramTiming8_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming8);
|
|
pwrcal_writel(DramTiming9_1, g_smc_dfs_table[target_mif_level_switch_idx].DramTiming9);
|
|
pwrcal_writel(DramDerateTiming0_1, g_smc_dfs_table[target_mif_level_switch_idx].DramDerateTiming0);
|
|
pwrcal_writel(DramDerateTiming1_1, g_smc_dfs_table[target_mif_level_switch_idx].DramDerateTiming1);
|
|
pwrcal_writel(Dimm0AutoRefTiming1_1, g_smc_dfs_table[target_mif_level_switch_idx].Dimm0AutoRefTiming1);
|
|
pwrcal_writel(Dimm1AutoRefTiming1_1, g_smc_dfs_table[target_mif_level_switch_idx].Dimm1AutoRefTiming1);
|
|
pwrcal_writel(AutoRefTiming2_1, g_smc_dfs_table[target_mif_level_switch_idx].AutoRefTiming2);
|
|
pwrcal_writel(PwrMgmtTiming0_1, g_smc_dfs_table[target_mif_level_switch_idx].PwrMgmtTiming0);
|
|
pwrcal_writel(PwrMgmtTiming1_1, g_smc_dfs_table[target_mif_level_switch_idx].PwrMgmtTiming1);
|
|
pwrcal_writel(PwrMgmtTiming2_1, g_smc_dfs_table[target_mif_level_switch_idx].PwrMgmtTiming2);
|
|
pwrcal_writel(PwrMgmtTiming3_1, g_smc_dfs_table[target_mif_level_switch_idx].PwrMgmtTiming3);
|
|
pwrcal_writel(TmrTrnInterval_1, g_smc_dfs_table[target_mif_level_switch_idx].TmrTrnInterval);
|
|
pwrcal_writel(DFIDelay1_1, g_smc_dfs_table[target_mif_level_switch_idx].DFIDelay1);
|
|
pwrcal_writel(DFIDelay2_1, g_smc_dfs_table[target_mif_level_switch_idx].DFIDelay2);
|
|
pwrcal_writel(DvfsTrnCtl_1, g_smc_dfs_table[target_mif_level_switch_idx].DvfsTrnCtl);
|
|
pwrcal_writel(TrnTiming0_1, g_smc_dfs_table[target_mif_level_switch_idx].TrnTiming0);
|
|
pwrcal_writel(TrnTiming1_1, g_smc_dfs_table[target_mif_level_switch_idx].TrnTiming1);
|
|
pwrcal_writel(TrnTiming2_1, g_smc_dfs_table[target_mif_level_switch_idx].TrnTiming2);
|
|
|
|
uReg = pwrcal_readl(PHY_DVFS_CON_CH0);
|
|
uReg &= ~(0x3<<30);
|
|
uReg |= (0x2<<30); //0x2 = DVFS 2 mode
|
|
pwrcal_writel(PHY_DVFS_CON, uReg);
|
|
|
|
pwrcal_writel(PHY_DVFS1_CON0, g_phy_dfs_table[target_mif_level_switch_idx].DVFSn_CON0);
|
|
pwrcal_writel(PHY_DVFS1_CON1, g_phy_dfs_table[target_mif_level_switch_idx].DVFSn_CON1);
|
|
pwrcal_writel(PHY_DVFS1_CON2, g_phy_dfs_table[target_mif_level_switch_idx].DVFSn_CON2);
|
|
pwrcal_writel(PHY_DVFS1_CON3, g_phy_dfs_table[target_mif_level_switch_idx].DVFSn_CON3);
|
|
pwrcal_writel(PHY_DVFS1_CON4, g_phy_dfs_table[target_mif_level_switch_idx].DVFSn_CON4);
|
|
|
|
mr13 = (0x0<<7)|(0x1<<6)|(0x0<<5)|(0x1<<3); //FSP-OP=0x0, FSP-WR=0x1, DMD=0x0, VRCG=0x1
|
|
smc_mode_register_write(DRAM_MR13, mr13);
|
|
smc_mode_register_write(DRAM_MR1, g_dram_dfs_table[target_mif_level_switch_idx].DirectCmd_MR1);
|
|
smc_mode_register_write(DRAM_MR2, g_dram_dfs_table[target_mif_level_switch_idx].DirectCmd_MR2);
|
|
smc_mode_register_write(DRAM_MR3, g_dram_dfs_table[target_mif_level_switch_idx].DirectCmd_MR3);
|
|
smc_mode_register_write(DRAM_MR11, g_dram_dfs_table[target_mif_level_switch_idx].DirectCmd_MR11);
|
|
smc_mode_register_write(DRAM_MR12, g_dram_dfs_table[target_mif_level_switch_idx].DirectCmd_MR12);
|
|
smc_mode_register_write(DRAM_MR14, g_dram_dfs_table[target_mif_level_switch_idx].DirectCmd_MR14);
|
|
smc_mode_register_write(DRAM_MR22, g_dram_dfs_table[target_mif_level_switch_idx].DirectCmd_MR22);
|
|
|
|
mr13 &= ~(0x1<<7); // clear FSP-OP[7]
|
|
mr13 |= (0x1<<7); // set FSP-OP[7]=0x1
|
|
pwrcal_writel(MRS_DATA1, mr13);
|
|
} else {
|
|
pr_err("wrong DMC timing set selection on DVFS\n");
|
|
return;
|
|
}
|
|
}
|
|
|
|
|
|
void dfs_dram_param_init(void)
|
|
{
|
|
int i;
|
|
void *dram_block;
|
|
int memory_size = 3; // means 3GB
|
|
struct ect_timing_param_size *size;
|
|
|
|
dram_block = ect_get_block(BLOCK_TIMING_PARAM);
|
|
if (dram_block == NULL)
|
|
return;
|
|
|
|
size = ect_timing_param_get_size(dram_block, memory_size);
|
|
if (size == NULL)
|
|
return;
|
|
|
|
if (num_of_g_smc_dfs_table_column + num_of_g_phy_dfs_table_column + num_of_g_dram_dfs_table_column != size->num_of_timing_param)
|
|
return;
|
|
|
|
g_smc_dfs_table = kzalloc(sizeof(struct smc_dfs_table) * num_of_g_smc_dfs_table_column * size->num_of_level, GFP_KERNEL);
|
|
if (g_smc_dfs_table == NULL)
|
|
return;
|
|
|
|
g_phy_dfs_table = kzalloc(sizeof(struct phy_dfs_table) * num_of_g_phy_dfs_table_column * size->num_of_level, GFP_KERNEL);
|
|
if (g_phy_dfs_table == NULL)
|
|
return;
|
|
|
|
g_dram_dfs_table = kzalloc(sizeof(struct dram_dfs_table) * num_of_g_dram_dfs_table_column * size->num_of_level, GFP_KERNEL);
|
|
if (g_dram_dfs_table == NULL)
|
|
return;
|
|
|
|
for (i = 0; i < size->num_of_level; ++i) {
|
|
g_smc_dfs_table[i].DramTiming0 = size->timing_parameter[i * num_of_dram_parameter + DramTiming0];
|
|
g_smc_dfs_table[i].DramTiming1 = size->timing_parameter[i * num_of_dram_parameter + DramTiming1];
|
|
g_smc_dfs_table[i].DramTiming2 = size->timing_parameter[i * num_of_dram_parameter + DramTiming2];
|
|
g_smc_dfs_table[i].DramTiming3 = size->timing_parameter[i * num_of_dram_parameter + DramTiming3];
|
|
g_smc_dfs_table[i].DramTiming4 = size->timing_parameter[i * num_of_dram_parameter + DramTiming4];
|
|
g_smc_dfs_table[i].DramTiming5 = size->timing_parameter[i * num_of_dram_parameter + DramTiming5];
|
|
g_smc_dfs_table[i].DramTiming6 = size->timing_parameter[i * num_of_dram_parameter + DramTiming6];
|
|
g_smc_dfs_table[i].DramTiming7 = size->timing_parameter[i * num_of_dram_parameter + DramTiming7];
|
|
g_smc_dfs_table[i].DramTiming8 = size->timing_parameter[i * num_of_dram_parameter + DramTiming8];
|
|
g_smc_dfs_table[i].DramTiming9 = size->timing_parameter[i * num_of_dram_parameter + DramTiming9];
|
|
g_smc_dfs_table[i].DramDerateTiming0 = size->timing_parameter[i * num_of_dram_parameter + DramDerateTiming0];
|
|
g_smc_dfs_table[i].DramDerateTiming1 = size->timing_parameter[i * num_of_dram_parameter + DramDerateTiming1];
|
|
g_smc_dfs_table[i].Dimm0AutoRefTiming1 = size->timing_parameter[i * num_of_dram_parameter + Dimm0AutoRefTiming1];
|
|
g_smc_dfs_table[i].Dimm1AutoRefTiming1 = size->timing_parameter[i * num_of_dram_parameter + Dimm1AutoRefTiming1];
|
|
g_smc_dfs_table[i].AutoRefTiming2 = size->timing_parameter[i * num_of_dram_parameter + AutoRefTiming2];
|
|
g_smc_dfs_table[i].PwrMgmtTiming0 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming0];
|
|
g_smc_dfs_table[i].PwrMgmtTiming1 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming1];
|
|
g_smc_dfs_table[i].PwrMgmtTiming2 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming2];
|
|
g_smc_dfs_table[i].PwrMgmtTiming3 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming3];
|
|
g_smc_dfs_table[i].TmrTrnInterval = size->timing_parameter[i * num_of_dram_parameter + TmrTrnInterval];
|
|
g_smc_dfs_table[i].DFIDelay1 = size->timing_parameter[i * num_of_dram_parameter + DFIDelay1];
|
|
g_smc_dfs_table[i].DFIDelay2 = size->timing_parameter[i * num_of_dram_parameter + DFIDelay2];
|
|
g_smc_dfs_table[i].DvfsTrnCtl = size->timing_parameter[i * num_of_dram_parameter + DvfsTrnCtl];
|
|
g_smc_dfs_table[i].TrnTiming0 = size->timing_parameter[i * num_of_dram_parameter + TrnTiming0];
|
|
g_smc_dfs_table[i].TrnTiming1 = size->timing_parameter[i * num_of_dram_parameter + TrnTiming1];
|
|
g_smc_dfs_table[i].TrnTiming2 = size->timing_parameter[i * num_of_dram_parameter + TrnTiming2];
|
|
|
|
g_phy_dfs_table[i].DVFSn_CON0 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON0];
|
|
g_phy_dfs_table[i].DVFSn_CON1 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON1];
|
|
g_phy_dfs_table[i].DVFSn_CON2 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON2];
|
|
g_phy_dfs_table[i].DVFSn_CON3 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON3];
|
|
g_phy_dfs_table[i].DVFSn_CON4 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON4];
|
|
|
|
g_dram_dfs_table[i].DirectCmd_MR1 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR1];
|
|
g_dram_dfs_table[i].DirectCmd_MR2 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR2];
|
|
g_dram_dfs_table[i].DirectCmd_MR3 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR3];
|
|
g_dram_dfs_table[i].DirectCmd_MR11 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR11];
|
|
g_dram_dfs_table[i].DirectCmd_MR12 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR12];
|
|
g_dram_dfs_table[i].DirectCmd_MR14 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR14];
|
|
g_dram_dfs_table[i].DirectCmd_MR22 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR22];
|
|
}
|
|
}
|
|
|
|
void dfs_mif_level_init(void)
|
|
{
|
|
int i;
|
|
void *dvfs_block;
|
|
struct ect_dvfs_domain *domain;
|
|
|
|
dvfs_block = ect_get_block(BLOCK_DVFS);
|
|
if (dvfs_block == NULL)
|
|
return;
|
|
|
|
domain = ect_dvfs_get_domain(dvfs_block, vclk_dvfs_mif.vclk.name);
|
|
if (domain == NULL)
|
|
return;
|
|
|
|
mif_freq_to_level = kzalloc(sizeof(unsigned long long) * domain->num_of_level, GFP_KERNEL);
|
|
if (mif_freq_to_level == NULL)
|
|
return;
|
|
|
|
num_mif_freq_to_level = domain->num_of_level;
|
|
|
|
for (i = 0; i < domain->num_of_level; ++i)
|
|
mif_freq_to_level[i] = domain->list_level[i].level * KHZ;
|
|
}
|
|
|
|
void dfs_dram_init(void)
|
|
{
|
|
dfs_dram_param_init();
|
|
dfs_mif_level_init();
|
|
}
|