mirror of
https://github.com/AetherDroid/vendor_samsung_universal7570-common.git
synced 2025-09-10 09:22:45 -04:00
move to proprietary
This commit is contained in:
Prabhjot Singh
parent
aa6772b176
commit
c0b61d9a22
1694 changed files with 0 additions and 0 deletions
234
universal7570-common/proprietary/vendor/etc/wifi/indoorchannel.info
vendored
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234
universal7570-common/proprietary/vendor/etc/wifi/indoorchannel.info
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VER 1.2
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||||
AD 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
AE 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
AF 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
AG 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
AI 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
AL 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
AN 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
AO 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
AQ 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
AR 36 40 44 48 52 56 60 64 100 104 108 112 116 132 136 140 144
|
||||
AS 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
AT 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
AU 36 40 44 48 52 56 60 64 100 104 108 112 116 132 136 140 144
|
||||
AW 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
AX 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
AZ 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
BA 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
BB 36 40 44 48 52 56 60 64
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||||
BE 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
BF 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
BG 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
BH 36 40 44 48 52 56 60 64
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||||
BI 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
BJ 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
BM 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
BN 52 56 60 64
|
||||
BO 52 56 60 64 149 153 157 161 165
|
||||
BR 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
BS 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
BT 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
BV 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
BW 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
BY 52 56 60 64 132 136 140
|
||||
BZ 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
CA 36 40 44 48 52 56 60 64 100 104 108 112 116 132 136 140 144
|
||||
CC 36 40 44 48 52 56 60 64 100 104 108 112 116 132 136 140 144
|
||||
CD 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
CF 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
CG 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
CH 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
CI 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
CK 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
CL 36 40 44 48 52 56 60 64
|
||||
CM 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
CN 36 40 44 48 52 56 60 64
|
||||
CO 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
CR 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
CU 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
CV 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
CX 52 56 60 64 100 104 108 112 116 132 136 140 144
|
||||
CY 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
CZ 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
DE 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
DK 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
DM 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
DO 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
DZ 52 56 60 64 100 104 108 112 116 120 124 128 132
|
||||
EC 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
EE 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
EG 36 40 44 48 52 56 60 64
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||||
EH 52 56 60 64
|
||||
ES 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
ET 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
FI 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
FJ 36 40 44 48 52 56 60 64 100 104 108 112 116 132 136 140 144
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||||
FK 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
FM 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
FO 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
FR 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
GA 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
GB 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
GD 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
GE 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
GF 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
GG 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
GH 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
GI 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
GL 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
GM 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
GN 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
GP 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
GQ 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
GR 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
GS 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
GT 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
GU 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
GW 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
HK 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
HM 36 40 44 48 52 56 60 64 100 104 108 112 116 132 136 140 144
|
||||
HN 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
HR 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
HT 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
HU 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
IE 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
IL 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
IM 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
IN 36 40 44 48 52 56 60 64 149 153 157 161
|
||||
IO 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
IQ 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
IR 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
IS 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
IT 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
JE 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
JP 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
KE 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
KG 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
KH 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
KI 52 56 60 64 100 104 108 112 116 132 136 140 144
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||||
KM 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
KN 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
KP 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
KR 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
KW 36 40 44 48 52 56 60 64
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||||
KY 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
KZ 52 56 60 64 132 136 140
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||||
LA 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
LB 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
LC 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
LI 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
LK 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
LR 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
LS 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
LT 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
LU 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
LV 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
LY 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
MA 36 40 44 48 52 56 60 64
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||||
MC 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
MD 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
ME 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
MG 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
MH 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
MK 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
ML 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
MM 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
MN 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
MO 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
MP 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
MQ 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
MR 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
MS 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
MT 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
|
||||
MU 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
MV 36 40 44 48 52 56 60 64
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||||
MW 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
|
||||
MX 52 56 60 64 100 104 108 112 116 132 136 140 144
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||||
MY 52 56 60 64 100 104 108 112 116 120 124 128
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||||
MZ 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
NA 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
NC 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
NE 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
NF 36 40 44 48 52 56 60 64 100 104 108 112 116 132 136 140 144
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||||
NG 52 56 60 64
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||||
NI 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
NL 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
NO 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
NP 52 56 60 64
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||||
NR 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
NU 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
NZ 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
OM 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
PA 36 40 44 48 52 56 60 64
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||||
PE 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
PF 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
PG 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
PH 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
PL 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
PM 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
PN 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
PR 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
PS 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
PT 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
PW 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
PY 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
QA 149 153 157 161 165
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||||
RE 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
RO 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
RS 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
RU 52 56 60 64 132 136 140
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||||
RW 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
SA 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
SC 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
SD 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
SE 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
SG 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
SH 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
SI 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
SJ 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
SK 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
SL 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
SM 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
SN 52 56 60 64
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||||
SR 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
SS 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
ST 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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SV 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
SX 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
SY 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
SZ 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
TC 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
TD 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
TF 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
TG 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
TH 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
TJ 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
TK 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
TL 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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TM 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
TN 52 56 60 64
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TR 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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TT 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
TW 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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TZ 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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||||
UA 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132
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||||
UG 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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UM 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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US 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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UY 36 40 44 48 52 56 60 64
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UZ 52 56 60 64
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VA 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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VC 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
VE 36 40 44 48 52 56 60 64
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VG 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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VI 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
VN 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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VU 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
WF 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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WS 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
YE 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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||||
YT 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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ZA 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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ZM 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 144
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ZW 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140
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0
universal7570-common/proprietary/vendor/etc/wifi/mx
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0
universal7570-common/proprietary/vendor/etc/wifi/mx
vendored
Normal file
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140.bin
vendored
Normal file
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140.bin
vendored
Normal file
Binary file not shown.
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140/conf/bluetooth/bt.hcf
vendored
Normal file
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140/conf/bluetooth/bt.hcf
vendored
Normal file
Binary file not shown.
1
universal7570-common/proprietary/vendor/etc/wifi/mx140/conf/bluetooth/platform.txt
vendored
Normal file
1
universal7570-common/proprietary/vendor/etc/wifi/mx140/conf/bluetooth/platform.txt
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on5
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BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140/conf/wlan/hydra_config.sdb
vendored
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BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140/conf/wlan/hydra_config.sdb
vendored
Normal file
Binary file not shown.
1
universal7570-common/proprietary/vendor/etc/wifi/mx140/conf/wlan/platform.txt
vendored
Normal file
1
universal7570-common/proprietary/vendor/etc/wifi/mx140/conf/wlan/platform.txt
vendored
Normal file
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on5
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BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140/conf/wlan/wlan.hcf
vendored
Normal file
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140/conf/wlan/wlan.hcf
vendored
Normal file
Binary file not shown.
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140/conf/wlan/wlan_t.hcf
vendored
Normal file
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140/conf/wlan/wlan_t.hcf
vendored
Normal file
Binary file not shown.
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/common/log-strings.bin
vendored
Normal file
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/common/log-strings.bin
vendored
Normal file
Binary file not shown.
56
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/hardware/moredump/Memory.xsd
vendored
Normal file
56
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/hardware/moredump/Memory.xsd
vendored
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<?xml version="1.0" encoding="utf-8"?>
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<xs:schema attributeFormDefault="unqualified" elementFormDefault="qualified" xmlns:xs="http://www.w3.org/2001/XMLSchema">
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<!-- Define an address range -->
|
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<xs:complexType name="addressRange">
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<xs:attribute name="startAddr" type="xs:hexBinary" use="required" />
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<xs:attribute name="endAddr" type="xs:hexBinary" use="required" />
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</xs:complexType>
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|
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<!-- Define a region -->
|
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<xs:complexType name="region">
|
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<xs:complexContent>
|
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<xs:extension base="addressRange">
|
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<xs:attribute name="name" type="xs:string" use="optional" />
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<xs:attribute name="comment" type="xs:string" use="optional" />
|
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</xs:extension>
|
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</xs:complexContent>
|
||||
</xs:complexType>
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|
||||
<xs:element name="memory">
|
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<xs:complexType>
|
||||
<xs:sequence>
|
||||
<xs:choice maxOccurs="unbounded">
|
||||
<!-- Define the mmap range -->
|
||||
<!-- Memory regions outwith R4/M4 that fall within the mmap range will use the mmap interface (android only) -->
|
||||
<xs:element name="mmap" minOccurs="1" maxOccurs="1" type ="addressRange" />
|
||||
|
||||
<!-- Memory that will be read over any available interface, mmap, r4 or m4 (in that order) -->
|
||||
<!-- This element can occur before R4 and/or between R4/M4 and/or after M4-->
|
||||
<xs:element minOccurs="0" maxOccurs="unbounded" name="region" type="region" />
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||||
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||||
<!-- Memory specific to (and will only be read via) R4 -->
|
||||
<!-- will also be wrapped with IF (CPUIS("CortexR4")) in CMM -->
|
||||
<xs:element name="R4" minOccurs="0" maxOccurs="1">
|
||||
<xs:complexType>
|
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<xs:sequence>
|
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<xs:element minOccurs="0" maxOccurs="unbounded" name="region" type="region" />
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</xs:sequence>
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</xs:complexType>
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</xs:element>
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||||
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||||
<!-- Memory specific to (and will only be read via) M4 -->
|
||||
<!-- will also be wrapped with IF (CPUIS("CortexM4")) in CMM -->
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||||
<xs:element name="M4" minOccurs="0" maxOccurs="1">
|
||||
<xs:complexType>
|
||||
<xs:sequence>
|
||||
<xs:element minOccurs="0" maxOccurs="unbounded" name="region" type="region" />
|
||||
</xs:sequence>
|
||||
</xs:complexType>
|
||||
</xs:element>
|
||||
|
||||
</xs:choice>
|
||||
</xs:sequence>
|
||||
</xs:complexType>
|
||||
</xs:element>
|
||||
</xs:schema>
|
||||
150
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/hardware/moredump/Registers.xsd
vendored
Normal file
150
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/hardware/moredump/Registers.xsd
vendored
Normal file
|
|
@ -0,0 +1,150 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<xs:schema attributeFormDefault="unqualified"
|
||||
elementFormDefault="qualified"
|
||||
xmlns:xs="http://www.w3.org/2001/XMLSchema">
|
||||
|
||||
<!-- Define the permissible memory classes -->
|
||||
<xs:simpleType name="class">
|
||||
<xs:restriction base="xs:string">
|
||||
<!-- Data memory -->
|
||||
<xs:enumeration value="D" />
|
||||
<!-- Data memory (supervisor access) -->
|
||||
<xs:enumeration value="S" />
|
||||
<!-- CP14 -->
|
||||
<xs:enumeration value="C14" />
|
||||
<!-- CP15 -->
|
||||
<xs:enumeration value="C15" />
|
||||
</xs:restriction>
|
||||
</xs:simpleType>
|
||||
|
||||
<!-- Define the permissible set of register widths in octets -->
|
||||
<xs:simpleType name="width">
|
||||
<xs:restriction base="xs:unsignedByte">
|
||||
<xs:enumeration value="1" />
|
||||
<xs:enumeration value="2" />
|
||||
<xs:enumeration value="4" />
|
||||
</xs:restriction>
|
||||
</xs:simpleType>
|
||||
|
||||
<!-- Define the read/write capability flags -->
|
||||
<xs:simpleType name="rw_flags">
|
||||
<xs:restriction base="xs:string">
|
||||
<xs:enumeration value="R" />
|
||||
<xs:enumeration value="W" />
|
||||
<xs:enumeration value="RW" />
|
||||
</xs:restriction>
|
||||
</xs:simpleType>
|
||||
|
||||
<!-- Define a basic register -->
|
||||
<xs:complexType name="register">
|
||||
<xs:attribute name="addr" type="xs:hexBinary" use="required" />
|
||||
<xs:attribute name="width" type="width" use="required" />
|
||||
<xs:attribute name="rw_flags" type="rw_flags" use="required" />
|
||||
<xs:attribute name="name" type="xs:string" use="optional" />
|
||||
<xs:attribute name="comment" type="xs:string" use="optional" />
|
||||
</xs:complexType>
|
||||
|
||||
<!-- Define a bit-field within a register -->
|
||||
<xs:complexType name="registerfield">
|
||||
<xs:complexContent>
|
||||
<xs:extension base="register">
|
||||
<xs:attribute name="shift" type="xs:unsignedShort" use="required" />
|
||||
<xs:attribute name="mask" type="xs:string" use="required" />
|
||||
</xs:extension>
|
||||
</xs:complexContent>
|
||||
</xs:complexType>
|
||||
|
||||
<!-- Define an index register -->
|
||||
<xs:complexType name="indexregister">
|
||||
<xs:complexContent>
|
||||
<xs:extension base="register">
|
||||
<xs:choice minOccurs="1" maxOccurs="1">
|
||||
<!-- Either an absolute count -->
|
||||
<xs:element name="count">
|
||||
<xs:complexType>
|
||||
<xs:attribute name="value" type="xs:unsignedShort" use="required" />
|
||||
</xs:complexType>
|
||||
</xs:element>
|
||||
<!-- or obtained indirectly from a register field -->
|
||||
<xs:element name="countfrom" type="registerfield" />
|
||||
</xs:choice>
|
||||
</xs:extension>
|
||||
</xs:complexContent>
|
||||
</xs:complexType>
|
||||
|
||||
<!-- Define a table -->
|
||||
<xs:complexType name="table">
|
||||
<xs:sequence>
|
||||
<!-- The one and only index register -->
|
||||
<xs:element name="indexregister" type="indexregister" minOccurs="1" maxOccurs="1" />
|
||||
<!-- and at least 1 other register in the table -->
|
||||
<xs:element name="register" type="register" minOccurs="1" maxOccurs="unbounded" />
|
||||
</xs:sequence>
|
||||
<xs:attribute name="name" type="xs:string" use="required" />
|
||||
</xs:complexType>
|
||||
|
||||
|
||||
<!-- Define a block -->
|
||||
<xs:complexType name="block">
|
||||
<!-- containing a number of tables or registers -->
|
||||
<xs:choice maxOccurs="unbounded">
|
||||
<xs:element name="register" type="register" />
|
||||
<xs:element name="table" type="table" />
|
||||
</xs:choice>
|
||||
<xs:attribute name="name" type="xs:string" use="optional" />
|
||||
<xs:attribute name="comment" type="xs:string" use="optional" />
|
||||
<xs:attribute name="description" type="xs:string" use="optional" />
|
||||
</xs:complexType>
|
||||
|
||||
<!-- Define a memory-mapped region -->
|
||||
<xs:complexType name="memory">
|
||||
<xs:choice maxOccurs="unbounded">
|
||||
<xs:element minOccurs="1" maxOccurs="unbounded" name="register" type="register" />
|
||||
<xs:element name="block" type="block" />
|
||||
<xs:element name="table" type="table" />
|
||||
</xs:choice>
|
||||
<xs:attribute name="name" type="xs:string" use="required" />
|
||||
<xs:attribute name="class" type="class" use="required"/>
|
||||
</xs:complexType>
|
||||
|
||||
<!-- Define a Cortex R4 co-processor -->
|
||||
<xs:complexType name="coprocessor">
|
||||
<xs:sequence>
|
||||
<xs:element name="block" minOccurs="1" maxOccurs="unbounded">
|
||||
<xs:complexType>
|
||||
<xs:choice maxOccurs="unbounded">
|
||||
<xs:element name="register" type="register" />
|
||||
<xs:element name="table" type="table" />
|
||||
</xs:choice>
|
||||
<xs:attribute name="name" type="xs:string" use="required" />
|
||||
</xs:complexType>
|
||||
</xs:element>
|
||||
</xs:sequence>
|
||||
<xs:attribute name="name" type="xs:string" use="required" />
|
||||
<xs:attribute name="id" type="class" use="required" />
|
||||
</xs:complexType>
|
||||
|
||||
<!-- Define a subsystem, top-level element for 'digits' registers -->
|
||||
<xs:element name="subsystem">
|
||||
<xs:complexType>
|
||||
<xs:sequence>
|
||||
<!-- containing a number of blocks -->
|
||||
<xs:element minOccurs="1" maxOccurs="unbounded" name="block" type="block" />
|
||||
</xs:sequence>
|
||||
<xs:attribute name="name" type="xs:string" use="required" />
|
||||
</xs:complexType>
|
||||
</xs:element>
|
||||
|
||||
<!-- Define a Cortex processor -->
|
||||
<xs:element name="processor">
|
||||
<xs:complexType>
|
||||
<xs:choice minOccurs="1" maxOccurs="unbounded">
|
||||
<xs:element name="coprocessor" type="coprocessor" />
|
||||
<xs:element name="memory" type="memory" />
|
||||
</xs:choice>
|
||||
<xs:attribute name="name" type="xs:string" use="required" />
|
||||
<xs:attribute name="comment" type="xs:string" use="required" />
|
||||
</xs:complexType>
|
||||
</xs:element>
|
||||
|
||||
</xs:schema>
|
||||
241
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/hardware/moredump/bt_registers.xml
vendored
Normal file
241
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/hardware/moredump/bt_registers.xml
vendored
Normal file
|
|
@ -0,0 +1,241 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!--
|
||||
(c) SCSC 2015-2016 autogenerated by moredump.py as part of 'drun prep'.
|
||||
Changes made to this file may cause incorrect behaviour and will be lost if it is regenerated.
|
||||
|
||||
XML file defining registers for bt subsystem moredump
|
||||
Chip hash: db95
|
||||
|
||||
|
||||
-->
|
||||
|
||||
<subsystem xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.samsung.com Registers.xsd"
|
||||
name="bt">
|
||||
<block name="bt_audio_pipe" comment="">
|
||||
<register addr="40330000" rw_flags="RW" width="4" name="AUDIO_PIPE_CONFIG" comment="Config register for audio pipe"/>
|
||||
<register addr="40330004" rw_flags="RW" width="4" name="AUDIO_PIPE_FREQ" comment="Config register for frequency select of audio pipe. Rising and falling halves are specified independently to allow more accurate selection of frequencies"/>
|
||||
</block>
|
||||
<block name="bt_bb_clkgen" comment="">
|
||||
<register addr="40300000" rw_flags="R" width="4" name="CLKGEN_SYSTEM_TIME" comment="The current microsecond system time."/>
|
||||
<register addr="40300004" rw_flags="RW" width="4" name="CLKGEN_ENABLES" comment="This register enables the core clocks on the chip. When a corresponding bit is set, the clock is enabled, regardless of any corresponding clock request"/>
|
||||
</block>
|
||||
<block name="bt_bb_modem" comment="">
|
||||
<register addr="40310000" rw_flags="RW" width="4" name="BT_DEBUG_MUX" comment="BT Debug Mux Selection."/>
|
||||
<register addr="40310004" rw_flags="RW" width="4" name="BT_WBREE_CONFIG" comment="Enables Wibree featues."/>
|
||||
<register addr="40310008" rw_flags="RW" width="4" name="BT_WBREE_CONFIG_EXT" comment="Extra Wibree controls."/>
|
||||
<register addr="4031000c" rw_flags="RW" width="4" name="BT_WBREE_CONFIG_EXTENDED" comment="Extended length Wibree controls."/>
|
||||
<register addr="40310010" rw_flags="RW" width="4" name="BT_WBREE_CONFIG_FUTURE" comment="Future Wibree controls."/>
|
||||
<register addr="40310014" rw_flags="RW" width="4" name="BT_WBREE_LEN_PARAMS" comment="Configure BLE length paramters"/>
|
||||
<register addr="40310018" rw_flags="RW" width="1" name="BT_WBREE_ADV_LEN_PARAMS" comment="Configure BLE length paramters"/>
|
||||
<register addr="4031001c" rw_flags="RW" width="4" name="BT_LEN_PARAMS" comment="Configure BR, EDR length paramters"/>
|
||||
<register addr="40310020" rw_flags="RW" width="2" name="BT_ANTPLUS_CONFIG" comment="Enables ANT+ featues."/>
|
||||
<register addr="40310024" rw_flags="RW" width="4" name="BT_LLR_TRIGGER_LSW" comment="LLR Access Code to transmit or receive LSW"/>
|
||||
<register addr="40310028" rw_flags="RW" width="4" name="BT_LLR_TRIGGER_MSW" comment="LLR Access Code to transmit or receive MSW"/>
|
||||
<register addr="4031002c" rw_flags="RW" width="4" name="BT_AES_ACL_CFG_1" comment="Enable BT AES and AES CCM modes on ACL packets"/>
|
||||
<register addr="40310030" rw_flags="RW" width="4" name="BT_AES_ACL_CFG_2" comment="Enable BT AES and AES CCM modes on ACL packets"/>
|
||||
<register addr="40310034" rw_flags="RW" width="4" name="BT_AES_ACL_CFG_3" comment="Enable BT AES and AES CCM modes on ACL packets"/>
|
||||
<register addr="40310038" rw_flags="RW" width="4" name="BT_AES_ACL23_CFG_1" comment="Enable BT AES and AES CCM modes on EDR ACL packets"/>
|
||||
<register addr="4031003c" rw_flags="RW" width="4" name="BT_AES_ACL23_CFG_2" comment="Enable BT AES and AES CCM modes on EDR ACL packets"/>
|
||||
<register addr="40310040" rw_flags="RW" width="4" name="BT_AES_ACL23_CFG_3" comment="Enable BT AES and AES CCM modes on EDR ACL packets"/>
|
||||
<register addr="40310044" rw_flags="RW" width="2" name="BT_AES_ACL23_CFG_4" comment="Enable BT AES and AES CCM modes on EDR ACL packets"/>
|
||||
<register addr="40310048" rw_flags="RW" width="4" name="BT_AES_ESCO_CFG" comment="Enable BT AES modes on ESCO packets"/>
|
||||
<register addr="4031004c" rw_flags="RW" width="4" name="BT_AES_ESCO23_CFG" comment="Enable BT AES modes on EDR ESCO packets"/>
|
||||
<register addr="40310050" rw_flags="RW" width="2" name="BT_AES_MISC41_CFG" comment="Miscellaneous BT AES config"/>
|
||||
<register addr="40310054" rw_flags="RW" width="4" name="BT_AES_MISC_CFG" comment="Miscellaneous BT AES config"/>
|
||||
<register addr="40310058" rw_flags="R" width="2" name="BT_AHB_STATUS" comment="AHB Status for BTLC"/>
|
||||
<register addr="4031005c" rw_flags="RW" width="4" name="BT_CONFIG_TX" comment="BT Config TX on Bitstream processing control"/>
|
||||
<register addr="40310060" rw_flags="RW" width="4" name="BT_TX_AUTO_START_TIME" comment="Automatically turn on the Tx Bitstream digital at this time when TX_AUTO_START_EN is set."/>
|
||||
<register addr="40310064" rw_flags="RW" width="4" name="BT_CONFIG_RX" comment="BT Config RX on Bitstream processing control"/>
|
||||
<register addr="40310068" rw_flags="RW" width="4" name="BT_RX_AUTO_START_TIME" comment="Automatically turn on the Rx Bitstream digital at this time when RX_AUTO_START_EN is set."/>
|
||||
<register addr="4031006c" rw_flags="RW" width="2" name="BT_CONFIG_COEX" comment="BT Config Coex Masking "/>
|
||||
<register addr="40310070" rw_flags="RW" width="1" name="BT_SPEEDY_RST" comment="BT reset on Bitstream processing control"/>
|
||||
<register addr="40310074" rw_flags="RW" width="4" name="BT_SPEEDY_S_MON_CTRL" comment="BT Speedy Slave Monitor Ctrl"/>
|
||||
<register addr="40310078" rw_flags="RW" width="4" name="BT_SPEEDY_M_MON_CTRL" comment="BT Speedy Master Monitor Ctrl"/>
|
||||
<register addr="4031007c" rw_flags="R" width="4" name="BT_SPEEDY_MON_STATUS" comment="BT Speedy Monitor Status"/>
|
||||
<register addr="40310080" rw_flags="RW" width="1" name="BT_TX_LINK_TYPE" comment=""/>
|
||||
<register addr="40310084" rw_flags="RW" width="2" name="BT_TX_PACKET_HEADER" comment="Bluetooth packet header data."/>
|
||||
<register addr="40310088" rw_flags="RW" width="2" name="BT_TX_PAYLOAD_HEADER" comment="Bluetooth payload header data."/>
|
||||
<register addr="4031008c" rw_flags="RW" width="4" name="BT_TX_VOICE_BUFFER" comment="Buffer Handle for voice data"/>
|
||||
<register addr="40310090" rw_flags="RW" width="4" name="BT_TX_DATA_BUFFER" comment="Buffer Handle for data"/>
|
||||
<register addr="40310094" rw_flags="RW" width="4" name="BT_TX_PACKET_CONFIG1" comment=""/>
|
||||
<register addr="40310098" rw_flags="RW" width="2" name="BT_TX_PACKET_CONFIG2" comment=""/>
|
||||
<register addr="4031009c" rw_flags="RW" width="2" name="BT_TX_ESCO_NUM_VOICE_BYTES" comment=""/>
|
||||
<register addr="403100a0" rw_flags="RW" width="2" name="BT_TX_CRC_L2CAP_SEED" comment=""/>
|
||||
<register addr="403100a4" rw_flags="R" width="2" name="BT_TX_CRC_L2CAP_STATE" comment=""/>
|
||||
<register addr="403100a8" rw_flags="R" width="1" name="BT_TX_STATE" comment=""/>
|
||||
<register addr="403100ac" rw_flags="R" width="1" name="BT_TX_EVENT_TYPE" comment="Status of last transmitted packet"/>
|
||||
<register addr="403100b0" rw_flags="R" width="1" name="BT_TX_EVENT_TYPE_BIT" comment="Latch of Status/Errors of last transmitted packet - each bit corresponds to event type value"/>
|
||||
<register addr="403100b4" rw_flags="RW" width="4" name="BT_TX_WBREE_ACCESS_ADDR" comment="Wibree transmit sync word"/>
|
||||
<register addr="403100b8" rw_flags="RW" width="2" name="BT_TX_WBREE_HDR_DATA" comment="Wibree tranamit header"/>
|
||||
<register addr="403100bc" rw_flags="RW" width="4" name="BT_TX_WBREE_AD_ADDR_LSW" comment="Wibree Advertiser address - transmitted by master in an advertising packet LSW"/>
|
||||
<register addr="403100c0" rw_flags="RW" width="2" name="BT_TX_WBREE_AD_ADDR_MSW" comment="Wibree Advertiser address - transmitted by master in an advertising packet MSW"/>
|
||||
<register addr="403100c4" rw_flags="RW" width="4" name="BT_TX_WBREE_CRC_SEED" comment="Seed value for Wibree CRC and ICV checksum"/>
|
||||
<register addr="403100c8" rw_flags="RW" width="4" name="BT_TX_WBREE_BUFFER" comment="Buffer handle for Wibree data"/>
|
||||
<register addr="403100cc" rw_flags="R" width="4" name="BT_TX_WBREE_CRC" comment="Transmitted Wibree CRC/ICV"/>
|
||||
<register addr="403100d0" rw_flags="RW" width="1" name="BT_TX_WBREE_DBG_CRC_CORRUPT" comment="Corrupt transmitted Wibree CRC/ICV"/>
|
||||
<register addr="403100d4" rw_flags="RW" width="1" name="BT_TX_ANTPLUS_LENGTH" comment="Length of ANT+ frame to transmit in bytes (including access code, etc.). For example, a standard fixed frame length should be 18."/>
|
||||
<register addr="403100d8" rw_flags="RW" width="4" name="BT_TX_PLDFIFO_CONFIG" comment="Tx Voice Fifo Configuration"/>
|
||||
<register addr="403100dc" rw_flags="R" width="1" name="BT_TX_PLDFIFO_STATUS" comment="Tx Voice Fifo Status"/>
|
||||
<register addr="403100e0" rw_flags="RW" width="2" name="BT_TX_LLR_CONFIG" comment="Transmit LLR config : "/>
|
||||
<register addr="403100e4" rw_flags="RW" width="2" name="BT_TX_LLR_REPETTIONS" comment="Number of times to repeat the LLR Trigger code"/>
|
||||
<register addr="403100e8" rw_flags="RW" width="1" name="BT_TX_WAIT_FOR_RFIC_DONE" comment="Wait for the TxDone acknowledgement to come back from the RFIC before firing the end of packet interrupt"/>
|
||||
<register addr="403100ec" rw_flags="RW" width="1" name="BT_RX_MEMBER_ADDRESS" comment="Receive member address"/>
|
||||
<register addr="403100f0" rw_flags="RW" width="2" name="BT_RX_LINK_TYPE" comment="Bluetooth link type"/>
|
||||
<register addr="403100f4" rw_flags="RW" width="4" name="BT_RX_FHS_BUFFER" comment="MMU FHS buffer handle"/>
|
||||
<register addr="403100f8" rw_flags="RW" width="4" name="BT_RX_LMP_BUFFER" comment="MMU LMP buffer handle"/>
|
||||
<register addr="403100fc" rw_flags="RW" width="4" name="BT_RX_VOICE_BUFFER" comment="MMU Voice buffer handle"/>
|
||||
<register addr="40310100" rw_flags="RW" width="4" name="BT_RX_DATA_BUFFER" comment="MMU Data buffer handle"/>
|
||||
<register addr="40310104" rw_flags="RW" width="2" name="BT_RX_FHS_BUF_SIZE" comment="MMU FHS buffer size "/>
|
||||
<register addr="40310108" rw_flags="RW" width="2" name="BT_RX_LMP_BUF_SIZE" comment="MMU LMP buffer size "/>
|
||||
<register addr="4031010c" rw_flags="RW" width="2" name="BT_RX_VOICE_BUF_SIZE" comment="MMU Voice buffer size"/>
|
||||
<register addr="40310110" rw_flags="RW" width="2" name="BT_RX_DATA_BUF_SIZE" comment="MMU Data buffer size"/>
|
||||
<register addr="40310114" rw_flags="RW" width="4" name="BT_RX_CONFIG" comment=""/>
|
||||
<register addr="40310118" rw_flags="RW" width="4" name="BT_RX_PACKET_CONFIG1" comment="Receive packet configuration - part1"/>
|
||||
<register addr="4031011c" rw_flags="RW" width="4" name="BT_RX_PACKET_CONFIG2" comment="Receive packet configuration - part2"/>
|
||||
<register addr="40310120" rw_flags="RW" width="2" name="BT_RX_ESCO_NUM_VOICE_BYTES" comment=""/>
|
||||
<register addr="40310124" rw_flags="RW" width="2" name="BT_RX_CRC_L2CAP_SEED" comment="L2CAP CRC seed"/>
|
||||
<register addr="40310128" rw_flags="RW" width="4" name="BT_RX_MLE_LEN" comment="Length increments for MLE escon length info"/>
|
||||
<register addr="4031012c" rw_flags="RW" width="1" name="BT_RX_MR_DEBUG_CONFIG" comment="Enable EDR debug - non zero"/>
|
||||
<register addr="40310130" rw_flags="R" width="1" name="BT_RX_STATE" comment="Debug register - current state of rx_control"/>
|
||||
<register addr="40310134" rw_flags="R" width="2" name="BT_RX_CRC_L2CAP_STATE" comment="Debug register - received L2CAP syndrome register"/>
|
||||
<register addr="40310138" rw_flags="R" width="1" name="BT_RX_FEC_NUM_CORR_HEADER_ERRORS" comment="FEC correctable header error count"/>
|
||||
<register addr="4031013c" rw_flags="R" width="2" name="BT_RX_PACKET_HEADER" comment="Received packet header"/>
|
||||
<register addr="40310140" rw_flags="R" width="2" name="BT_RX_PAYLOAD_HEADER" comment="Received payload header"/>
|
||||
<register addr="40310144" rw_flags="R" width="2" name="BT_RX_PAYLOAD_NUM_VOICE_BYTES" comment="Number of voice bytes received"/>
|
||||
<register addr="40310148" rw_flags="R" width="2" name="BT_RX_PAYLOAD_NUM_DATA_BYTES" comment="Number of data bytes received"/>
|
||||
<register addr="4031014c" rw_flags="R" width="1" name="BT_RX_FEC_NUM_CORR_ERRORS" comment="FEC correctable error count"/>
|
||||
<register addr="40310150" rw_flags="R" width="1" name="BT_RX_FEC_NUM_UNCORR_ERRORS" comment="FEC un-correctable error count"/>
|
||||
<register addr="40310154" rw_flags="RW" width="1" name="BT_RX_EVENT_CLEAR" comment="Write to clear receive event and interrupt without disabling the RX (need to toggle the bit)"/>
|
||||
<register addr="40310158" rw_flags="R" width="1" name="BT_RX_EVENT_TYPE" comment="Received event type"/>
|
||||
<register addr="4031015c" rw_flags="R" width="4" name="BT_RX_EVENT_TYPE_BIT" comment="Received event type - Latch of bits for each error/event type"/>
|
||||
<register addr="40310160" rw_flags="RW" width="4" name="BT_RX_WBREE_ACCESS_ADDR_BB" comment="Wibree Access Address. Sync word to seacrhg for in received packets"/>
|
||||
<register addr="40310164" rw_flags="R" width="2" name="BT_RX_WBREE_HDR_DATA" comment="Wibree received header"/>
|
||||
<register addr="40310168" rw_flags="R" width="4" name="BT_RX_WBREE_AD_ADDR_LSW" comment="Received Advertiser address - applicable to adverting packets only LSW"/>
|
||||
<register addr="4031016c" rw_flags="R" width="2" name="BT_RX_WBREE_AD_ADDR_MSW" comment="Received Advertiser address - applicable to adverting packets only MSW"/>
|
||||
<register addr="40310170" rw_flags="RW" width="4" name="BT_RX_WBREE_CRC_SEED" comment="Wibree CRC seed"/>
|
||||
<register addr="40310174" rw_flags="RW" width="4" name="BT_RX_WBREE_BUFFER" comment="Wibree receive buffer handle"/>
|
||||
<register addr="40310178" rw_flags="RW" width="2" name="BT_RX_WBREE_BUF_SIZE" comment="Wibree receive buffer size"/>
|
||||
<register addr="4031017c" rw_flags="R" width="4" name="BT_RX_WBREE_CRC" comment=""/>
|
||||
<register addr="40310180" rw_flags="RW" width="4" name="BT_RX_PLDFIFO_CONFIG" comment="Tx Voice Fifo Configuration"/>
|
||||
<register addr="40310184" rw_flags="R" width="1" name="BT_RX_PLDFIFO_STATUS" comment="Tx Voice Fifo Status"/>
|
||||
<register addr="40310188" rw_flags="RW" width="4" name="BT41_ZL_NONCE_CFG" comment="Set zero flag on Rcv Nonce for zero length packets received with following types:"/>
|
||||
<register addr="4031018c" rw_flags="R" width="4" name="AES_CCM_DATA" comment="Received encrypted MIC"/>
|
||||
<register addr="40310190" rw_flags="R" width="4" name="AES_EXP_CCM_DATA" comment="Expected encrypted MIC"/>
|
||||
<register addr="40310194" rw_flags="RW" width="1" name="BT41_SNIFF_MODE" comment="Prevent decryption of incoming data stream"/>
|
||||
<register addr="40310198" rw_flags="RW" width="1" name="BT_RX_ANTPLUS_LENGTH" comment="ANT plus packet length (for receive state machine)"/>
|
||||
<register addr="4031019c" rw_flags="RW" width="1" name="BT_RX_WAIT_FOR_RFIC_DONE" comment="Wait for the RxDone acknowledgement to come back from the RFIC before firing the end of packet interrupt"/>
|
||||
<register addr="403101a0" rw_flags="RW" width="2" name="BT_RX_MLE_ACL_PAYLOAD_ESTIMATE" comment="An estimate of the ACL payload length. This is used to ensure the MLE demodulator doesn't stop tracing back before we get the correct payload length across to the RFIC."/>
|
||||
<register addr="403101a4" rw_flags="RW" width="1" name="BT_RX_MLE_ACL_PAYLOAD_DELAY" comment="Number of clock cycles to delay sending the ACL payload to the RFIC. This is used to correct a potential timing issue (see SB-17048)"/>
|
||||
<register addr="403101a8" rw_flags="RW" width="4" name="BT_TXRX_MASTER_CLOCK" comment="Master clock seed for BT encryption LSFR"/>
|
||||
<register addr="403101ac" rw_flags="RW" width="4" name="BT_TXRX_MASTER_ADDRESS_LSW" comment="Master address seed for BT encryption LSFR"/>
|
||||
<register addr="403101b0" rw_flags="RW" width="2" name="BT_TXRX_MASTER_ADDRESS_MSW" comment="Master address seed for BT encryption LSFR"/>
|
||||
<register addr="403101b4" rw_flags="RW" width="1" name="BT_TXRX_HOP_MODE" comment="0: 79 hops, 1: 23 hops"/>
|
||||
<register addr="403101b8" rw_flags="RW" width="1" name="BT_TXRX_HOP_SEQ_TYPE" comment="Configure HOP sequence type"/>
|
||||
<register addr="403101bc" rw_flags="RW" width="4" name="BT_TXRX_HOP_UAP_LAP" comment="Upper and Lower BT address to determine frequecy hopping sequence"/>
|
||||
<register addr="403101c0" rw_flags="RW" width="4" name="BT_TXRX_HOP_CLOCK" comment="Master clock"/>
|
||||
<register addr="403101c4" rw_flags="RW" width="1" name="BT_TXRX_HOP_Y1" comment="Y1 from BT specification,"/>
|
||||
<register addr="403101c8" rw_flags="RW" width="1" name="BT_TXRX_HOP_K_SEL" comment="K from BT specification, 0: Koffset=24, 1: Koffset=8"/>
|
||||
<register addr="403101cc" rw_flags="RW" width="1" name="BT_TXRX_HOP_N" comment="Number of channels in adapted hop sequence"/>
|
||||
<register addr="403101d0" rw_flags="RW" width="1" name="BT_TXRX_HOP_F" comment="Adapted Hop sequence mapping (F from BT specification)"/>
|
||||
<register addr="403101d4" rw_flags="RW" width="4" name="BT_TXRX_ACCESS_CODE_LAP" comment="Lower 24 bits of BT address to generate access code - bit 24 causes an invertion of the generated access code."/>
|
||||
<register addr="403101d8" rw_flags="RW" width="1" name="BT_TXRX_WHITEN_ACTIVE" comment="Enable data whitening"/>
|
||||
<register addr="403101dc" rw_flags="RW" width="1" name="BT_TXRX_WHITEN_SEED" comment="Whitener seed for BT and Wibree packets"/>
|
||||
<register addr="403101e0" rw_flags="RW" width="1" name="BT_TXRX_ENCRYPT_ACTIVE" comment="Enable BT encryption"/>
|
||||
<register addr="403101e4" rw_flags="RW" width="4" name="BT_TXRX_ENCRYPT_KEY_0" comment="BT encryption key"/>
|
||||
<register addr="403101e8" rw_flags="RW" width="4" name="BT_TXRX_ENCRYPT_KEY_1" comment="BT encryption key"/>
|
||||
<register addr="403101ec" rw_flags="RW" width="4" name="BT_TXRX_ENCRYPT_KEY_2" comment="BT encryption key"/>
|
||||
<register addr="403101f0" rw_flags="RW" width="4" name="BT_TXRX_ENCRYPT_KEY_3" comment="BT encryption key"/>
|
||||
<register addr="403101f4" rw_flags="RW" width="1" name="BT_TXRX_HEC_CRC_SEED" comment="Transmit and receive Header Error CRC seed"/>
|
||||
<register addr="403101f8" rw_flags="R" width="2" name="BT_TXRX_HOP_INDEX_PRE_MOD" comment="Index of required hop before final modulus"/>
|
||||
<register addr="403101fc" rw_flags="R" width="1" name="BT_TXRX_HOP_INDEX" comment="Index of required hop (0 to 78 or 0 to 22)"/>
|
||||
<register addr="40310200" rw_flags="RW" width="1" name="BT_TXRX_AES_DBG_ADDR" comment="Select data to be read in AES_DBG_DATA"/>
|
||||
<register addr="40310204" rw_flags="R" width="2" name="BT_TXRX_AES_DBG_DATA" comment="P and K debug data"/>
|
||||
<register addr="40310208" rw_flags="RW" width="4" name="BT_TXRX_AES_KEY_0" comment="AES key"/>
|
||||
<register addr="4031020c" rw_flags="RW" width="4" name="BT_TXRX_AES_KEY_1" comment="AES key"/>
|
||||
<register addr="40310210" rw_flags="RW" width="4" name="BT_TXRX_AES_KEY_2" comment="AES key"/>
|
||||
<register addr="40310214" rw_flags="RW" width="4" name="BT_TXRX_AES_KEY_3" comment="AES key"/>
|
||||
<register addr="40310218" rw_flags="RW" width="4" name="BT_TXRX_AES_NONCE_0" comment="AES Nonce to be encrypted"/>
|
||||
<register addr="4031021c" rw_flags="RW" width="4" name="BT_TXRX_AES_NONCE_1" comment="AES Nonce to be encrypted"/>
|
||||
<register addr="40310220" rw_flags="RW" width="4" name="BT_TXRX_AES_NONCE_2" comment="AES Nonce to be encrypted"/>
|
||||
<register addr="40310224" rw_flags="RW" width="1" name="BT_TXRX_AES_NONCE_3" comment="AES Nonce to be encrypted"/>
|
||||
<register addr="40310228" rw_flags="RW" width="4" name="BT_TXRX_AES_NONCE2_0" comment="AES Additional Nonce to be encrypted"/>
|
||||
<register addr="4031022c" rw_flags="RW" width="4" name="BT_TXRX_AES_NONCE2_1" comment="AES Additional Nonce to be encrypted"/>
|
||||
<register addr="40310230" rw_flags="RW" width="4" name="BT_TXRX_AES_NONCE2_2" comment="AES Additional Nonce to be encrypted"/>
|
||||
<register addr="40310234" rw_flags="RW" width="1" name="BT_TXRX_AES_NONCE2_3" comment="AES Additional Nonce to be encrypted"/>
|
||||
<register addr="40310238" rw_flags="RW" width="2" name="BT_TXRX_AES_CCM_HDR_EN1" comment="Select which bits of header make up B0 key for AES-CCM"/>
|
||||
<register addr="4031023c" rw_flags="RW" width="2" name="BT_TXRX_AES_CCM_HDR_EN2" comment="Select which bits of header make up B0 key for AES-CCM"/>
|
||||
<register addr="40310240" rw_flags="RW" width="1" name="BT_TXRX_AES_CCM_FLAG_B0" comment="Aes-Ccm B0 flag"/>
|
||||
<register addr="40310244" rw_flags="RW" width="1" name="BT_TXRX_AES_CCM_FLAG_C0" comment="Aes-Ccm C0 flag"/>
|
||||
<register addr="40310248" rw_flags="RW" width="2" name="BT_TXRX_AES_CONFIG" comment="AES config CMM select / Nonce Select"/>
|
||||
<register addr="4031024c" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_KEY_0" comment="AES key for standalone engine"/>
|
||||
<register addr="40310250" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_KEY_1" comment="AES key for standalone engine"/>
|
||||
<register addr="40310254" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_KEY_2" comment="AES key for standalone engine"/>
|
||||
<register addr="40310258" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_KEY_3" comment="AES key for standalone engine"/>
|
||||
<register addr="4031025c" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_PLAINTEXT_0" comment="Plaintext for standalone AES engine"/>
|
||||
<register addr="40310260" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_PLAINTEXT_1" comment="Plaintext for standalone AES engine"/>
|
||||
<register addr="40310264" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_PLAINTEXT_2" comment="Plaintext for standalone AES engine"/>
|
||||
<register addr="40310268" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_PLAINTEXT_3" comment="Plaintext for standalone AES engine"/>
|
||||
<register addr="4031026c" rw_flags="R" width="4" name="BT_TXRX_STANDALONE_AES_CRYPTTEXT_0" comment="Enciphered text for standalone AES engine"/>
|
||||
<register addr="40310270" rw_flags="R" width="4" name="BT_TXRX_STANDALONE_AES_CRYPTTEXT_1" comment="Enciphered text for standalone AES engine"/>
|
||||
<register addr="40310274" rw_flags="R" width="4" name="BT_TXRX_STANDALONE_AES_CRYPTTEXT_2" comment="Enciphered text for standalone AES engine"/>
|
||||
<register addr="40310278" rw_flags="R" width="4" name="BT_TXRX_STANDALONE_AES_CRYPTTEXT_3" comment="Enciphered text for standalone AES engine"/>
|
||||
<register addr="4031027c" rw_flags="RW" width="2" name="BT_TXRX_STANDALONE_AES_CONTROL" comment="Write to start standalone AES engine"/>
|
||||
<register addr="40310280" rw_flags="R" width="1" name="BT_TXRX_STANDALONE_AES_BUSY" comment="Indicates that the AES engine is currently busy. Goes high immediately when BT_TXRX_STANDALONE_AES_START is written. BT_TXRX_STANDALONE_AES_CRYPTTEXT is not valid until it goes low."/>
|
||||
<register addr="40310284" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_0" comment="Update the CVSD codec state 279:0"/>
|
||||
<register addr="40310288" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_1" comment=""/>
|
||||
<register addr="4031028c" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_2" comment=""/>
|
||||
<register addr="40310290" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_3" comment=""/>
|
||||
<register addr="40310294" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_4" comment=""/>
|
||||
<register addr="40310298" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_5" comment=""/>
|
||||
<register addr="4031029c" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_6" comment=""/>
|
||||
<register addr="403102a0" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_7" comment=""/>
|
||||
<register addr="403102a4" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_8" comment=""/>
|
||||
<register addr="403102a8" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_0" comment="Current voice codec state bits 279:0 "/>
|
||||
<register addr="403102ac" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_1" comment=""/>
|
||||
<register addr="403102b0" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_2" comment=""/>
|
||||
<register addr="403102b4" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_3" comment=""/>
|
||||
<register addr="403102b8" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_4" comment=""/>
|
||||
<register addr="403102bc" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_5" comment=""/>
|
||||
<register addr="403102c0" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_6" comment=""/>
|
||||
<register addr="403102c4" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_7" comment=""/>
|
||||
<register addr="403102c8" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_8" comment=""/>
|
||||
<register addr="403102cc" rw_flags="RW" width="2" name="BT_VOICE_SETTING" comment="SCO voice setting"/>
|
||||
</block>
|
||||
<block name="bt_dmah" comment="">
|
||||
<register addr="40100000" rw_flags="R" width="1" name="BTDMAH_CH0_STATUS" comment="Channel 0 - Status word"/>
|
||||
<register addr="40100004" rw_flags="RW" width="4" name="BTDMAH_CH0_SRC_ADDR" comment="Channel 0 - Base address of the source block"/>
|
||||
<register addr="40100008" rw_flags="RW" width="4" name="BTDMAH_CH0_DST_ADDR" comment="Channel 0 - Base address of the destination block"/>
|
||||
<register addr="4010000c" rw_flags="RW" width="4" name="BTDMAH_CH0_CONTROL" comment="Channel 0 - Control word"/>
|
||||
<register addr="40100010" rw_flags="R" width="1" name="BTDMAH_CH1_STATUS" comment="Channel 1 - Status word"/>
|
||||
<register addr="40100014" rw_flags="RW" width="4" name="BTDMAH_CH1_SRC_ADDR" comment="Channel 1 - Base address of the source block"/>
|
||||
<register addr="40100018" rw_flags="RW" width="4" name="BTDMAH_CH1_DST_ADDR" comment="Channel 1 - Base address of the destination block"/>
|
||||
<register addr="4010001c" rw_flags="RW" width="4" name="BTDMAH_CH1_CONTROL" comment="Channel 1 - Control word"/>
|
||||
<register addr="40100020" rw_flags="R" width="1" name="BTDMAH_CH2_STATUS" comment="Channel 2 - Status word"/>
|
||||
<register addr="40100024" rw_flags="RW" width="4" name="BTDMAH_CH2_SRC_ADDR" comment="Channel 2 - Base address of the source block"/>
|
||||
<register addr="40100028" rw_flags="R" width="2" name="BTDMAH_CH2_PTR" comment="Channel 2 - Current Buffer Pointer"/>
|
||||
<register addr="4010002c" rw_flags="RW" width="4" name="BTDMAH_CH2_CONTROL" comment="Channel 2 - Control word"/>
|
||||
<register addr="40100030" rw_flags="R" width="1" name="BTDMAH_CH3_STATUS" comment="Channel 3 - Status word"/>
|
||||
<register addr="40100034" rw_flags="RW" width="4" name="BTDMAH_CH3_DST_ADDR" comment="Channel 3 - Base address of the destination block"/>
|
||||
<register addr="40100038" rw_flags="R" width="2" name="BTDMAH_CH3_PTR" comment="Channel 3 - Current Buffer Pointer"/>
|
||||
<register addr="4010003c" rw_flags="RW" width="4" name="BTDMAH_CH3_CONTROL" comment="Channel 3 - Control word"/>
|
||||
</block>
|
||||
<block name="bt_pp_config" comment="">
|
||||
<register addr="40200000" rw_flags="R" width="4" name="BTPP_VERSION" comment="Processor platform version signature - actually a 32-bit value in ctime format"/>
|
||||
<register addr="40200004" rw_flags="RW" width="4" name="BTPP_POR_CONFIG" comment="Processor platform Configuration - NOTE Currently not in use."/>
|
||||
<register addr="40200008" rw_flags="RW" width="4" name="BTPP_RST_CONFIG" comment="Processor platform Configuration - NOTE Currently not in use."/>
|
||||
<register addr="4020000c" rw_flags="R" width="2" name="BT_PROC_STATUS" comment="Pio Status"/>
|
||||
<register addr="40200010" rw_flags="RW" width="2" name="BT_PROC_DRIVE" comment="Pio Drive"/>
|
||||
<register addr="40200014" rw_flags="RW" width="2" name="BT_PROC_DRIVE_EN" comment="Pio Drive En"/>
|
||||
<register addr="40200018" rw_flags="RW" width="1" name="BT_PROC_BLOCK_ACCESS_TO_R4" comment="Block the CPU access to R4 resources"/>
|
||||
<register addr="4020001c" rw_flags="RW" width="1" name="BTPP_IRQ2R4_SET" comment="Write 1 in the corresponding bit to raise an IRQ line to WLAN. Writing 0 has no any effect"/>
|
||||
<register addr="40200020" rw_flags="RW" width="1" name="BTPP_IRQ2R4_CLR" comment="Write 1 in the corresponding bit to clear an IRQ line to WLAN. Writing 0 has no any effect"/>
|
||||
<register addr="40200024" rw_flags="R" width="1" name="BTPP_IRQ2R4" comment="Status of the IRQ lines to WLAN"/>
|
||||
</block>
|
||||
<block name="speedy" comment="">
|
||||
<register addr="40320000" rw_flags="RW" width="4" name="SPEEDY_ADDR_CTRL" comment="Address and control flags for a Speedy transaction. Write this register to create an APB cycle on the remote chip (set up the write data first for write cycles). NOTE: usage of bit 19 (spare)"/>
|
||||
<register addr="40320004" rw_flags="RW" width="4" name="SPEEDY_WRITE_DATA" comment="Data to write to APB over Speedy"/>
|
||||
<register addr="40320008" rw_flags="R" width="4" name="SPEEDY_READ_DATA" comment="Data read back for APB over Speedy"/>
|
||||
<register addr="4032000c" rw_flags="R" width="1" name="SPEEDY_APB_STATUS" comment="Status of the current APB cycle"/>
|
||||
</block>
|
||||
</subsystem>
|
||||
313
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/hardware/moredump/cortexM4.xml
vendored
Normal file
313
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/hardware/moredump/cortexM4.xml
vendored
Normal file
|
|
@ -0,0 +1,313 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!--
|
||||
(c) SCSC 2015.
|
||||
|
||||
XML file defining Cortex M4 moredump
|
||||
-->
|
||||
|
||||
<processor xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||
xsi:schemaLocation="http://www.samsung.com Registers.xsd"
|
||||
name="Cortex M4" comment="Cortex M4 On-Chip Peripherals">
|
||||
<memory name="System Control" class="S">
|
||||
<register addr="e000e008" rw_flags="RW" width="4" name="ACTLR" comment="Auxiliary Control Register"/>
|
||||
<register addr="e000e010" rw_flags="RW" width="4" name="STCSR" comment="SysTick Control and Status Register"/>
|
||||
<register addr="e000e014" rw_flags="RW" width="4" name="STRVR" comment="SysTick Reload Value Register"/>
|
||||
<register addr="e000e018" rw_flags="RW" width="4" name="STCVR" comment="SysTick Current Value Register"/>
|
||||
<register addr="e000e01c" rw_flags="RW" width="4" name="STCR" comment="SysTick Calibration Value Register"/>
|
||||
<register addr="e000ed00" rw_flags="RW" width="4" name="CPUID" comment="CPU ID Base Register"/>
|
||||
<register addr="e000ed04" rw_flags="RW" width="4" name="ICSR" comment="Interrupt Control State Register"/>
|
||||
<register addr="e000ed08" rw_flags="RW" width="4" name="VTOR" comment="Vector Table Offset Register"/>
|
||||
<register addr="e000ed0c" rw_flags="RW" width="4" name="AIRCR" comment="Application Interrupt and Reset Control Register"/>
|
||||
<register addr="e000ed10" rw_flags="RW" width="4" name="SCR" comment="System Control Register"/>
|
||||
<register addr="e000ed14" rw_flags="RW" width="4" name="CCR" comment="Configuration Control Register"/>
|
||||
<register addr="e000ed18" rw_flags="RW" width="4" name="SHPR1" comment="System Handler Priority Register 1"/>
|
||||
<register addr="e000ed1c" rw_flags="RW" width="4" name="SHPR2" comment="System Handler Priority Register 2"/>
|
||||
<register addr="e000ed20" rw_flags="RW" width="4" name="SHPR3" comment="System Handler Priority Register 3"/>
|
||||
<register addr="e000ed24" rw_flags="RW" width="4" name="SHCSR" comment="System Handler Control and State Register"/>
|
||||
<register addr="e000ed28" rw_flags="RW" width="4" name="CFSR" comment="Configurable Fault Status Register"/>
|
||||
<register addr="e000ed2c" rw_flags="RW" width="4" name="HFSR" comment="Hard Fault Status Register"/>
|
||||
<register addr="e000ed30" rw_flags="RW" width="4" name="DFSR" comment="Debug Fault Status Register"/>
|
||||
<register addr="e000ed34" rw_flags="RW" width="4" name="MMFAR" comment="MemManage Fault Address Register"/>
|
||||
<register addr="e000ed38" rw_flags="RW" width="4" name="BFAR" comment="BusFault Address Register"/>
|
||||
<register addr="e000ed3c" rw_flags="RW" width="4" name="AFSR" comment="Auxiliary Fault Status Register"/>
|
||||
<register addr="e000ed88" rw_flags="RW" width="4" name="CPACR" comment="Coprocessor Access Control Register"/>
|
||||
<block name="Feature Registers">
|
||||
<register addr="e000ed40" rw_flags="RW" width="4" name="ID_PFR0" comment="Processor Feature Register 0"/>
|
||||
<register addr="e000ed44" rw_flags="RW" width="4" name="ID_PFR1" comment="Processor Feature Register 1"/>
|
||||
<register addr="e000ed48" rw_flags="RW" width="4" name="ID_DFR0" comment="Debug Feature Register 0"/>
|
||||
<register addr="e000ed4c" rw_flags="RW" width="4" name="ID_AFR0" comment="Auxiliary Feature Register 0"/>
|
||||
<register addr="e000ed50" rw_flags="RW" width="4" name="ID_MMFR0" comment="Memory Model Feature Register 0"/>
|
||||
<register addr="e000ed54" rw_flags="RW" width="4" name="ID_MMFR1" comment="Memory Model Feature Register 1"/>
|
||||
<register addr="e000ed58" rw_flags="RW" width="4" name="ID_MMFR2" comment="Memory Model Feature Register 2"/>
|
||||
<register addr="e000ed5c" rw_flags="RW" width="4" name="ID_MMFR3" comment="Memory Model Feature Register 3"/>
|
||||
<register addr="e000ed60" rw_flags="RW" width="4" name="ID_ISAR0" comment="Instruction Set Attribute Feature Register 0"/>
|
||||
<register addr="e000ed64" rw_flags="RW" width="4" name="ID_ISAR1" comment="Instruction Set Attribute Feature Register 1"/>
|
||||
<register addr="e000ed68" rw_flags="RW" width="4" name="ID_ISAR2" comment="Instruction Set Attribute Feature Register 2"/>
|
||||
<register addr="e000ed6c" rw_flags="RW" width="4" name="ID_ISAR3" comment="Instruction Set Attribute Feature Register 3"/>
|
||||
<register addr="e000ed70" rw_flags="RW" width="4" name="ID_ISAR4" comment="Instruction Set Attribute Feature Register 4"/>
|
||||
</block>
|
||||
<block name="Coresight identification Registers">
|
||||
<register addr="e000efd0" rw_flags="RW" width="4" name="PID4" comment="Peripheral Identification Register 4"/>
|
||||
<register addr="e000efe0" rw_flags="RW" width="4" name="PID0" comment="Peripheral ID0"/>
|
||||
<register addr="e000efe4" rw_flags="RW" width="4" name="PID1" comment="Peripheral ID1"/>
|
||||
<register addr="e000efe8" rw_flags="RW" width="4" name="PID2" comment="Peripheral ID2"/>
|
||||
<register addr="e000efec" rw_flags="RW" width="4" name="PID3" comment="Peripheral ID3"/>
|
||||
<register addr="e000eff0" rw_flags="RW" width="4" name="CID0" comment="Component ID0 (Preamble)"/>
|
||||
<register addr="e000eff4" rw_flags="RW" width="4" name="CID1" comment="Component ID1"/>
|
||||
<register addr="e000eff8" rw_flags="RW" width="4" name="CID2" comment="Component ID2"/>
|
||||
<register addr="e000effc" rw_flags="RW" width="4" name="CID3" comment="Component ID3"/>
|
||||
</block>
|
||||
</memory>
|
||||
|
||||
<memory name="Memory Protection Unit" class="S">
|
||||
<register addr="e000ed90" rw_flags="RW" width="4" name="MPUTYPE" comment="MPU Type Register"/>
|
||||
<register addr="e000ed94" rw_flags="RW" width="4" name="MPUCONTROL" comment="MPU Control Register"/>
|
||||
<table name="MPU Regions">
|
||||
<indexregister addr="e000ed98" rw_flags="RW" width="4" name="MPUREGION" comment="MPU Region Number Register">
|
||||
<countfrom addr="e000ed90" rw_flags="RW" width="4" name="MPUTYPE" comment="MPU type register" shift="8" mask="000F"/>
|
||||
</indexregister>
|
||||
<register addr="e000ed9c" rw_flags="RW" width="4" name="MBUREGBASEADD" comment="MPU Region Base Address Register"/>
|
||||
<register addr="e000eda0" rw_flags="RW" width="4" name="MPUREGATTRIB" comment="MPU Region Attribute and Size Register"/>
|
||||
</table>
|
||||
</memory>
|
||||
|
||||
<memory name="Nested Vectored Interrupt Controller" class="S">
|
||||
<register addr="e000e004" rw_flags="RW" width="4" name="ICTR" comment="Interrupt Controller Type Register"/>
|
||||
<block name="Interrupt Set/Clear Enable Registers">
|
||||
<register addr="e000e100" rw_flags="RW" width="4" name="IRQ0_31SET/CLREN" comment="Interrupt Set/Clear Enable Register"/>
|
||||
<register addr="e000e104" rw_flags="RW" width="4" name="IRQ32_63SET/CLREN" comment="Interrupt Set/Clear Enable Register"/>
|
||||
<register addr="e000e108" rw_flags="RW" width="4" name="IRQ64_95SET/CLREN" comment="Interrupt Set/Clear Enable Register"/>
|
||||
<register addr="e000e10c" rw_flags="RW" width="4" name="IRQ96_127SET/CLREN" comment="Interrupt Set/Clear Enable Register"/>
|
||||
<register addr="e000e110" rw_flags="RW" width="4" name="IRQ128_159SET/CLREN" comment="Interrupt Set/Clear Enable Register"/>
|
||||
<register addr="e000e114" rw_flags="RW" width="4" name="IRQ160_191SET/CLREN" comment="Interrupt Set/Clear Enable Register"/>
|
||||
<register addr="e000e118" rw_flags="RW" width="4" name="IRQ192_223SET/CLREN" comment="Interrupt Set/Cleared Enable Register"/>
|
||||
<register addr="e000e11c" rw_flags="RW" width="4" name="IRQ224_239SET/CLREN" comment="Interrupt Set/Clear Enable Register"/>
|
||||
</block>
|
||||
<block name="Interrupt Set/Clear Pending Registers">
|
||||
<register addr="e000e200" rw_flags="RW" width="4" name="IRQ0_31_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
<register addr="e000e204" rw_flags="RW" width="4" name="IRQ32_63_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
<register addr="e000e208" rw_flags="RW" width="4" name="IRQ64_95_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
<register addr="e000e20c" rw_flags="RW" width="4" name="IRQ96_127_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
<register addr="e000e210" rw_flags="RW" width="4" name="IRQ128_159_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
<register addr="e000e214" rw_flags="RW" width="4" name="IRQ160_191_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
<register addr="e000e218" rw_flags="RW" width="4" name="IRQ192_223_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
<register addr="e000e21c" rw_flags="RW" width="4" name="IRQ224_239_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
</block>
|
||||
<block name="Interrupt Active Bit Registers">
|
||||
<register addr="e000e300" rw_flags="RW" width="4" name="ACTIVE1" comment="Active Bit Register 1"/>
|
||||
<register addr="e000e304" rw_flags="RW" width="4" name="ACTIVE2" comment="Active Bit Register 2"/>
|
||||
<register addr="e000e308" rw_flags="RW" width="4" name="ACTIVE3" comment="Active Bit Register 3"/>
|
||||
<register addr="e000e30c" rw_flags="RW" width="4" name="ACTIVE4" comment="Active Bit Register 4"/>
|
||||
<register addr="e000e310" rw_flags="RW" width="4" name="ACTIVE5" comment="Active Bit Register 5"/>
|
||||
<register addr="e000e314" rw_flags="RW" width="4" name="ACTIVE6" comment="Active Bit Register 6"/>
|
||||
<register addr="e000e318" rw_flags="RW" width="4" name="ACTIVE7" comment="Active Bit Register 7"/>
|
||||
<register addr="e000e31c" rw_flags="RW" width="4" name="ACTIVE8" comment="Active Bit Register 8"/>
|
||||
</block>
|
||||
<block name="Interrupt Priority Registers">
|
||||
<register addr="e000e400" rw_flags="RW" width="4" name="INT0" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e404" rw_flags="RW" width="4" name="INT1" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e408" rw_flags="RW" width="4" name="INT2" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e40c" rw_flags="RW" width="4" name="INT3" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e410" rw_flags="RW" width="4" name="INT4" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e414" rw_flags="RW" width="4" name="INT5" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e418" rw_flags="RW" width="4" name="INT6" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e41c" rw_flags="RW" width="4" name="INT7" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e420" rw_flags="RW" width="4" name="INT8" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e424" rw_flags="RW" width="4" name="INT9" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e428" rw_flags="RW" width="4" name="INT10" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e42c" rw_flags="RW" width="4" name="INT11" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e430" rw_flags="RW" width="4" name="INT12" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e434" rw_flags="RW" width="4" name="INT13" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e438" rw_flags="RW" width="4" name="INT14" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e43c" rw_flags="RW" width="4" name="INT15" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e440" rw_flags="RW" width="4" name="INT16" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e444" rw_flags="RW" width="4" name="INT17" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e448" rw_flags="RW" width="4" name="INT18" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e44c" rw_flags="RW" width="4" name="INT19" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e450" rw_flags="RW" width="4" name="INT20" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e454" rw_flags="RW" width="4" name="INT21" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e458" rw_flags="RW" width="4" name="INT22" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e45c" rw_flags="RW" width="4" name="INT23" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e460" rw_flags="RW" width="4" name="INT24" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e464" rw_flags="RW" width="4" name="INT25" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e468" rw_flags="RW" width="4" name="INT26" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e46c" rw_flags="RW" width="4" name="INT27" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e470" rw_flags="RW" width="4" name="INT28" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e474" rw_flags="RW" width="4" name="INT29" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e478" rw_flags="RW" width="4" name="INT30" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e47c" rw_flags="RW" width="4" name="INT31" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e480" rw_flags="RW" width="4" name="INT32" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e484" rw_flags="RW" width="4" name="INT33" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e488" rw_flags="RW" width="4" name="INT34" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e48c" rw_flags="RW" width="4" name="INT35" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e490" rw_flags="RW" width="4" name="INT36" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e494" rw_flags="RW" width="4" name="INT37" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e498" rw_flags="RW" width="4" name="INT38" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e49c" rw_flags="RW" width="4" name="INT39" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4a0" rw_flags="RW" width="4" name="INT40" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4a4" rw_flags="RW" width="4" name="INT41" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4a8" rw_flags="RW" width="4" name="INT42" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4ac" rw_flags="RW" width="4" name="INT43" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4b0" rw_flags="RW" width="4" name="INT44" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4b4" rw_flags="RW" width="4" name="INT45" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4b8" rw_flags="RW" width="4" name="INT46" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4bc" rw_flags="RW" width="4" name="INT47" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4c0" rw_flags="RW" width="4" name="INT48" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4c4" rw_flags="RW" width="4" name="INT49" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4c8" rw_flags="RW" width="4" name="INT50" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4cc" rw_flags="RW" width="4" name="INT51" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4d0" rw_flags="RW" width="4" name="INT52" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4d4" rw_flags="RW" width="4" name="INT53" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4d8" rw_flags="RW" width="4" name="INT54" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4dc" rw_flags="RW" width="4" name="INT55" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4e0" rw_flags="RW" width="4" name="INT56" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4e4" rw_flags="RW" width="4" name="INT57" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4e8" rw_flags="RW" width="4" name="INT58" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4ec" rw_flags="RW" width="4" name="INT59" comment="Interrupt Priority Register"/>
|
||||
</block>
|
||||
</memory>
|
||||
|
||||
<memory name="Floating-point Unit (FPU)" class="S">
|
||||
<register addr="e000ef34" rw_flags="RW" width="4" name="FPCCR" comment="Floating-Point Context Control Register"/>
|
||||
<register addr="e000ef38" rw_flags="RW" width="4" name="FPCAR" comment="Floating-Point Context Address Register"/>
|
||||
<register addr="e000ef3c" rw_flags="RW" width="4" name="FPDSCR" comment="Floating-Point Default Status Control Register"/>
|
||||
<register addr="e000ef40" rw_flags="RW" width="4" name="MVFR0" comment="Media and FP Feature Register 0"/>
|
||||
<register addr="e000ef44" rw_flags="RW" width="4" name="MVFR1" comment="Media and FP Feature Register 1"/>
|
||||
</memory>
|
||||
|
||||
<memory name="Debug" class="D">
|
||||
<register addr="e000edf0" rw_flags="RW" width="4" name="DHCSR" comment="Debug Halting Control and Status Register"/>
|
||||
<register addr="e000edf8" rw_flags="RW" width="4" name="DCRDR" comment="Debug Core Register Data Register"/>
|
||||
<register addr="e000edfc" rw_flags="RW" width="4" name="DEMCR" comment="Debug Exception and Monitor Control Register"/>
|
||||
<block name="Debug components">
|
||||
<register addr="e00ff000" rw_flags="RW" width="4" name="SCS" comment="System Control Space"/>
|
||||
<register addr="e00ff004" rw_flags="RW" width="4" name="DWT" comment="Data Watchpoint and Trace Unit"/>
|
||||
<register addr="e00ff008" rw_flags="RW" width="4" name="FPB" comment="Flash Patch and Breakpoint Unit"/>
|
||||
<register addr="e00ff00c" rw_flags="RW" width="4" name="ITM" comment="Instrumentation Trace Macrocell"/>
|
||||
<register addr="e00ff010" rw_flags="RW" width="4" name="TPIU" comment="Trace Port Interface Unit"/>
|
||||
<register addr="e00ff014" rw_flags="RW" width="4" name="ETM" comment="Embedded Trace Macrocell"/>
|
||||
<register addr="e00ff018" rw_flags="RW" width="4" name="EndMarker" comment="EndMarker"/>
|
||||
<register addr="e00fffcc" rw_flags="RW" width="4" name="SYSTEM_ACCESS" comment="SYSTEM_ACCESS"/>
|
||||
</block>
|
||||
<block name="Coresight identification Registers">
|
||||
<register addr="e00fffd0" rw_flags="RW" width="4" name="PID4" comment="Peripheral Identification Register 4"/>
|
||||
<register addr="e00fffe0" rw_flags="RW" width="4" name="PID0" comment="Peripheral ID0"/>
|
||||
<register addr="e00fffe4" rw_flags="RW" width="4" name="PID1" comment="Peripheral ID1"/>
|
||||
<register addr="e00fffe8" rw_flags="RW" width="4" name="PID2" comment="Peripheral ID2"/>
|
||||
<register addr="e00fffec" rw_flags="RW" width="4" name="PID3" comment="Peripheral ID3"/>
|
||||
<register addr="e00ffff0" rw_flags="RW" width="4" name="CID0" comment="Component ID0 (Preamble)"/>
|
||||
<register addr="e00ffff4" rw_flags="RW" width="4" name="CID1" comment="Component ID1"/>
|
||||
<register addr="e00ffff8" rw_flags="RW" width="4" name="CID2" comment="Component ID2"/>
|
||||
<register addr="e00ffffc" rw_flags="RW" width="4" name="CID3" comment="Component ID3"/>
|
||||
</block>
|
||||
<block name="Flash Patch and Breakpoint Unit (FPB)">
|
||||
<register addr="e0002000" rw_flags="RW" width="4" name="FP_CTRL" comment="Flash Patch Control Register"/>
|
||||
<register addr="e0002004" rw_flags="RW" width="4" name="FP_REMAP" comment="Flash Patch Remap Register"/>
|
||||
<register addr="e0002008" rw_flags="RW" width="4" name="FP_COMP0" comment="Flash Patch Comparator Register 0"/>
|
||||
<register addr="e000200c" rw_flags="RW" width="4" name="FP_COMP1" comment="Flash Patch Comparator Register 1"/>
|
||||
<register addr="e0002010" rw_flags="RW" width="4" name="FP_COMP2" comment="Flash Patch Comparator Register 2"/>
|
||||
<register addr="e0002014" rw_flags="RW" width="4" name="FP_COMP3" comment="Flash Patch Comparator Register 3"/>
|
||||
<register addr="e0002018" rw_flags="RW" width="4" name="FP_COMP4" comment="Flash Patch Comparator Register 4"/>
|
||||
<register addr="e000201c" rw_flags="RW" width="4" name="FP_COMP5" comment="Flash Patch Comparator Register 5"/>
|
||||
<register addr="e0002020" rw_flags="RW" width="4" name="FP_COMP6" comment="Flash Patch Comparator Register 6"/>
|
||||
<register addr="e0002024" rw_flags="RW" width="4" name="FP_COMP7" comment="Flash Patch Comparator Register 7"/>
|
||||
</block>
|
||||
<block name="Coresight Management Registers">
|
||||
<register addr="e0002fd0" rw_flags="RW" width="4" name="PID4" comment="Peripheral Identification Register 4"/>
|
||||
<register addr="e0002fe0" rw_flags="RW" width="4" name="PID0" comment="Peripheral ID0"/>
|
||||
<register addr="e0002fe4" rw_flags="RW" width="4" name="PID1" comment="Peripheral ID1"/>
|
||||
<register addr="e0002fe8" rw_flags="RW" width="4" name="PID2" comment="Peripheral ID2"/>
|
||||
<register addr="e0002fec" rw_flags="RW" width="4" name="PID3" comment="Peripheral ID3"/>
|
||||
<register addr="e0002f10" rw_flags="RW" width="4" name="CID0" comment="Component ID0 (Preamble)"/>
|
||||
<register addr="e0002f14" rw_flags="RW" width="4" name="CID1" comment="Component ID1"/>
|
||||
<register addr="e0002f18" rw_flags="RW" width="4" name="CID2" comment="Component ID2"/>
|
||||
<register addr="e0002f1c" rw_flags="RW" width="4" name="CID3" comment="Component ID3"/>
|
||||
</block>
|
||||
</memory>
|
||||
|
||||
<memory name="Data Watchpoint and Trace Unit" class="S">
|
||||
<register addr="e0001000" rw_flags="RW" width="4" name="DWT_CTRL" comment="DWT Control Register"/>
|
||||
<register addr="e0001004" rw_flags="RW" width="4" name="DWT_CYCCNT" comment="Cycle Count register"/>
|
||||
<register addr="e0001008" rw_flags="RW" width="4" name="DWT_CPICNT" comment="CPI Count register"/>
|
||||
<register addr="e000100c" rw_flags="RW" width="4" name="DWT_EXCCNT" comment="DWT Exception Overhead Count Register"/>
|
||||
<register addr="e0001010" rw_flags="RW" width="4" name="DWT_SLEEPCNT" comment="DWT Sleep Count Register"/>
|
||||
<register addr="e0001014" rw_flags="RW" width="4" name="DWT_LSUCNT" comment="DWT LSU Count Register"/>
|
||||
<register addr="e0001018" rw_flags="RW" width="4" name="DWT_FOLDCNT" comment="DWT Fold Count Register"/>
|
||||
<register addr="e000101c" rw_flags="RW" width="4" name="DWT_PCSR" comment="Program Counter Sample register"/>
|
||||
<register addr="e0001020" rw_flags="RW" width="4" name="DWT_COMP0" comment="DWT Comparator Register 0"/>
|
||||
<register addr="e0001024" rw_flags="RW" width="4" name="DWT_MASK0" comment="DWT Mask Registers 0"/>
|
||||
<register addr="e0001028" rw_flags="RW" width="4" name="DWT_FUNCTION0" comment="DWT Function Registers 0"/>
|
||||
<register addr="e0001030" rw_flags="RW" width="4" name="DWT_COMP1" comment="DWT Comparator Register 1"/>
|
||||
<register addr="e0001034" rw_flags="RW" width="4" name="DWT_MASK1" comment="DWT Mask Registers 1"/>
|
||||
<register addr="e0001038" rw_flags="RW" width="4" name="DWT_FUNCTION1" comment="DWT Function Registers 1"/>
|
||||
<register addr="e0001040" rw_flags="RW" width="4" name="DWT_COMP2" comment="DWT Comparator Register 2"/>
|
||||
<register addr="e0001044" rw_flags="RW" width="4" name="DWT_MASK2" comment="DWT Mask Registers 2"/>
|
||||
<register addr="e0001048" rw_flags="RW" width="4" name="DWT_FUNCTION2" comment="DWT Function Registers 2"/>
|
||||
<register addr="e0001050" rw_flags="RW" width="4" name="DWT_COMP3" comment="DWT Comparator Register 3"/>
|
||||
<register addr="e0001054" rw_flags="RW" width="4" name="DWT_MASK3" comment="DWT Mask Registers 3"/>
|
||||
<register addr="e0001058" rw_flags="RW" width="4" name="DWT_FUNCTION3" comment="DWT Function Registers 3"/>
|
||||
<block name="Coresight Management Registers">
|
||||
<register addr="e0001fd0" rw_flags="RW" width="4" name="PID4" comment="Peripheral Identification Register 4"/>
|
||||
<register addr="e0001fe0" rw_flags="RW" width="4" name="PID0" comment="Peripheral ID0"/>
|
||||
<register addr="e0001fe4" rw_flags="RW" width="4" name="PID1" comment="Peripheral ID1"/>
|
||||
<register addr="e0001fe8" rw_flags="RW" width="4" name="PID2" comment="Peripheral ID2"/>
|
||||
<register addr="e0001fec" rw_flags="RW" width="4" name="PID3" comment="Peripheral ID3"/>
|
||||
<register addr="e0001ff0" rw_flags="RW" width="4" name="CID0" comment="Component ID0 (Preamble)"/>
|
||||
<register addr="e0001ff4" rw_flags="RW" width="4" name="CID1" comment="Component ID1"/>
|
||||
<register addr="e0001ff8" rw_flags="RW" width="4" name="CID2" comment="Component ID2"/>
|
||||
<register addr="e0001ffc" rw_flags="RW" width="4" name="CID3" comment="Component ID3"/>
|
||||
</block>
|
||||
</memory>
|
||||
|
||||
<memory name="Instrumentation Trace Macrocell (ITM)" class="S">
|
||||
<block name="Stimulus Port registers 0-31">
|
||||
<register addr="e0000000" rw_flags="RW" width="4" name="SPR0" comment="Stimulus Port Register 0"/>
|
||||
<register addr="e0000004" rw_flags="RW" width="4" name="SPR1" comment="Stimulus Port Register 1"/>
|
||||
<register addr="e0000008" rw_flags="RW" width="4" name="SPR2" comment="Stimulus Port Register 2"/>
|
||||
<register addr="e000000c" rw_flags="RW" width="4" name="SPR3" comment="Stimulus Port Register 3"/>
|
||||
<register addr="e0000010" rw_flags="RW" width="4" name="SPR4" comment="Stimulus Port Register 4"/>
|
||||
<register addr="e0000014" rw_flags="RW" width="4" name="SPR5" comment="Stimulus Port Register 5"/>
|
||||
<register addr="e0000018" rw_flags="RW" width="4" name="SPR6" comment="Stimulus Port Register 6"/>
|
||||
<register addr="e000001c" rw_flags="RW" width="4" name="SPR7" comment="Stimulus Port Register 7"/>
|
||||
<register addr="e0000020" rw_flags="RW" width="4" name="SPR8" comment="Stimulus Port Register 8"/>
|
||||
<register addr="e0000024" rw_flags="RW" width="4" name="SPR9" comment="Stimulus Port Register 9"/>
|
||||
<register addr="e0000028" rw_flags="RW" width="4" name="SPR10" comment="Stimulus Port Register 10"/>
|
||||
<register addr="e000002c" rw_flags="RW" width="4" name="SPR11" comment="Stimulus Port Register 11"/>
|
||||
<register addr="e0000030" rw_flags="RW" width="4" name="SPR12" comment="Stimulus Port Register 12"/>
|
||||
<register addr="e0000034" rw_flags="RW" width="4" name="SPR13" comment="Stimulus Port Register 13"/>
|
||||
<register addr="e0000038" rw_flags="RW" width="4" name="SPR14" comment="Stimulus Port Register 14"/>
|
||||
<register addr="e000003c" rw_flags="RW" width="4" name="SPR15" comment="Stimulus Port Register 15"/>
|
||||
<register addr="e0000040" rw_flags="RW" width="4" name="SPR16" comment="Stimulus Port Register 16"/>
|
||||
<register addr="e0000044" rw_flags="RW" width="4" name="SPR17" comment="Stimulus Port Register 17"/>
|
||||
<register addr="e0000048" rw_flags="RW" width="4" name="SPR18" comment="Stimulus Port Register 18"/>
|
||||
<register addr="e000004c" rw_flags="RW" width="4" name="SPR19" comment="Stimulus Port Register 19"/>
|
||||
<register addr="e0000050" rw_flags="RW" width="4" name="SPR20" comment="Stimulus Port Register 20"/>
|
||||
<register addr="e0000054" rw_flags="RW" width="4" name="SPR21" comment="Stimulus Port Register 21"/>
|
||||
<register addr="e0000058" rw_flags="RW" width="4" name="SPR22" comment="Stimulus Port Register 22"/>
|
||||
<register addr="e000005c" rw_flags="RW" width="4" name="SPR23" comment="Stimulus Port Register 23"/>
|
||||
<register addr="e0000060" rw_flags="RW" width="4" name="SPR24" comment="Stimulus Port Register 24"/>
|
||||
<register addr="e0000064" rw_flags="RW" width="4" name="SPR25" comment="Stimulus Port Register 25"/>
|
||||
<register addr="e0000068" rw_flags="RW" width="4" name="SPR26" comment="Stimulus Port Register 26"/>
|
||||
<register addr="e000006c" rw_flags="RW" width="4" name="SPR27" comment="Stimulus Port Register 27"/>
|
||||
<register addr="e0000070" rw_flags="RW" width="4" name="SPR28" comment="Stimulus Port Register 28"/>
|
||||
<register addr="e0000074" rw_flags="RW" width="4" name="SPR29" comment="Stimulus Port Register 29"/>
|
||||
<register addr="e0000078" rw_flags="RW" width="4" name="SPR30" comment="Stimulus Port Register 30"/>
|
||||
<register addr="e000007c" rw_flags="RW" width="4" name="SPR31" comment="Stimulus Port Register 31"/>
|
||||
</block>
|
||||
<register addr="e0000e00" rw_flags="RW" width="4" name="ITM_TER" comment="ITM Trace Enable Register"/>
|
||||
<register addr="e0000e40" rw_flags="RW" width="4" name="ITM_TPR" comment="Trace Privilege Register"/>
|
||||
<register addr="e0000e80" rw_flags="RW" width="4" name="ITM_TCR" comment="Trace Control Register"/>
|
||||
<block name="Coresight identification Registers">
|
||||
<register addr="e0000fd0" rw_flags="RW" width="4" name="PID4" comment="Peripheral Identification Register 4"/>
|
||||
<register addr="e0000fe0" rw_flags="RW" width="4" name="PID0" comment="Peripheral ID0"/>
|
||||
<register addr="e0000fe4" rw_flags="RW" width="4" name="PID1" comment="Peripheral ID1"/>
|
||||
<register addr="e0000fe8" rw_flags="RW" width="4" name="PID2" comment="Peripheral ID2"/>
|
||||
<register addr="e0000fec" rw_flags="RW" width="4" name="PID3" comment="Peripheral ID3"/>
|
||||
<register addr="e0000ff0" rw_flags="RW" width="4" name="CID0" comment="Component ID0 (Preamble)"/>
|
||||
<register addr="e0000ff4" rw_flags="RW" width="4" name="CID1" comment="Component ID1"/>
|
||||
<register addr="e0000ff8" rw_flags="RW" width="4" name="CID2" comment="Component ID2"/>
|
||||
<register addr="e0000ffc" rw_flags="RW" width="4" name="CID3" comment="Component ID3"/>
|
||||
</block>
|
||||
</memory>
|
||||
</processor>
|
||||
278
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/hardware/moredump/cortexR4.xml
vendored
Normal file
278
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/hardware/moredump/cortexR4.xml
vendored
Normal file
|
|
@ -0,0 +1,278 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!--
|
||||
(c) SCSC 2015.
|
||||
|
||||
XML file defining Cortex R4 moredump
|
||||
-->
|
||||
|
||||
<processor xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||
xsi:schemaLocation="http://www.samsung.com Registers.xsd"
|
||||
name="Cortex R4" comment="Cortex R4 On-Chip Peripherals">
|
||||
<coprocessor name="System Control" id="C15">
|
||||
<block name="ID Registers">
|
||||
<register addr="0000" rw_flags="RW" width="4" name="MIDR" comment="Main ID Register"/>
|
||||
<register addr="0100" rw_flags="RW" width="4" name="CTR" comment="Cache Type Register"/>
|
||||
<register addr="0200" rw_flags="RW" width="4" name="TCMTR" comment="Tightly-Coupled Memory Status Register"/>
|
||||
<register addr="0400" rw_flags="RW" width="4" name="MPUIR" comment="MPU type register"/>
|
||||
<register addr="0500" rw_flags="RW" width="4" name="MPIDR" comment="Multiprocessor Affinity Register"/>
|
||||
<register addr="0410" rw_flags="RW" width="4" name="MMFR0" comment="Memory Model Feature Register 0"/>
|
||||
<register addr="0510" rw_flags="RW" width="4" name="MMFR1" comment="Memory Model Feature Register 1"/>
|
||||
<register addr="0610" rw_flags="RW" width="4" name="MMFR2" comment="Memory Model Feature Register 2"/>
|
||||
<register addr="0710" rw_flags="RW" width="4" name="MMFR3" comment="Memory Model Feature Register 3"/>
|
||||
<register addr="0020" rw_flags="RW" width="4" name="ISAR0" comment="Instruction Set Attribute Register 0"/>
|
||||
<register addr="0120" rw_flags="RW" width="4" name="ISAR1" comment="Instruction Set Attribute Register 1"/>
|
||||
<register addr="0220" rw_flags="RW" width="4" name="ISAR2" comment="Instruction Set Attribute Register 2"/>
|
||||
<register addr="0320" rw_flags="RW" width="4" name="ISAR3" comment="Instruction Set Attribute Register 3"/>
|
||||
<register addr="0420" rw_flags="RW" width="4" name="ISAR4" comment="Instruction Set Attribute Register 4"/>
|
||||
<register addr="0520" rw_flags="RW" width="4" name="ISAR5" comment="Instruction Set Attribute Registers 5 (Reserved)"/>
|
||||
<register addr="0620" rw_flags="RW" width="4" name="ISAR6" comment="Instruction Set Attribute Registers 6 (Reserved)"/>
|
||||
<register addr="0720" rw_flags="RW" width="4" name="ISAR7" comment="Instruction Set Attribute Registers 7 (Reserved)"/>
|
||||
<register addr="0010" rw_flags="RW" width="4" name="PFR0" comment="Processor Feature Register 0"/>
|
||||
<register addr="0110" rw_flags="RW" width="4" name="PFR1" comment="Processor Feature Register 1"/>
|
||||
<register addr="0210" rw_flags="RW" width="4" name="DFR0" comment="Debug Feature Register 0"/>
|
||||
<register addr="0310" rw_flags="RW" width="4" name="AFR0" comment="Auxiliary Feature Register 0"/>
|
||||
</block>
|
||||
|
||||
<block name="System Control and Configuration">
|
||||
<register addr="0101" rw_flags="RW" width="4" name="ACTLR" comment="Auxiliary Control Register"/>
|
||||
<register addr="0201" rw_flags="RW" width="4" name="CPACR" comment="Coprocessor Access Control Register"/>
|
||||
<register addr="000b" rw_flags="RW" width="4" name="SPC" comment="Slave Port Control"/>
|
||||
</block>
|
||||
|
||||
<block name="MPU Control and Configuration">
|
||||
<register addr="0005" rw_flags="RW" width="4" name="DFSR" comment="Data Fault Status Register"/>
|
||||
<register addr="0006" rw_flags="RW" width="4" name="DFAR" comment="Data Fault Address Register"/>
|
||||
<register addr="0105" rw_flags="RW" width="4" name="IFSR" comment="Instruction Fault Status Register"/>
|
||||
<register addr="0206" rw_flags="RW" width="4" name="IFAR" comment="Instruction Fault Address Register"/>
|
||||
<register addr="0015" rw_flags="RW" width="4" name="ADFSR" comment="Auxiliary Data Fault Status Register"/>
|
||||
<register addr="0115" rw_flags="RW" width="4" name="AIFSR" comment="Auxiliary Instruction Fault Status Register"/>
|
||||
<register addr="010d" rw_flags="RW" width="4" name="CONTEXTIDR" comment="Context ID Register"/>
|
||||
<table name="MPU Regions">
|
||||
<indexregister addr="0026" rw_flags="RW" width="4" name="MRNR" comment="Memory Region Number Register">
|
||||
<countfrom addr="0400" rw_flags="RW" width="4" name="MPUIR" comment="MPU type register" shift="8" mask="000F"/>
|
||||
</indexregister>
|
||||
<register addr="0016" rw_flags="RW" width="4" name="RBAR" comment="Region Base Address Register"/>
|
||||
<register addr="0216" rw_flags="RW" width="4" name="RSER" comment="Region Size and Enable Register"/>
|
||||
<register addr="0416" rw_flags="RW" width="4" name="RACR" comment="Region Access Control Register"/>
|
||||
</table>
|
||||
<!-- Must restore this after MPU -->
|
||||
<register addr="0001" rw_flags="RW" width="4" name="SCTLR" comment="Control Register"/>
|
||||
</block>
|
||||
|
||||
<block name="Cache Control and Configuration">
|
||||
<register addr="1100" rw_flags="RW" width="4" name="CLIDR" comment="Cache Level ID Register"/>
|
||||
<register addr="1000" rw_flags="RW" width="4" name="CCSIDR" comment="Current Cache Size ID Register"/>
|
||||
<register addr="2000" rw_flags="RW" width="4" name="CSSELR" comment="Cache Size Selection Register"/>
|
||||
<register addr="003f" rw_flags="RW" width="4" name="CFLR" comment="Correctable Fault Location Register"/>
|
||||
</block>
|
||||
|
||||
<block name="TCM Control and Configuration">
|
||||
<register addr="0019" rw_flags="RW" width="4" name="BTCM" comment="Data TCM Region Register"/>
|
||||
<register addr="0119" rw_flags="RW" width="4" name="ATCM" comment="Instruction TCM Region Register"/>
|
||||
<register addr="0029" rw_flags="RW" width="4" name="TCMSEL" comment="TCM Selection Register"/>
|
||||
</block>
|
||||
|
||||
<block name="System Performance Monitor">
|
||||
<register addr="00C9" rw_flags="RW" width="4" name="PMNC" comment="Performance Monitor Control Register"/>
|
||||
<register addr="01C9" rw_flags="RW" width="4" name="CNTENS" comment="Count Enable Set Register"/>
|
||||
<register addr="02C9" rw_flags="RW" width="4" name="CNTENC" comment="Count Enable Clear Register"/>
|
||||
<register addr="03C9" rw_flags="RW" width="4" name="FLAG" comment="Overflow Flag Status Register"/>
|
||||
<register addr="00D9" rw_flags="RW" width="4" name="CCNT" comment="Cycle Count Register"/>
|
||||
<register addr="00E9" rw_flags="RW" width="4" name="USEREN" comment="User Enable Register"/>
|
||||
<register addr="01E9" rw_flags="RW" width="4" name="INTENS" comment="Interrupt Enable Set Register"/>
|
||||
<register addr="02E9" rw_flags="RW" width="4" name="INTENC" comment="Interrupt Enable Clear Register"/>
|
||||
<table name="Performance Counters">
|
||||
<indexregister addr="05C9" rw_flags="RW" width="4" name="PMNXSEL" comment="Performance Counter Selection Register">
|
||||
<count value="3"/>
|
||||
</indexregister>
|
||||
<register addr="01d9" rw_flags="RW" width="4" name="ESR" comment="Event Selection Register"/>
|
||||
<register addr="02d9" rw_flags="RW" width="4" name="PMCR" comment="Performance Monitor Count Register"/>
|
||||
</table>
|
||||
</block>
|
||||
</coprocessor>
|
||||
|
||||
<coprocessor name="Debug Registers" id="C14">
|
||||
<block name="Processor Identifier Registers">
|
||||
<register addr="0340" rw_flags="RW" width="4" name="CPUID" comment="Main ID Register"/>
|
||||
<register addr="0341" rw_flags="RW" width="4" name="CACHETYPE" comment="Cache Type Register"/>
|
||||
<register addr="0343" rw_flags="RW" width="4" name="TLBTYPE" comment="TLB Type Register"/>
|
||||
<register addr="0348" rw_flags="RW" width="4" name="ID_PFR0" comment="Processor Feature Register 0"/>
|
||||
<register addr="0349" rw_flags="RW" width="4" name="ID_PFR1" comment="Processor Feature Register 1"/>
|
||||
<register addr="034a" rw_flags="RW" width="4" name="ID_DFR0" comment="Debug Feature Register 0"/>
|
||||
<register addr="034b" rw_flags="RW" width="4" name="ID_AFR0" comment="Auxiliary Feature Register 0"/>
|
||||
<register addr="034c" rw_flags="RW" width="4" name="ID_MMFR0" comment="Processor Feature Register 0"/>
|
||||
<register addr="034d" rw_flags="RW" width="4" name="ID_MMFR1" comment="Processor Feature Register 1"/>
|
||||
<register addr="034e" rw_flags="RW" width="4" name="ID_MMFR2" comment="Processor Feature Register 2"/>
|
||||
<register addr="034f" rw_flags="RW" width="4" name="ID_MMFR3" comment="Processor Feature Register 3"/>
|
||||
<register addr="0350" rw_flags="RW" width="4" name="ID_ISAR0" comment="ISA Feature Register 0"/>
|
||||
<register addr="0351" rw_flags="RW" width="4" name="ID_ISAR1" comment="ISA Feature Register 1"/>
|
||||
<register addr="0352" rw_flags="RW" width="4" name="ID_ISAR2" comment="ISA Feature Register 2"/>
|
||||
<register addr="0353" rw_flags="RW" width="4" name="ID_ISAR3" comment="ISA Feature Register 3"/>
|
||||
<register addr="0354" rw_flags="RW" width="4" name="ID_ISAR4" comment="ISA Feature Register 4"/>
|
||||
<register addr="0355" rw_flags="RW" width="4" name="ID_ISAR5" comment="ISA Feature Register 5"/>
|
||||
</block>
|
||||
|
||||
<block name="Coresight Management Registers">
|
||||
<register addr="03bf" rw_flags="RW" width="4" name="DBGITMISCIN" comment="Integration Test Input Register"/>
|
||||
<register addr="03c0" rw_flags="RW" width="4" name="DBGITCTRL" comment="Integration Mode Control Register"/>
|
||||
<register addr="03e8" rw_flags="RW" width="4" name="DBGCLAIMSET" comment="Claim Tag Set Register"/>
|
||||
<register addr="03e9" rw_flags="RW" width="4" name="DBGCLAIMCLR" comment="Claim Tag Clear Register"/>
|
||||
<register addr="03ed" rw_flags="RW" width="4" name="DBGLSR" comment="Lock Status Register"/>
|
||||
<register addr="03ee" rw_flags="RW" width="4" name="DBGAUTHSTATUS" comment="Authentication Status Register"/>
|
||||
<register addr="03f2" rw_flags="RW" width="4" name="DBGDEVID" comment="Device Identifier (RESERVED)"/>
|
||||
<register addr="03f3" rw_flags="RW" width="4" name="DBGDEVTYPE" comment="Device Type"/>
|
||||
<register addr="03f8" rw_flags="RW" width="4" name="PID0" comment="Peripheral ID0"/>
|
||||
<register addr="03f9" rw_flags="RW" width="4" name="PID1" comment="Peripheral ID1"/>
|
||||
<register addr="03fa" rw_flags="RW" width="4" name="PID2" comment="Peripheral ID2"/>
|
||||
<register addr="03fb" rw_flags="RW" width="4" name="PID3" comment="Peripheral ID3"/>
|
||||
<register addr="03f4" rw_flags="RW" width="4" name="PID4" comment="Peripheral ID4"/>
|
||||
<register addr="03fc" rw_flags="RW" width="4" name="COMPONENTID0" comment="Component ID0"/>
|
||||
<register addr="03fd" rw_flags="RW" width="4" name="COMPONENTID1" comment="Component ID1"/>
|
||||
<register addr="03fe" rw_flags="RW" width="4" name="COMPONENTID2" comment="Component ID2"/>
|
||||
<register addr="03ff" rw_flags="RW" width="4" name="COMPONENTID3" comment="Component ID3"/>
|
||||
<register addr="0000" rw_flags="RW" width="4" name="DBGDIDR" comment="Debug ID Register"/>
|
||||
<register addr="0022" rw_flags="RW" width="4" name="DBGDSCR" comment="Debug Status and Control Register"/>
|
||||
<register addr="0007" rw_flags="RW" width="4" name="DBGVCR" comment="Vector Catch Register"/>
|
||||
<register addr="0023" rw_flags="RW" width="4" name="DBGDTRTX" comment="Host -> Target Data Transfer Register"/>
|
||||
<register addr="000a" rw_flags="RW" width="4" name="DBGDSCCR" comment="Debug State Cache Control Register"/>
|
||||
<register addr="00c1" rw_flags="RW" width="4" name="DBGOSLSR" comment="Operating System Lock Status Register"/>
|
||||
<register addr="00c4" rw_flags="RW" width="4" name="DBGPRCR" comment="Device Power-Down and Reset Control Register"/>
|
||||
</block>
|
||||
|
||||
<block name="Breakpoint Registers">
|
||||
<register addr="0040" rw_flags="RW" width="4" name="DBGBVR0" comment="Breakpoint Value Register 0"/>
|
||||
<register addr="0050" rw_flags="RW" width="4" name="DBGBCR0" comment="Breakpoint Control Register 0"/>
|
||||
<register addr="0041" rw_flags="RW" width="4" name="DBGBVR1" comment="Breakpoint Value Register 1"/>
|
||||
<register addr="0051" rw_flags="RW" width="4" name="DBGBCR1" comment="Breakpoint Control Register 1"/>
|
||||
<register addr="0042" rw_flags="RW" width="4" name="DBGBVR2" comment="Breakpoint Value Register 2"/>
|
||||
<register addr="0052" rw_flags="RW" width="4" name="DBGBCR2" comment="Breakpoint Control Register 2"/>
|
||||
<register addr="0043" rw_flags="RW" width="4" name="DBGBVR3" comment="Breakpoint Value Register 3"/>
|
||||
<register addr="0053" rw_flags="RW" width="4" name="DBGBCR3" comment="Breakpoint Control Register 3"/>
|
||||
<register addr="0044" rw_flags="RW" width="4" name="DBGBVR4" comment="Breakpoint Value Register 4"/>
|
||||
<register addr="0054" rw_flags="RW" width="4" name="DBGBCR4" comment="Breakpoint Control Register 4"/>
|
||||
<register addr="0045" rw_flags="RW" width="4" name="DBGBVR5" comment="Breakpoint Value Register 5"/>
|
||||
<register addr="0055" rw_flags="RW" width="4" name="DBGBCR5" comment="Breakpoint Control Register 5"/>
|
||||
<register addr="0046" rw_flags="RW" width="4" name="DBGBVR6" comment="Breakpoint Value Register 6"/>
|
||||
<register addr="0056" rw_flags="RW" width="4" name="DBGBCR6" comment="Breakpoint Control Register 6"/>
|
||||
<register addr="0047" rw_flags="RW" width="4" name="DBGBVR7" comment="Breakpoint Value Register 7"/>
|
||||
<register addr="0057" rw_flags="RW" width="4" name="DBGBCR7" comment="Breakpoint Control Register 7"/>
|
||||
</block>
|
||||
|
||||
<block name="Watchpoint Control Registers">
|
||||
<register addr="0060" rw_flags="RW" width="4" name="DBGWVR0" comment="Watchpoint Value Register 0"/>
|
||||
<register addr="0070" rw_flags="RW" width="4" name="DBGWCR0" comment="Watchpoint Control Register 0"/>
|
||||
<register addr="0061" rw_flags="RW" width="4" name="DBGWVR1" comment="Watchpoint Value Register 1"/>
|
||||
<register addr="0071" rw_flags="RW" width="4" name="DBGWCR1" comment="Watchpoint Control Register 1"/>
|
||||
<register addr="0062" rw_flags="RW" width="4" name="DBGWVR2" comment="Watchpoint Value Register 2"/>
|
||||
<register addr="0072" rw_flags="RW" width="4" name="DBGWCR2" comment="Watchpoint Control Register 2"/>
|
||||
<register addr="0063" rw_flags="RW" width="4" name="DBGWVR3" comment="Watchpoint Value Register 3"/>
|
||||
<register addr="0073" rw_flags="RW" width="4" name="DBGWCR3" comment="Watchpoint Control Register 3"/>
|
||||
<register addr="0064" rw_flags="RW" width="4" name="DBGWVR4" comment="Watchpoint Value Register 4"/>
|
||||
<register addr="0074" rw_flags="RW" width="4" name="DBGWCR4" comment="Watchpoint Control Register 4"/>
|
||||
<register addr="0065" rw_flags="RW" width="4" name="DBGWVR5" comment="Watchpoint Value Register 5"/>
|
||||
<register addr="0075" rw_flags="RW" width="4" name="DBGWCR5" comment="Watchpoint Control Register 5"/>
|
||||
<register addr="0066" rw_flags="RW" width="4" name="DBGWVR6" comment="Watchpoint Value Register 6"/>
|
||||
<register addr="0076" rw_flags="RW" width="4" name="DBGWCR6" comment="Watchpoint Control Register 6"/>
|
||||
<register addr="0067" rw_flags="RW" width="4" name="DBGWVR7" comment="Watchpoint Value Register 7"/>
|
||||
<register addr="0077" rw_flags="RW" width="4" name="DBGWCR7" comment="Watchpoint Control Register 7"/>
|
||||
<register addr="0006" rw_flags="RW" width="4" name="DBGWFAR" comment="Watchpoint Fault Address Register"/>
|
||||
</block>
|
||||
</coprocessor>
|
||||
|
||||
<memory name="Vectored interrupt controller" class="D">
|
||||
<!-- From ARM PrimeCell VectoredInterrupt Controller (PL192) TRM -->
|
||||
<block name ="Common">
|
||||
<register addr="dfff0000" rw_flags="R" width="4" name="VICIRQSTATUS" comment="IRQ Status Register"/>
|
||||
<register addr="dfff0004" rw_flags="R" width="4" name="VICFIQSTATUS" comment="FIQ Status Register"/>
|
||||
<register addr="dfff0008" rw_flags="R" width="4" name="VICRAWINTR" comment="Raw Interrupt Status Register"/>
|
||||
<register addr="dfff000C" rw_flags="RW" width="4" name="VICINTSELECT" comment="Interrupt Select Register"/>
|
||||
<register addr="dfff0010" rw_flags="RW" width="4" name="VICINTENABLE" comment="Interrupt Enable Register"/>
|
||||
<register addr="dfff0014" rw_flags="W" width="4" name="VICINTENCLEAR" comment="Interrupt Enable Clear Register"/>
|
||||
<register addr="dfff0018" rw_flags="RW" width="4" name="VICSOFTINT" comment="Software Interrupt Register"/>
|
||||
<register addr="dfff001C" rw_flags="W" width="4" name="VICSOFTINTCLEAR" comment="Software Interrupt Clear Register"/>
|
||||
<register addr="dfff0020" rw_flags="RW" width="1" name="VICPROTECTION" comment="Protection Enable Register"/>
|
||||
<register addr="dfff0024" rw_flags="RW" width="2" name="VICSWPRIORITY MASK" comment="Software Priority Mask Register"/>
|
||||
<register addr="dfff0028" rw_flags="RW" width="1" name="VICPRIORITYDAISY" comment="Vector Priority Register for Daisy Chain"/>
|
||||
</block>
|
||||
<block name ="Vector addresses">
|
||||
<register addr="dfff0100" rw_flags="RW" width="4" name="VICVECTADDR0" comment="Vector Address 0 Register"/>
|
||||
<register addr="dfff0104" rw_flags="RW" width="4" name="VICVECTADDR1" comment="Vector Address 1 Register"/>
|
||||
<register addr="dfff0108" rw_flags="RW" width="4" name="VICVECTADDR2" comment="Vector Address 2 Register"/>
|
||||
<register addr="dfff010C" rw_flags="RW" width="4" name="VICVECTADDR3" comment="Vector Address 3 Register"/>
|
||||
<register addr="dfff0110" rw_flags="RW" width="4" name="VICVECTADDR4" comment="Vector Address 4 Register"/>
|
||||
<register addr="dfff0114" rw_flags="RW" width="4" name="VICVECTADDR5" comment="Vector Address 5 Register"/>
|
||||
<register addr="dfff0118" rw_flags="RW" width="4" name="VICVECTADDR6" comment="Vector Address 6 Register"/>
|
||||
<register addr="dfff011C" rw_flags="RW" width="4" name="VICVECTADDR7" comment="Vector Address 7 Register"/>
|
||||
<register addr="dfff0120" rw_flags="RW" width="4" name="VICVECTADDR8" comment="Vector Address 8 Register"/>
|
||||
<register addr="dfff0124" rw_flags="RW" width="4" name="VICVECTADDR9" comment="Vector Address 9 Register"/>
|
||||
<register addr="dfff0128" rw_flags="RW" width="4" name="VICVECTADDR10" comment="Vector Address 10 Register"/>
|
||||
<register addr="dfff012C" rw_flags="RW" width="4" name="VICVECTADDR11" comment="Vector Address 11 Register"/>
|
||||
<register addr="dfff0130" rw_flags="RW" width="4" name="VICVECTADDR12" comment="Vector Address 12 Register"/>
|
||||
<register addr="dfff0134" rw_flags="RW" width="4" name="VICVECTADDR13" comment="Vector Address 13 Register"/>
|
||||
<register addr="dfff0138" rw_flags="RW" width="4" name="VICVECTADDR14" comment="Vector Address 14 Register"/>
|
||||
<register addr="dfff013C" rw_flags="RW" width="4" name="VICVECTADDR15" comment="Vector Address 15 Register"/>
|
||||
<register addr="dfff0140" rw_flags="RW" width="4" name="VICVECTADDR16" comment="Vector Address 16 Register"/>
|
||||
<register addr="dfff0144" rw_flags="RW" width="4" name="VICVECTADDR17" comment="Vector Address 17 Register"/>
|
||||
<register addr="dfff0148" rw_flags="RW" width="4" name="VICVECTADDR18" comment="Vector Address 18 Register"/>
|
||||
<register addr="dfff014C" rw_flags="RW" width="4" name="VICVECTADDR19" comment="Vector Address 19 Register"/>
|
||||
<register addr="dfff0150" rw_flags="RW" width="4" name="VICVECTADDR20" comment="Vector Address 20 Register"/>
|
||||
<register addr="dfff0154" rw_flags="RW" width="4" name="VICVECTADDR21" comment="Vector Address 21 Register"/>
|
||||
<register addr="dfff0158" rw_flags="RW" width="4" name="VICVECTADDR22" comment="Vector Address 22 Register"/>
|
||||
<register addr="dfff015C" rw_flags="RW" width="4" name="VICVECTADDR23" comment="Vector Address 23 Register"/>
|
||||
<register addr="dfff0160" rw_flags="RW" width="4" name="VICVECTADDR24" comment="Vector Address 24 Register"/>
|
||||
<register addr="dfff0164" rw_flags="RW" width="4" name="VICVECTADDR25" comment="Vector Address 25 Register"/>
|
||||
<register addr="dfff0168" rw_flags="RW" width="4" name="VICVECTADDR26" comment="Vector Address 26 Register"/>
|
||||
<register addr="dfff016C" rw_flags="RW" width="4" name="VICVECTADDR27" comment="Vector Address 27 Register"/>
|
||||
<register addr="dfff0170" rw_flags="RW" width="4" name="VICVECTADDR28" comment="Vector Address 28 Register"/>
|
||||
<register addr="dfff0174" rw_flags="RW" width="4" name="VICVECTADDR29" comment="Vector Address 29 Register"/>
|
||||
<register addr="dfff0178" rw_flags="RW" width="4" name="VICVECTADDR30" comment="Vector Address 30 Register"/>
|
||||
<register addr="dfff017C" rw_flags="RW" width="4" name="VICVECTADDR31" comment="Vector Address 31 Register"/>
|
||||
</block>
|
||||
<block name ="Vector priorities">
|
||||
<register addr="dfff0200" rw_flags="RW" width="1" name="VICVECTPRIORITY0" comment="Vector Priority 0 Register"/>
|
||||
<register addr="dfff0204" rw_flags="RW" width="1" name="VICVECTPRIORITY1" comment="Vector Priority 1 Register"/>
|
||||
<register addr="dfff0208" rw_flags="RW" width="1" name="VICVECTPRIORITY2" comment="Vector Priority 2 Register"/>
|
||||
<register addr="dfff020C" rw_flags="RW" width="1" name="VICVECTPRIORITY3" comment="Vector Priority 3 Register"/>
|
||||
<register addr="dfff0210" rw_flags="RW" width="1" name="VICVECTPRIORITY4" comment="Vector Priority 4 Register"/>
|
||||
<register addr="dfff0214" rw_flags="RW" width="1" name="VICVECTPRIORITY5" comment="Vector Priority 5 Register"/>
|
||||
<register addr="dfff0218" rw_flags="RW" width="1" name="VICVECTPRIORITY6" comment="Vector Priority 6 Register"/>
|
||||
<register addr="dfff021C" rw_flags="RW" width="1" name="VICVECTPRIORITY7" comment="Vector Priority 7 Register"/>
|
||||
<register addr="dfff0220" rw_flags="RW" width="1" name="VICVECTPRIORITY8" comment="Vector Priority 8 Register"/>
|
||||
<register addr="dfff0224" rw_flags="RW" width="1" name="VICVECTPRIORITY9" comment="Vector Priority 9 Register"/>
|
||||
<register addr="dfff0228" rw_flags="RW" width="1" name="VICVECTPRIORITY10" comment="Vector Priority 10 Register"/>
|
||||
<register addr="dfff022C" rw_flags="RW" width="1" name="VICVECTPRIORITY11" comment="Vector Priority 11 Register"/>
|
||||
<register addr="dfff0230" rw_flags="RW" width="1" name="VICVECTPRIORITY12" comment="Vector Priority 12 Register"/>
|
||||
<register addr="dfff0234" rw_flags="RW" width="1" name="VICVECTPRIORITY13" comment="Vector Priority 13 Register"/>
|
||||
<register addr="dfff0238" rw_flags="RW" width="1" name="VICVECTPRIORITY14" comment="Vector Priority 14 Register"/>
|
||||
<register addr="dfff023C" rw_flags="RW" width="1" name="VICVECTPRIORITY15" comment="Vector Priority 15 Register"/>
|
||||
<register addr="dfff0240" rw_flags="RW" width="1" name="VICVECTPRIORITY16" comment="Vector Priority 16 Register"/>
|
||||
<register addr="dfff0244" rw_flags="RW" width="1" name="VICVECTPRIORITY17" comment="Vector Priority 17 Register"/>
|
||||
<register addr="dfff0248" rw_flags="RW" width="1" name="VICVECTPRIORITY18" comment="Vector Priority 18 Register"/>
|
||||
<register addr="dfff024C" rw_flags="RW" width="1" name="VICVECTPRIORITY19" comment="Vector Priority 19 Register"/>
|
||||
<register addr="dfff0250" rw_flags="RW" width="1" name="VICVECTPRIORITY20" comment="Vector Priority 20 Register"/>
|
||||
<register addr="dfff0254" rw_flags="RW" width="1" name="VICVECTPRIORITY21" comment="Vector Priority 21 Register"/>
|
||||
<register addr="dfff0258" rw_flags="RW" width="1" name="VICVECTPRIORITY22" comment="Vector Priority 22 Register"/>
|
||||
<register addr="dfff025C" rw_flags="RW" width="1" name="VICVECTPRIORITY23" comment="Vector Priority 23 Register"/>
|
||||
<register addr="dfff0260" rw_flags="RW" width="1" name="VICVECTPRIORITY24" comment="Vector Priority 24 Register"/>
|
||||
<register addr="dfff0264" rw_flags="RW" width="1" name="VICVECTPRIORITY25" comment="Vector Priority 25 Register"/>
|
||||
<register addr="dfff0268" rw_flags="RW" width="1" name="VICVECTPRIORITY26" comment="Vector Priority 26 Register"/>
|
||||
<register addr="dfff026C" rw_flags="RW" width="1" name="VICVECTPRIORITY27" comment="Vector Priority 27 Register"/>
|
||||
<register addr="dfff0270" rw_flags="RW" width="1" name="VICVECTPRIORITY28" comment="Vector Priority 28 Register"/>
|
||||
<register addr="dfff0274" rw_flags="RW" width="1" name="VICVECTPRIORITY29" comment="Vector Priority 29 Register"/>
|
||||
<register addr="dfff0278" rw_flags="RW" width="1" name="VICVECTPRIORITY30" comment="Vector Priority 30 Register"/>
|
||||
<register addr="dfff027C" rw_flags="RW" width="1" name="VICVECTPRIORITY31" comment="Vector Priority 31 Register"/>
|
||||
</block>
|
||||
<block name ="Coresight Management Registers">
|
||||
<register addr="dfff0F00" rw_flags="RW" width="4" name="VICADDRESS" comment="Vector Address Register"/>
|
||||
<register addr="dfff0FE0" rw_flags="R" width="1" name="VICPERIPHID0" comment="Peripheral Identification Register bits 7:0"/>
|
||||
<register addr="dfff0FE4" rw_flags="R" width="1" name="VICPERIPHID1" comment="Peripheral Identification Register bits 15:8"/>
|
||||
<register addr="dfff0FE8" rw_flags="R" width="1" name="VICPERIPHID2" comment="Peripheral Identification Register bits 23:16"/>
|
||||
<register addr="dfff0FEC" rw_flags="R" width="1" name="VICPERIPHID3" comment="Peripheral Identification Register bits 31:24"/>
|
||||
<register addr="dfff0FF0" rw_flags="R" width="1" name="VICPCELLID0" comment="PrimeCell Identification Register bits 7:0"/>
|
||||
<register addr="dfff0FF4" rw_flags="R" width="1" name="VICPCELLID1" comment="PrimeCell Identification Register bits 15:8"/>
|
||||
<register addr="dfff0FF8" rw_flags="R" width="1" name="VICPCELLID2" comment="PrimeCell Identification Register bits 23:16"/>
|
||||
<register addr="dfff0FFC" rw_flags="R" width="1" name="VICPCELLID3" comment="PrimeCell Identification Register bits 31:24"/>
|
||||
</block>
|
||||
</memory>
|
||||
</processor>
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!--
|
||||
(c) SCSC 2015 Maxwell moredump memory definitions
|
||||
From http://wiki/Maxwell140MemoryMap
|
||||
-->
|
||||
|
||||
<memory xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.samsung.com Memory.xsd">
|
||||
<!-- Define the mmap range - DO NOT CHANGE THIS -->
|
||||
<mmap startAddr="80000000" endAddr="803FFFFF"/>
|
||||
<R4>
|
||||
<!-- Memory specific to (and will only be read via) R4 -->
|
||||
<region startAddr="00000000" endAddr="00007fff" name="TCMA" comment=""/>
|
||||
<region startAddr="00018000" endAddr="0001ffff" name="TCMB1" comment=""/>
|
||||
</R4>
|
||||
<M4>
|
||||
<!-- Memory specific to (and will only be read via) M4 -->
|
||||
</M4>
|
||||
<!-- Memory that can be read via R4 or M4 (or possibly mmap) -->
|
||||
<region startAddr="07FE0000" endAddr="07FFFFFF" name="RAMCB" comment="128KB" />
|
||||
<region startAddr="08000000" endAddr="08013FFF" name="RAMSB" comment="80KB" />
|
||||
<region startAddr="80000000" endAddr="803FFFFF" name="DRAM" comment="4MB" />
|
||||
<region startAddr="C0000000" endAddr="C0017FFF" name="RAMSW ASIC" comment="96KB" />
|
||||
|
||||
<region startAddr="A0580000" endAddr="A0580003" name="MAILBOX_AP_APM 1" comment="MCU Controller" />
|
||||
<region startAddr="A0580008" endAddr="A058002F" name="MAILBOX_AP_APM 2" comment="Interrupt registers" />
|
||||
<region startAddr="A058004C" endAddr="A0580053" name="MAILBOX_AP_APM 3" comment="INIT/VERSION" />
|
||||
<region startAddr="A0580080" endAddr="A058009F" name="MAILBOX_AP_APM 4" comment="Shared registers" />
|
||||
</memory>
|
||||
586
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/hardware/moredump/rf_chip_registers.xml
vendored
Normal file
586
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/hardware/moredump/rf_chip_registers.xml
vendored
Normal file
|
|
@ -0,0 +1,586 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!--
|
||||
(c) SCSC 2015-2016 autogenerated by moredump.py as part of 'drun prep'.
|
||||
Changes made to this file may cause incorrect behaviour and will be lost if it is regenerated.
|
||||
|
||||
XML file defining registers for chip subsystem moredump
|
||||
Chip hash: 8423
|
||||
|
||||
|
||||
-->
|
||||
|
||||
<subsystem xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.samsung.com Registers.xsd"
|
||||
name="chip">
|
||||
<block name="alwayson_rf" comment="">
|
||||
<register addr="00000000" rw_flags="R" width="2" name="CHIP_VERSION" comment="Chip Version and ID (EVT0=0x00B0, EVT1=0x10B0, EVT1.1=0x11B0, EVT2=0x20B0)"/>
|
||||
<register addr="00000004" rw_flags="RW" width="2" name="RFIC_CONFIG" comment="Main BT/WL configuration register for RFIC."/>
|
||||
<register addr="00000008" rw_flags="R" width="1" name="RFIC_CORE_PWR_STATUS" comment="Set when the BT/WL core power domain has powered up"/>
|
||||
<register addr="0000000c" rw_flags="R" width="1" name="RFIC_PLL_UNLOCK_STATUS" comment="Set on falling edge of Aux PLL lock indicator when RFIC_CONFIG_PLL_UNLOCK_EN=1."/>
|
||||
<register addr="00000010" rw_flags="RW" width="2" name="RFIC_CLKGEN_ENABLES" comment="Clock enables"/>
|
||||
<register addr="00000014" rw_flags="RW" width="1" name="RFIC_CLKGEN_INVERT_CTRL" comment="Clock enables"/>
|
||||
<register addr="00000018" rw_flags="RW" width="1" name="RFIC_CLKGEN_SYSTEM_TIME_DIV_RATIO" comment="Divide ratio for system timer (from 80MHz clock)"/>
|
||||
<register addr="0000001c" rw_flags="RW" width="1" name="RFIC_CLKGEN_SYSTEM_TIME_EN" comment="Enable System Timer"/>
|
||||
<register addr="00000020" rw_flags="RW" width="4" name="RFIC_CLKGEN_SYSTEM_TIME_INIT_VAL" comment="Set initial value for System Timer"/>
|
||||
<register addr="00000024" rw_flags="R" width="4" name="RFIC_CLKGEN_SYSTEM_TIME" comment="Current value of System Timer"/>
|
||||
<register addr="00000028" rw_flags="R" width="1" name="AUX_ANA_STATUS0" comment=""/>
|
||||
<register addr="0000002c" rw_flags="RW" width="4" name="AUX_ANA_ENABLES" comment=""/>
|
||||
<register addr="00000030" rw_flags="RW" width="4" name="AUX_ANA_SH_CFG0" comment=""/>
|
||||
<register addr="00000034" rw_flags="RW" width="4" name="AUX_ANA_SH_CFG1" comment=""/>
|
||||
<register addr="00000038" rw_flags="RW" width="2" name="AUX_ANA_SH_CFG2" comment=""/>
|
||||
<register addr="0000003c" rw_flags="RW" width="4" name="AUX_ANA_CFG0" comment=""/>
|
||||
<register addr="00000040" rw_flags="RW" width="4" name="RFIC_PAD_MUX_CTRL" comment="PIO mux controls for PIO0 to PIO3"/>
|
||||
<register addr="00000044" rw_flags="RW" width="1" name="RFIC_SCAN_MODE_ENABLES" comment="DFT Scan mode configuration register. *FIRMWARE DO NOT TOUCH THIS*"/>
|
||||
<register addr="00000048" rw_flags="RW" width="4" name="RFIC_SCAN_CONFIG" comment="DFT Scan mode configuration register. *FIRMWARE DO NOT TOUCH THIS*"/>
|
||||
<register addr="0000004c" rw_flags="RW" width="1" name="RFIC_SCAN_RESERVE_REGS" comment="DFT Scan mode reserve registers. *FIRMWARE DO NOT TOUCH THIS*"/>
|
||||
<register addr="00000050" rw_flags="R" width="2" name="RFIC_SCAN_OBSERVE_REGS" comment="DFT Scan mode observable regsiters. *FIRMWARE DO NOT TOUCH THIS*"/>
|
||||
<register addr="00000054" rw_flags="R" width="4" name="RFIC_SCSC0" comment="Chris Hunter/Damien Smith"/>
|
||||
<register addr="00000058" rw_flags="R" width="4" name="RFIC_SCSC1" comment="Michael Cowell/Andy Barnish"/>
|
||||
<register addr="0000005c" rw_flags="R" width="4" name="RFIC_SCSC2" comment="Roger Wood/Colin Tapp"/>
|
||||
<register addr="00000060" rw_flags="R" width="4" name="RFIC_SCSC3" comment="Stelios Staveris/Hayley Bird"/>
|
||||
<register addr="00000064" rw_flags="R" width="4" name="RFIC_SCSC4" comment="Dave Price/Riccardo Micci"/>
|
||||
</block>
|
||||
<block name="bt_rf" comment="">
|
||||
<register addr="00003000" rw_flags="RW" width="1" name="BT_RF_CONFIG" comment=""/>
|
||||
<register addr="00003004" rw_flags="RW" width="1" name="BT_RF_DEBUG_SEL" comment=""/>
|
||||
<register addr="00003008" rw_flags="RW" width="1" name="BT_TX_DEBUG_SEL" comment="Bluetooth Transmit debug mux select"/>
|
||||
<register addr="0000300c" rw_flags="RW" width="1" name="BT_TX_INTERFACE_CTRL" comment=""/>
|
||||
<register addr="00003010" rw_flags="RW" width="4" name="BT_TX_MOD_TEST" comment=""/>
|
||||
<register addr="00003014" rw_flags="RW" width="1" name="BT_TX_PATTERN_GEN_CFG" comment=""/>
|
||||
<register addr="00003018" rw_flags="RW" width="1" name="BT_TX_CTRL_DEBUG_SEL" comment="Bluetooth Transmit Control debug mux select."/>
|
||||
<register addr="0000301c" rw_flags="RW" width="4" name="BT_TX_CTRL_CFG" comment="Bluetooth Transmit Control configuration."/>
|
||||
<register addr="00003020" rw_flags="RW" width="2" name="BT_TX_EDR3_ALIGN_CFG" comment="Bluetooth Transmit EDR3 Symbol Alignment workaround logic (to workaround Java EVT0 EDR3 bitstream bug)"/>
|
||||
<register addr="00003024" rw_flags="R" width="1" name="BT_TX_CTRL_STATUS" comment="The current Bluetooth Tx radio mode"/>
|
||||
<register addr="00003028" rw_flags="RW" width="1" name="BT_TX_TIMER_CFG" comment="Bluetooth Transmit Radio Timer configuration."/>
|
||||
<register addr="0000302c" rw_flags="R" width="1" name="BT_TX_TIMER_STATUS" comment="Bluetooth Transmit Radio Timer status."/>
|
||||
<register addr="00003030" rw_flags="RW" width="1" name="BT_TX_TIMER_SW_TRIGGERS" comment="Bluetooth Transmit Radio Timer software triggers."/>
|
||||
<register addr="00003034" rw_flags="RW" width="4" name="BT_TX_TIMER_EVENT_TIME" comment="Set the required Tx event time. Used when timing to an event, not used when timing from an event."/>
|
||||
<register addr="00003038" rw_flags="RW" width="1" name="BT_TX_TIMER_DIG_SW_ORIDE" comment="Bluetooth Transmit Radio Timer digital enable software overrides."/>
|
||||
<register addr="0000303c" rw_flags="RW" width="2" name="BT_TX_TIMER_TRIGGER_PLL_ABORT" comment="Bluetooth Tx Radio Timer - PLL Abort trigger configuration."/>
|
||||
<register addr="00003040" rw_flags="RW" width="2" name="BT_TX_TIMER_TRIGGER_START" comment="Bluetooth Tx Radio Timer - Start trigger configuration."/>
|
||||
<register addr="00003044" rw_flags="RW" width="2" name="BT_TX_TIMER_TRIGGER_SW_ABORT" comment="Bluetooth Tx Radio Timer - Software Abort trigger configuration."/>
|
||||
<register addr="00003048" rw_flags="RW" width="2" name="BT_TX_TIMER_TRIGGER_DONE" comment="Bluetooth Tx Radio Timer - Done trigger configuration."/>
|
||||
<register addr="0000304c" rw_flags="RW" width="2" name="BT_TX_TIMER_TRIGGER_COEX_ABORT" comment="Bluetooth Tx Radio Timer - Coex Abort trigger configuration."/>
|
||||
<register addr="00003050" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT0_ANA_EN" comment="Transmit slot 0 Analogue Enables"/>
|
||||
<register addr="00003054" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT1_ANA_EN" comment="Transmit slot 1 Analogue Enables"/>
|
||||
<register addr="00003058" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT2_ANA_EN" comment="Transmit slot 2 Analogue Enables"/>
|
||||
<register addr="0000305c" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT3_ANA_EN" comment="Transmit slot 3 Analogue Enables"/>
|
||||
<register addr="00003060" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT4_ANA_EN" comment="Transmit slot 4 Analogue Enables"/>
|
||||
<register addr="00003064" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT5_ANA_EN" comment="Transmit slot 5 Analogue Enables"/>
|
||||
<register addr="00003068" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT6_ANA_EN" comment="Transmit slot 6 Analogue Enables"/>
|
||||
<register addr="0000306c" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT7_ANA_EN" comment="Transmit slot 7 Analogue Enables"/>
|
||||
<register addr="00003070" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT8_ANA_EN" comment="Transmit slot 8 Analogue Enables"/>
|
||||
<register addr="00003074" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT9_ANA_EN" comment="Transmit slot 9 Analogue Enables"/>
|
||||
<register addr="00003078" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT10_ANA_EN" comment="Transmit slot 10 Analogue Enables"/>
|
||||
<register addr="0000307c" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT11_ANA_EN" comment="Transmit slot 11 Analogue Enables"/>
|
||||
<register addr="00003080" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT0_DIG_EN" comment="Transmit slot 0 Digital Enables"/>
|
||||
<register addr="00003084" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT1_DIG_EN" comment="Transmit slot 1 Digital Enables"/>
|
||||
<register addr="00003088" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT2_DIG_EN" comment="Transmit slot 2 Digital Enables"/>
|
||||
<register addr="0000308c" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT3_DIG_EN" comment="Transmit slot 3 Digital Enables"/>
|
||||
<register addr="00003090" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT4_DIG_EN" comment="Transmit slot 4 Digital Enables"/>
|
||||
<register addr="00003094" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT5_DIG_EN" comment="Transmit slot 5 Digital Enables"/>
|
||||
<register addr="00003098" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT6_DIG_EN" comment="Transmit slot 6 Digital Enables"/>
|
||||
<register addr="0000309c" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT7_DIG_EN" comment="Transmit slot 7 Digital Enables"/>
|
||||
<register addr="000030a0" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT8_DIG_EN" comment="Transmit slot 8 Digital Enables"/>
|
||||
<register addr="000030a4" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT9_DIG_EN" comment="Transmit slot 9 Digital Enables"/>
|
||||
<register addr="000030a8" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT10_DIG_EN" comment="Transmit slot 10 Digital Enables"/>
|
||||
<register addr="000030ac" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT11_DIG_EN" comment="Transmit slot 11 Digital Enables"/>
|
||||
<register addr="000030b0" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT0_DELAY" comment="Transmit slot 0 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030b4" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT1_DELAY" comment="Transmit slot 1 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030b8" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT2_DELAY" comment="Transmit slot 2 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030bc" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT3_DELAY" comment="Transmit slot 3 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030c0" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT4_DELAY" comment="Transmit slot 4 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030c4" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT5_DELAY" comment="Transmit slot 5 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030c8" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT6_DELAY" comment="Transmit slot 6 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030cc" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT7_DELAY" comment="Transmit slot 7 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030d0" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT8_DELAY" comment="Transmit slot 8 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030d4" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT9_DELAY" comment="Transmit slot 9 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030d8" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT10_DELAY" comment="Transmit slot 10 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030dc" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT11_DELAY" comment="Transmit slot 11 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030e0" rw_flags="RW" width="2" name="BT_TX_CONFIG1" comment=""/>
|
||||
<register addr="000030e4" rw_flags="RW" width="2" name="BT_TX_CONFIG2" comment=""/>
|
||||
<register addr="000030e8" rw_flags="RW" width="1" name="BT_TX_CONFIG3" comment=""/>
|
||||
<register addr="000030ec" rw_flags="RW" width="1" name="BT_TX_BB_RAMP_CONFIG" comment=""/>
|
||||
<register addr="000030f0" rw_flags="RW" width="2" name="BT_TX_BDR_SCALE_CONFIG" comment=""/>
|
||||
<register addr="000030f4" rw_flags="RW" width="2" name="BT_TX_EDR_SCALE_CONFIG" comment=""/>
|
||||
<register addr="000030f8" rw_flags="RW" width="1" name="BT_TX_MAX_ATT_CONFIG" comment=""/>
|
||||
<register addr="000030fc" rw_flags="RW" width="2" name="BT_TX_GAIN_RAMP" comment=""/>
|
||||
<register addr="00003100" rw_flags="RW" width="1" name="BT_TX_GAIN_RAMP_DELAY" comment=""/>
|
||||
<register addr="00003104" rw_flags="R" width="1" name="BT_TX_GAIN" comment=""/>
|
||||
<register addr="00003108" rw_flags="RW" width="2" name="BT_TX_MR_CONFIG1" comment=""/>
|
||||
<register addr="0000310c" rw_flags="RW" width="2" name="BT_TX_MR_CONFIG2" comment=""/>
|
||||
<register addr="00003110" rw_flags="RW" width="1" name="BT_TX_MR_MOD_DELAY" comment=""/>
|
||||
<register addr="00003114" rw_flags="RW" width="2" name="BT_POLAR_CTRL" comment="General control register"/>
|
||||
<register addr="00003118" rw_flags="RW" width="2" name="BT_POLAR_CTRL2" comment="Second set of general control register"/>
|
||||
<register addr="0000311c" rw_flags="RW" width="2" name="BT_POLAR_MAG_DATA" comment="Magnitude value to be inserted into Polar chain at various points when reg source selected (Only 10 LS bits are used when this is used to drive TX_AM_DAC output)"/>
|
||||
<register addr="00003120" rw_flags="RW" width="2" name="BT_POLAR_PHASE_DATA" comment="Phase value to be inserted into Polar chain at various points when reg source selected"/>
|
||||
<register addr="00003124" rw_flags="RW" width="2" name="BT_POLAR_MUX_1" comment="Mux control register"/>
|
||||
<register addr="00003128" rw_flags="RW" width="2" name="BT_POLAR_MUX_2" comment="Mux control register"/>
|
||||
<register addr="0000312c" rw_flags="RW" width="2" name="BT_POLAR_QUAD_POLAR_I_DATA" comment="Quadrature-Polar converter I data input register"/>
|
||||
<register addr="00003130" rw_flags="RW" width="2" name="BT_POLAR_QUAD_POLAR_Q_DATA" comment="Quadrature-Polar converter Q data input register"/>
|
||||
<register addr="00003134" rw_flags="RW" width="1" name="BT_POLAR_AA_FIR_CONTROL" comment="FIR filter control for AntiAliasing"/>
|
||||
<register addr="00003138" rw_flags="RW" width="1" name="BT_POLAR_AA_FIR_TAP0" comment="AntiAliasing FIR filter, tap 0 of 5"/>
|
||||
<register addr="0000313c" rw_flags="RW" width="1" name="BT_POLAR_AA_FIR_TAP1" comment="AntiAliasing FIR filter, tap 1 of 5"/>
|
||||
<register addr="00003140" rw_flags="RW" width="1" name="BT_POLAR_AA_FIR_TAP2" comment="AntiAliasing FIR filter, tap 2 of 5"/>
|
||||
<register addr="00003144" rw_flags="RW" width="1" name="BT_POLAR_AA_FIR_TAP3" comment="AntiAliasing FIR filter, tap 3 of 5"/>
|
||||
<register addr="00003148" rw_flags="RW" width="1" name="BT_POLAR_AA_FIR_TAP4" comment="AntiAliasing FIR filter, tap 4 of 5"/>
|
||||
<register addr="0000314c" rw_flags="R" width="2" name="BT_POLAR_DEBUG_STATUS" comment="Debug Status bus"/>
|
||||
<register addr="00003150" rw_flags="RW" width="2" name="BT_POLAR_QUAD_POLAR_AMP_CONST" comment="Correction const for Quad-Polar Amp output (const/4096 scales output and includes Cordic magnitude correction)"/>
|
||||
<register addr="00003154" rw_flags="RW" width="2" name="BT_POLAR_QUAD_POLAR_PHASE_CONST" comment="Correction const for Quad-Polar Phase output (const/4096 scales +-180 to +-2047)"/>
|
||||
<register addr="00003158" rw_flags="RW" width="2" name="BT_POLAR_COMPENSATION_DATA_WRITE" comment="Compensation Y LUT write register"/>
|
||||
<register addr="0000315c" rw_flags="R" width="2" name="BT_POLAR_COMPENSATION_DATA_READ" comment="Compensation Y LUT read register"/>
|
||||
<register addr="00003160" rw_flags="RW" width="1" name="BT_POLAR_COMPENSATION_ADDR" comment="Compensation Y LUT address register"/>
|
||||
<register addr="00003164" rw_flags="RW" width="4" name="BT_POLAR_TEST_STIM_LSW" comment="Polar Test stimulus"/>
|
||||
<register addr="00003168" rw_flags="RW" width="1" name="BT_POLAR_TEST_STIM_MSB" comment="Polar Test stimulus"/>
|
||||
<register addr="0000316c" rw_flags="R" width="4" name="BT_POLAR_TEST_CAP_LSW" comment="Polar Test capture"/>
|
||||
<register addr="00003170" rw_flags="R" width="4" name="BT_POLAR_TEST_CAP_MSW" comment="Polar Test capture"/>
|
||||
<register addr="00003174" rw_flags="RW" width="4" name="BT_POLAR_IIR_COEFF1_LSW" comment="TX POLAR IIR filter coefficients (Biquad 1)"/>
|
||||
<register addr="00003178" rw_flags="RW" width="1" name="BT_POLAR_IIR_COEFF1_MSB" comment="TX POLAR IIR filter coefficients (Biquad 1)"/>
|
||||
<register addr="0000317c" rw_flags="RW" width="4" name="BT_POLAR_IIR_COEFF2_LSW" comment="TX POLAR IIR filter coefficients (Biquad 2)"/>
|
||||
<register addr="00003180" rw_flags="RW" width="1" name="BT_POLAR_IIR_COEFF2_MSB" comment="TX POLAR IIR filter coefficients (Biquad 2)"/>
|
||||
<register addr="00003184" rw_flags="RW" width="2" name="BT_POLAR_IIR_FILTER_CFG" comment="TX POLAR IIR filter configuration"/>
|
||||
<register addr="00003188" rw_flags="RW" width="2" name="BT_POLAR_POLAR_QUAD_PHASE_CORR" comment="Signed: Phase correction adjustments for Polar to IQ conversion (shifted left by 2)"/>
|
||||
<register addr="0000318c" rw_flags="RW" width="1" name="BT_POLAR_POLAR_QUAD_AMP_CORR" comment="Signed: Amplitude correction adjustments for Polar to IQ conversion"/>
|
||||
<register addr="00003190" rw_flags="RW" width="2" name="BT_POLAR_POLAR_QUAD_OFFSET" comment="I and Q offset adjustments for Polar to IQ conversion"/>
|
||||
<register addr="00003194" rw_flags="RW" width="2" name="BT_POLAR_POLAR_QUAD_AMP_CONST" comment="Correction const for Polar-Quad Amp output (4096/const unscales output)"/>
|
||||
<register addr="00003198" rw_flags="RW" width="2" name="BT_POLAR_POLAR_QUAD_PHASE_CONST" comment="Correction const for Polar-Quad Phase output - reset default gives x1"/>
|
||||
<register addr="0000319c" rw_flags="RW" width="2" name="BT_POLAR_SIGGEN_CTRL" comment="Cal Siggen sine wave Ctrl"/>
|
||||
<register addr="000031a0" rw_flags="RW" width="2" name="BT_POLAR_SIGGEN_FREQ" comment="Cal Siggen sine wave - frequency to generate"/>
|
||||
<register addr="000031a4" rw_flags="RW" width="1" name="BT_POLAR_INVERT_CTRL" comment="Fallback IQ Inversion control"/>
|
||||
<register addr="000031a8" rw_flags="RW" width="1" name="BT_RF_RX_CFG" comment="Bluetooth Rx configuration."/>
|
||||
<register addr="000031ac" rw_flags="RW" width="1" name="BT_RX_INTERFACE_CTRL" comment="Bluetooth Rx Interface control."/>
|
||||
<register addr="000031b0" rw_flags="RW" width="1" name="BT_RX_DEBUG_SEL" comment="Bluetooth Rx debug mux select."/>
|
||||
<register addr="000031b4" rw_flags="RW" width="2" name="BT_RX_SUPP_CFG" comment="Bluetooth Rx Supplemental Sampler configuration register (for Direction Finding)."/>
|
||||
<register addr="000031b8" rw_flags="RW" width="1" name="BT_RX_CTRL_DEBUG_SEL" comment="Bluetooth Rx Control debug mux select."/>
|
||||
<register addr="000031bc" rw_flags="R" width="4" name="BT_RX_BDR_SYNC_TIME" comment="The time we found BDR Sync (in relation to RFIC System Time)"/>
|
||||
<register addr="000031c0" rw_flags="RW" width="4" name="BT_RX_BDR_SYNC_TIMEOUT_OFFSET" comment="The number of microseconds before the BDR sync timeout is asserted from the point the Rx Digital enable is set (in reference to the RFIC system time)"/>
|
||||
<register addr="000031c4" rw_flags="RW" width="4" name="BT_RX_LR_SYNC_TIMEOUT_OFFSET" comment="The number of microseconds before the LR sync timeout is asserted from the point the Rx Digital enable is set (in reference to the RFIC system time)"/>
|
||||
<register addr="000031c8" rw_flags="RW" width="2" name="BT_RX_CTRL_CFG" comment="Bluetooth Rx Control configuration."/>
|
||||
<register addr="000031cc" rw_flags="RW" width="1" name="BT_RX_EDR3_ALIGN_CFG" comment="Set to enable EDR3 symbol alignment workaround logic for Java EVT0."/>
|
||||
<register addr="000031d0" rw_flags="RW" width="4" name="BT_RX_MLE_ESCO_OFFSET" comment="Set to enable EDR3 symbol alignment workaround logic for Java EVT0."/>
|
||||
<register addr="000031d4" rw_flags="RW" width="4" name="BT_RX_MLE_ACL_OFFSET" comment="Set to enable EDR3 symbol alignment workaround logic for Java EVT0."/>
|
||||
<register addr="000031d8" rw_flags="RW" width="4" name="BT_RX_MR_SYNC_TIMING" comment="BT DPSK synchronization timing configuration"/>
|
||||
<register addr="000031dc" rw_flags="RW" width="1" name="BT_RX_TIMER_CFG" comment="Bluetooth Rx Radio Timer configuration."/>
|
||||
<register addr="000031e0" rw_flags="R" width="1" name="BT_RX_TIMER_STATUS" comment="Bluetooth Rx Radio Timer status."/>
|
||||
<register addr="000031e4" rw_flags="RW" width="1" name="BT_RX_TIMER_SW_TRIGGERS" comment="Bluetooth Rx Radio Timer software triggers."/>
|
||||
<register addr="000031e8" rw_flags="RW" width="4" name="BT_RX_TIMER_EVENT_TIME" comment="Set the required Tx event time. Used when timing to an event, not used when timing from an event."/>
|
||||
<register addr="000031ec" rw_flags="RW" width="1" name="BT_RX_TIMER_DIG_SW_ORIDE" comment="Override timer digital outputs, when masked."/>
|
||||
<register addr="000031f0" rw_flags="RW" width="2" name="BT_RX_TIMER_TRIGGER_PLL_ABORT" comment="Bluetooth Rx Radio Timer - PLL Abort trigger configuration."/>
|
||||
<register addr="000031f4" rw_flags="RW" width="2" name="BT_RX_TIMER_TRIGGER_START" comment="Bluetooth Rx Radio Timer - Start trigger configuration."/>
|
||||
<register addr="000031f8" rw_flags="RW" width="2" name="BT_RX_TIMER_TRIGGER_SW_ABORT" comment="Bluetooth Rx Radio Timer - Softwre Abort trigger configuration."/>
|
||||
<register addr="000031fc" rw_flags="RW" width="2" name="BT_RX_TIMER_TRIGGER_DONE" comment="Bluetooth Rx Radio Timer - Done trigger configuration."/>
|
||||
<register addr="00003200" rw_flags="RW" width="2" name="BT_RX_TIMER_TRIGGER_SYNC_TIMEOUT" comment="Bluetooth Rx Radio Timer - BDR Sync Timeout trigger configuration."/>
|
||||
<register addr="00003204" rw_flags="RW" width="2" name="BT_RX_TIMER_TRIGGER_COEX_ABORT" comment="Bluetooth Rx Radio Timer - Coex Abort trigger configuration."/>
|
||||
<register addr="00003208" rw_flags="RW" width="2" name="BT_RX_TIMER_TRIGGER_MLSE_EARLY" comment="Bluetooth Rx Radio Timer - MLSE Early trigger configuration."/>
|
||||
<register addr="0000320c" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT0_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003210" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT1_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003214" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT2_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003218" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT3_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="0000321c" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT4_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003220" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT5_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003224" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT6_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003228" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT7_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="0000322c" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT8_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003230" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT9_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003234" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT10_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003238" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT11_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="0000323c" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT0_DIG_EN" comment="Receive slot 0 Digital Enables"/>
|
||||
<register addr="00003240" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT1_DIG_EN" comment="Receive slot 1 Digital Enables"/>
|
||||
<register addr="00003244" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT2_DIG_EN" comment="Receive slot 2 Digital Enables"/>
|
||||
<register addr="00003248" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT3_DIG_EN" comment="Receive slot 3 Digital Enables"/>
|
||||
<register addr="0000324c" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT4_DIG_EN" comment="Receive slot 4 Digital Enables"/>
|
||||
<register addr="00003250" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT5_DIG_EN" comment="Receive slot 5 Digital Enables"/>
|
||||
<register addr="00003254" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT6_DIG_EN" comment="Receive slot 6 Digital Enables"/>
|
||||
<register addr="00003258" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT7_DIG_EN" comment="Receive slot 7 Digital Enables"/>
|
||||
<register addr="0000325c" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT8_DIG_EN" comment="Receive slot 8 Digital Enables"/>
|
||||
<register addr="00003260" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT9_DIG_EN" comment="Receive slot 9 Digital Enables"/>
|
||||
<register addr="00003264" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT10_DIG_EN" comment="Receive slot 10 Digital Enables"/>
|
||||
<register addr="00003268" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT11_DIG_EN" comment="Receive slot 11 Digital Enables"/>
|
||||
<register addr="0000326c" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT0_DELAY" comment="Receive slot 0 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003270" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT1_DELAY" comment="Receive slot 1 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003274" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT2_DELAY" comment="Receive slot 2 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003278" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT3_DELAY" comment="Receive slot 3 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="0000327c" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT4_DELAY" comment="Receive slot 4 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003280" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT5_DELAY" comment="Receive slot 5 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003284" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT6_DELAY" comment="Receive slot 6 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003288" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT7_DELAY" comment="Receive slot 7 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="0000328c" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT8_DELAY" comment="Receive slot 8 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003290" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT9_DELAY" comment="Receive slot 9 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003294" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT10_DELAY" comment="Receive slot 10 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003298" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT11_DELAY" comment="Receive slot 11 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="0000329c" rw_flags="RW" width="2" name="BT_RX_MR_FREQ_CONFIG" comment="BT DPSK demodulator frequency offset in bits [12:0] - Bit 15 when *** cleared *** enables spectrum inversion (change sign of Q channel *** after *** SDDCRS mixer)"/>
|
||||
<register addr="000032a0" rw_flags="RW" width="2" name="BT_RX_MR_FREQ_OFFSET" comment="BT DPSK demodulator frequency offset value"/>
|
||||
<register addr="000032a4" rw_flags="RW" width="2" name="BT_CAL_ANALYSER_CFG" comment="This register configures the signal analyser"/>
|
||||
<register addr="000032a8" rw_flags="RW" width="2" name="BT_CAL_ANALYSER_FREQ" comment="This sets the frequency of the tone used by the signal analyser. f = reg_value * (16_000_000)/2^16.This sets the frequency of the tone used by the signal analyser."/>
|
||||
<register addr="000032ac" rw_flags="R" width="4" name="BT_CAL_ANALYSER_RESULT" comment="This register contains the values generated by the signal analyser, Real = [7:0], Imag = [15:8]"/>
|
||||
<register addr="000032b0" rw_flags="RW" width="4" name="BT_RX_DEMOD_CONFIG" comment="BT GFSK demodulator configuration"/>
|
||||
<register addr="000032b4" rw_flags="RW" width="2" name="BT_BDR_FREQ_DISC_CONFIG" comment="Configures GFSK frequency discriminator"/>
|
||||
<register addr="000032b8" rw_flags="RW" width="4" name="BT_BDR_FREQ2_CONFIG" comment="Configures GFSK frequency discriminator"/>
|
||||
<register addr="000032bc" rw_flags="RW" width="2" name="BT_RX_DEMOD_BDR_DECISION_EQ_CONFIG" comment="Configures the decision-directed BDR equaliser"/>
|
||||
<register addr="000032c0" rw_flags="RW" width="1" name="BT_PHASESQUELCH_CONFIG" comment="'Squelch' functionality for frequency discriminator"/>
|
||||
<register addr="000032c4" rw_flags="RW" width="4" name="BT_RX_DEMOD_MLSE_CONFIG" comment="Config for and enable for the new RX BDR enhancements provided by MLSE block"/>
|
||||
<register addr="000032c8" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLSE_LR_CONFIG" comment="Config for MLSE LR"/>
|
||||
<register addr="000032cc" rw_flags="RW" width="4" name="BT_RX_DEMOD_MLSE_LR_EXP_FREQ_CONFIG" comment="Config for MLSE LR, expected FREQ"/>
|
||||
<register addr="000032d0" rw_flags="RW" width="4" name="BT_RX_DEMOD_MLSE_SYNC_CONFIG" comment="MLSE config for the FFT sync block"/>
|
||||
<register addr="000032d4" rw_flags="RW" width="1" name="BT_RX_DEMOD_MLSE_DEBUG" comment="Debug Sel"/>
|
||||
<register addr="000032d8" rw_flags="RW" width="2" name="BT_RX_SYNC_CONFIG" comment="Additional Synchroniser config"/>
|
||||
<register addr="000032dc" rw_flags="RW" width="4" name="BT_RF_ACCESS_CODE_LAP" comment="Lower address part of BT address to generate access code"/>
|
||||
<register addr="000032e0" rw_flags="RW" width="4" name="BT_RX_WBREE_ACCESS_ADDR" comment="Wibree Access Address. Sync word to seacrhg for in received packets"/>
|
||||
<register addr="000032e4" rw_flags="RW" width="2" name="BT_RX_ANT_NET_ADDR" comment="ANT Network Address for Rx Synchroniser"/>
|
||||
<register addr="000032e8" rw_flags="RW" width="2" name="BT_RX_LLR_CONFIG" comment="LLR Configuration"/>
|
||||
<register addr="000032ec" rw_flags="RW" width="4" name="BT_RF_LLR_TRIGGER_LSW" comment="LLR Access Code to transmit or receive LSW"/>
|
||||
<register addr="000032f0" rw_flags="RW" width="4" name="BT_RF_LLR_TRIGGER_MSW" comment="LLR Access Code to transmit or receive MSW"/>
|
||||
<register addr="000032f4" rw_flags="R" width="2" name="BT_RX_SYNC_NUM_ERRORS" comment="Number of bit errors in access code"/>
|
||||
<register addr="000032f8" rw_flags="R" width="2" name="BT_RX_FREQ_DISCRIM" comment="BT GFSK frequency discriminator output"/>
|
||||
<register addr="000032fc" rw_flags="R" width="2" name="BT_RX_FREQ_ERROR" comment="BT GFSK actual frequency offset output"/>
|
||||
<register addr="00003300" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_CONFIG" comment="Config for and enable for the new RX EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003304" rw_flags="RW" width="4" name="BT_RX_MR_SYNC_MLE_CONFIG" comment=""/>
|
||||
<register addr="00003308" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM00" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="0000330c" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM02" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003310" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM04" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003314" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM06" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003318" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM08" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="0000331c" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM10" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003320" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM12" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003324" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM14" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003328" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_HBASE00" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="0000332c" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_HBASE02" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003330" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_HBASE04" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003334" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_HBASE06" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003338" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_HBASE08" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="0000333c" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_HBASE10" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003340" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_HBASE12" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003344" rw_flags="RW" width="1" name="BT_RX_DEMOD_MLE_HBASE14" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003348" rw_flags="RW" width="2" name="BT_RX_MR_SYNC_CONFIG" comment="BT DPSK demodulator synchronization configuration"/>
|
||||
<register addr="0000334c" rw_flags="RW" width="2" name="BT_RX_MR_SAMP_CONFIG" comment="BT DPSK demodulator slicer configuration"/>
|
||||
<register addr="00003350" rw_flags="RW" width="4" name="BT_RX_MR_EQ_TAPS_LSW" comment="BT DPSK RRC-filter coefficients LSW"/>
|
||||
<register addr="00003354" rw_flags="RW" width="4" name="BT_RX_MR_EQ_TAPS_MSW" comment="BT DPSK RRC-filter coefficients MSW"/>
|
||||
<register addr="00003358" rw_flags="R" width="1" name="BT_RX_MR_FREQ_ERROR" comment="BT DPSK actual frequency offset output"/>
|
||||
<register addr="0000335c" rw_flags="R" width="1" name="BT_RX_MR_SYNC_SCORE" comment="BT DPSK synchronizer score output"/>
|
||||
<register addr="00003360" rw_flags="R" width="1" name="BT_DCRS_ADC_MON_STATUS" comment="ADC power detect output register: Note: BT_DCRS_ADC_MON_SINGLE_SHOT_EN should be set if this register is being used for scanning purposes."/>
|
||||
<register addr="00003364" rw_flags="RW" width="1" name="BT_DCRS_ADC_MON_CS_ENABLE" comment="Conditional scan enable (turns on just sincfir and adcproc)"/>
|
||||
<register addr="00003368" rw_flags="RW" width="1" name="BT_DCRS_CIC_CFG" comment="BT CIC decimator configuration"/>
|
||||
<register addr="0000336c" rw_flags="RW" width="1" name="BT_DCRS_ADC_MON_ENABLE" comment="Enables optional ADC domain processing"/>
|
||||
<register addr="00003370" rw_flags="RW" width="2" name="BT_DCRS_ADC_MON_CONFIG" comment="Optional ADC domain processing configuration"/>
|
||||
<register addr="00003374" rw_flags="RW" width="1" name="BT_DCRS_ADC_MON_CONFIG2" comment="Optional ADC domain processing configuration 2"/>
|
||||
<register addr="00003378" rw_flags="RW" width="1" name="BT_DCRS_ADC_MON_CS_RESET" comment="Rising edge on this signal resets ADC RMS accumulator"/>
|
||||
<register addr="0000337c" rw_flags="R" width="2" name="BT_DCRS_AGCGAIN_MON_AT_SYNC" comment="AGC gain parameters readback to determine gain settings at time of RxSync. Additional fields contain 4 bits recording whether saturation occurred after RxSync."/>
|
||||
<register addr="00003380" rw_flags="RW" width="1" name="BT_DCRS_AGC_CFG" comment="BT AGC configuration"/>
|
||||
<register addr="00003384" rw_flags="R" width="1" name="BT_DCRS_AGC_STATUS" comment="Capture some raw Ana sigs"/>
|
||||
<register addr="00003388" rw_flags="RW" width="1" name="BT_DCRS_AGC_EN_SRC" comment="Configures AGC enable criteria"/>
|
||||
<register addr="0000338c" rw_flags="RW" width="1" name="BT_DCRS_AGC_SW_LNA_GAIN" comment="Startup/SW override for LNA gain value (valid values are 0 to 6)"/>
|
||||
<register addr="00003390" rw_flags="RW" width="1" name="BT_DCRS_AGC_SW_MIX_GAIN" comment="Startup/SW override for MIX gain value (valid values are 0 to 4)"/>
|
||||
<register addr="00003394" rw_flags="RW" width="1" name="BT_DCRS_AGC_SW_BUF_GAIN" comment="Startup/SW override for BUF gain value (valid values are 0 to 3)"/>
|
||||
<register addr="00003398" rw_flags="RW" width="1" name="BT_DCRS_AGC_SW_DIG_GAIN" comment="Startup/SW override for DIG gain value - Signed 2's complement: -8 to +15 selects digital gain of -48dB to +21dB in 3dB steps"/>
|
||||
<register addr="0000339c" rw_flags="RW" width="2" name="BT_DCRS_AGC_SW_CTRL" comment="SW override enables"/>
|
||||
<register addr="000033a0" rw_flags="RW" width="4" name="BT_DCRS_AGC_GAIN_STEPS" comment="AGC LNA step values for each saturation indicator"/>
|
||||
<register addr="000033a4" rw_flags="RW" width="4" name="BT_DCRS_AGC_SATRST" comment="Configurable AGC Saturation Indicator resets"/>
|
||||
<register addr="000033a8" rw_flags="RW" width="2" name="BT_DCRS_AGC_CONF1" comment="AGC configuration register 1"/>
|
||||
<register addr="000033ac" rw_flags="RW" width="2" name="BT_DCRS_AGC_CONF2" comment="AGC configuration register 2"/>
|
||||
<register addr="000033b0" rw_flags="RW" width="2" name="BT_DCRS_AGC_CONF3" comment="AGC configuration register 3"/>
|
||||
<register addr="000033b4" rw_flags="RW" width="2" name="BT_DCRS_AGC_CONF4" comment="AGC configuration register 4"/>
|
||||
<register addr="000033b8" rw_flags="RW" width="1" name="BT_DCRS_AGC_CONF5" comment="AGC configuration register 5"/>
|
||||
<register addr="000033bc" rw_flags="RW" width="2" name="BT_DCRS_AGC_EQ_PWR_THR" comment="(Post digital gain) power threshold register for digital gain control"/>
|
||||
<register addr="000033c0" rw_flags="RW" width="2" name="BT_DCRS_AGC_BB_PWR_HI_THR" comment="(Pre digital gain) power threshold register for analog gain control"/>
|
||||
<register addr="000033c4" rw_flags="RW" width="2" name="BT_DCRS_AGC_BB_PWR_DET_THR" comment="(Post digital gain) power threshold register for power detection"/>
|
||||
<register addr="000033c8" rw_flags="RW" width="1" name="BT_DCRS_AGC_FAST_DIG_CTRL_CFG" comment="(Pre digital gain) power threshold register for fast digital control of the analogue gains"/>
|
||||
<register addr="000033cc" rw_flags="R" width="2" name="BT_DCRS_AGCGAIN_MON" comment="AGC gain parameters readback"/>
|
||||
<register addr="000033d0" rw_flags="R" width="2" name="BT_DCRS_SAT_MON" comment="Monitor raw saturation detectorors"/>
|
||||
<register addr="000033d4" rw_flags="RW" width="4" name="BT_DCRS_BB_EQ_CFG0" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033d8" rw_flags="RW" width="4" name="BT_DCRS_BB_EQ_CFG1" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033dc" rw_flags="RW" width="4" name="BT_DCRS_BB_EQ_CFG2" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033e0" rw_flags="RW" width="4" name="BT_DCRS_BB_EQ_CFG3" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033e4" rw_flags="RW" width="4" name="BT_DCRS_BB_EQ_CFG4" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033e8" rw_flags="RW" width="4" name="BT_DCRS_BB_EQ_CFG5" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033ec" rw_flags="RW" width="4" name="BT_DCRS_BB_EQ_CFG6" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033f0" rw_flags="RW" width="2" name="BT_DCRS_BB_EQ_CFG7" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033f4" rw_flags="RW" width="1" name="BT_DCRS_EQ_CONFIG" comment="BT baseband equalizer configuration"/>
|
||||
<register addr="000033f8" rw_flags="RW" width="1" name="BT_DCRS_DBG_CFG" comment="BT debug mux configuration"/>
|
||||
<register addr="000033fc" rw_flags="RW" width="1" name="BT_DCRS_DBG_SEL" comment=""/>
|
||||
<register addr="00003400" rw_flags="RW" width="2" name="BT_DCRS_IF_EQ_CFG" comment="BT IF equalizer filter coefficients"/>
|
||||
<register addr="00003404" rw_flags="RW" width="1" name="BT_DCRS_IIR_CONFIG" comment="IIR decimation configuration"/>
|
||||
<register addr="00003408" rw_flags="RW" width="2" name="BT_DCRS_NBIIR_FILTER_CFG" comment="SDDCRS NarrowBand IIR filter configuration"/>
|
||||
<register addr="0000340c" rw_flags="RW" width="4" name="BT_DCRS_NBIIR_COEFF1_LSW" comment="SDDCRS NarrowBand IIR filter coefficients (Biquad 1) LSW"/>
|
||||
<register addr="00003410" rw_flags="RW" width="1" name="BT_DCRS_NBIIR_COEFF1_MSB" comment="SDDCRS NarrowBand IIR filter coefficients (Biquad 1) MSB"/>
|
||||
<register addr="00003414" rw_flags="RW" width="4" name="BT_DCRS_NBIIR_COEFF2_LSW" comment="SDDCRS NarrowBand IIR filter coefficients (Biquad 2) LSW"/>
|
||||
<register addr="00003418" rw_flags="RW" width="1" name="BT_DCRS_NBIIR_COEFF2_MSB" comment="SDDCRS NarrowBand IIR filter coefficients (Biquad 2) MSB"/>
|
||||
<register addr="0000341c" rw_flags="RW" width="4" name="BT_DCRS_TINC_CFG" comment="BT resampling ratio configuration - Must be calculated as round((1 - 16*(BT_DCRS_CIC_DEC+1)/fAdc_MHz) * 2^26) - Use floor instead of round if BT_DCRS_PHASE_LOCK is set"/>
|
||||
<register addr="00003420" rw_flags="RW" width="1" name="BT_DCRS_LINT_CFG" comment="BT linear interpolator configuration"/>
|
||||
<register addr="00003424" rw_flags="RW" width="4" name="BT_DCRS_PHASECOMP_SHIFTS_LNA0" comment=""/>
|
||||
<register addr="00003428" rw_flags="RW" width="2" name="BT_DCRS_PHASECOMP_SHIFTS_LNA1" comment=""/>
|
||||
<register addr="0000342c" rw_flags="RW" width="4" name="BT_DCRS_PHASECOMP_SHIFTS_BUF" comment=""/>
|
||||
<register addr="00003430" rw_flags="RW" width="4" name="BT_DCRS_PHASECOMP_SHIFTS_MIX0" comment=""/>
|
||||
<register addr="00003434" rw_flags="RW" width="1" name="BT_DCRS_PHASECOMP_SHIFTS_MIX1" comment=""/>
|
||||
<register addr="00003438" rw_flags="RW" width="4" name="BT_DCRS_PHASECOMP_DELAYS" comment="Phase compensator delay values"/>
|
||||
<register addr="0000343c" rw_flags="RW" width="2" name="BT_DCRS_NOM_IF_BT_CFG" comment="BT nominal IF"/>
|
||||
<register addr="00003440" rw_flags="R" width="2" name="BT_DCRS_FREQ_OFFSET_STATUS" comment=""/>
|
||||
<register addr="00003444" rw_flags="R" width="4" name="BT_DCRS_BB_PWR_STATUS" comment="Measured baseband power (pre-digital gain)"/>
|
||||
<register addr="00003448" rw_flags="R" width="2" name="BT_DCRS_EQ_PWR_STATUS_AT_SYNC" comment="This is not exactly EqPwr registered at Sync. It is the post-digital gain signal power averaged over the longer period of time used for BbPwr. In order to measure this, we use BbPwr and compensate for the digital gain at Sync. This results in a stabilised RSSI value after digital gain. It also produces a 16-bit result which the XAP can more easily manage than the raw BBPwrAtSync (32 bit)Measured baseband power (post-digital gain) obtained at RxSync, averaged over the longer period of time used for pre-digital gain measurements."/>
|
||||
<register addr="0000344c" rw_flags="R" width="2" name="BT_DCRS_EQ_PWR_STATUS" comment="Raw EqPwr"/>
|
||||
<register addr="00003450" rw_flags="RW" width="2" name="BT_DCRS_AGC_PWR_MEAS" comment="AGC power measure configuration"/>
|
||||
<register addr="00003454" rw_flags="RW" width="2" name="BT_DCRS_SYNCPHASE_CONFIG" comment="Configures phase of clock synchronization buffer"/>
|
||||
<register addr="00003458" rw_flags="R" width="1" name="BT_DCRS_STATUS" comment="Contains the status from the Dcrs block "/>
|
||||
<register addr="0000345c" rw_flags="R" width="2" name="BT_ANA_STATUS" comment="Miscellaneous readable analogue bits"/>
|
||||
<register addr="00003460" rw_flags="R" width="4" name="BT_ANA_LO_DPLL_TEST_STATUS" comment="This register contains test outputs from the LO"/>
|
||||
<register addr="00003464" rw_flags="RW" width="4" name="BT_ANA_MISC" comment=""/>
|
||||
<register addr="00003468" rw_flags="RW" width="4" name="BT_ANA_STATIC_SPARE" comment="Static spare bits for analogue. Descriptions will be updated based on analogue usage."/>
|
||||
<register addr="0000346c" rw_flags="RW" width="4" name="BT_ANA_RXRF" comment=""/>
|
||||
<register addr="00003470" rw_flags="RW" width="4" name="BT_ANA_RXADC" comment=""/>
|
||||
<register addr="00003474" rw_flags="RW" width="4" name="BT_ANA_TXBB_0" comment=""/>
|
||||
<register addr="00003478" rw_flags="RW" width="2" name="BT_ANA_TXBB_1" comment=""/>
|
||||
<register addr="0000347c" rw_flags="RW" width="4" name="BT_ANA_TXRF_0" comment=""/>
|
||||
<register addr="00003480" rw_flags="RW" width="4" name="BT_ANA_TXRF_1" comment=""/>
|
||||
<register addr="00003484" rw_flags="RW" width="2" name="BT_ANA_TXRF_2" comment=""/>
|
||||
<register addr="00003488" rw_flags="RW" width="4" name="BT_ANA_LO_CLKREF_ADC" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="0000348c" rw_flags="RW" width="4" name="BT_ANA_LO_DCO_CONF1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="00003490" rw_flags="RW" width="4" name="BT_ANA_LO_DCO_CONF2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="00003494" rw_flags="RW" width="4" name="BT_ANA_LO_DCO_OPEN1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="00003498" rw_flags="RW" width="4" name="BT_ANA_LO_DCO_OPEN2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="0000349c" rw_flags="RW" width="4" name="BT_ANA_LO_DCO_TEST" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034a0" rw_flags="RW" width="4" name="BT_ANA_LO_DPLL_CONF1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034a4" rw_flags="RW" width="4" name="BT_ANA_LO_DPLL_CONF2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034a8" rw_flags="RW" width="4" name="BT_ANA_LO_DPLL_TEST" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034ac" rw_flags="RW" width="4" name="BT_ANA_LO_D_FREQ1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034b0" rw_flags="RW" width="4" name="BT_ANA_LO_D_FREQ2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034b4" rw_flags="RW" width="4" name="BT_ANA_LO_TEST" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034b8" rw_flags="RW" width="4" name="BT_ANA_LO_PLL_RESV" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034bc" rw_flags="RW" width="4" name="BT_ANA_LO_PU_DCO_CONF" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034c0" rw_flags="RW" width="4" name="BT_ANA_LO_PU_TDC_CONF" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034c4" rw_flags="RW" width="4" name="BT_ANA_LO_AREG_CONF" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034c8" rw_flags="RW" width="4" name="BT_ANA_LO_TDC_NLMEM" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034cc" rw_flags="RW" width="4" name="BT_ANA_LO_TOP" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034d0" rw_flags="RW" width="1" name="BT_ANA_DEBUG_SEL" comment=""/>
|
||||
<register addr="000034d4" rw_flags="RW" width="2" name="BT_ANAIF_CFG" comment="ADC Digital saturation filter control"/>
|
||||
<register addr="000034d8" rw_flags="RW" width="1" name="BT_ANA_LO_SW_STOP" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034dc" rw_flags="RW" width="4" name="BT_ANA_SW_ENABLES" comment="Override value for timer outputs when not controlled by timer"/>
|
||||
<register addr="000034e0" rw_flags="RW" width="4" name="BT_ANA_SW_ENABLES_MASK" comment="Selects whether timer outputs or override bits are used for analogue"/>
|
||||
<register addr="000034e4" rw_flags="R" width="4" name="BT_ANA_ENABLES_STATUS" comment="Shows values being driven to analogue interface after timer and masking function is resolved"/>
|
||||
<register addr="000034e8" rw_flags="RW" width="4" name="BT_ANA_LNA_ZIN_TRIM_LUT" comment="First 4 locations of LUT used to generate the 2G5 LNA ZinTrim value."/>
|
||||
</block>
|
||||
<block name="btwl_common" comment="">
|
||||
<register addr="00002000" rw_flags="RW" width="1" name="COEX_RF_DEBUG_SEL" comment="Coexistence RFIC debug mux select."/>
|
||||
<register addr="00002004" rw_flags="RW" width="1" name="COEX_RF_CFG" comment="Coexistence RFIC configuration."/>
|
||||
<register addr="00002008" rw_flags="RW" width="1" name="COEX_RF_SW_RESET" comment="Software reset of Coexistence RFIC digital."/>
|
||||
<register addr="0000200c" rw_flags="RW" width="4" name="COEX_RF_ARB_CFG" comment=""/>
|
||||
<register addr="00002010" rw_flags="RW" width="4" name="COEX_RF_TRAN_CTRL_CFG" comment="Coexistence Transition Control configuration."/>
|
||||
<register addr="00002014" rw_flags="RW" width="4" name="COEX_RF_SH_STATIC_CTRL0" comment=""/>
|
||||
<register addr="00002018" rw_flags="RW" width="4" name="COEX_RF_SH_STATIC_CTRL1" comment=""/>
|
||||
<register addr="0000201c" rw_flags="RW" width="4" name="COEX_RF_LO_LDOREG_CFG1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="00002020" rw_flags="RW" width="2" name="COEX_RF_SHRX_CFG" comment=""/>
|
||||
<register addr="00002024" rw_flags="RW" width="1" name="COEX_RF_SHTX_CFG" comment="Coexistence Shared Tx Mux configuration."/>
|
||||
<register addr="00002028" rw_flags="RW" width="1" name="COEX_RF_FEC_IDLE_2G_CFG" comment="RF Switch configuration to use when both WLAN/BT radios are idle at 2G."/>
|
||||
<register addr="0000202c" rw_flags="RW" width="1" name="COEX_RF_FEC_SH_2G_RX_CFG" comment="RF Switch configuration to use when WLAN/BT are simultaneously receiving at 2G."/>
|
||||
<register addr="00002030" rw_flags="RW" width="1" name="COEX_RF_FEC_WL_2G_TX_CFG" comment="RF Switch configuration to use when WLAN is transmitting at 2G."/>
|
||||
<register addr="00002034" rw_flags="RW" width="1" name="COEX_RF_FEC_BT_TX_CFG" comment="RF Switch configuration to use when BT is transmitting."/>
|
||||
<register addr="00002038" rw_flags="RW" width="1" name="COEX_RF_FEC_WL_2G_DCOC_CFG" comment="RF Switch configuration to use during WLAN 2G DCOC."/>
|
||||
<register addr="0000203c" rw_flags="RW" width="1" name="COEX_RF_FEC_WL_2G_DPD_CFG" comment="RF Switch configuration to use during WLAN 2G DPD training."/>
|
||||
<register addr="00002040" rw_flags="RW" width="1" name="COEX_RF_FEC_IDLE_5G_CFG" comment="RF Switch configuration to use when WLAN is idle at 5G (or operating in 2G band)."/>
|
||||
<register addr="00002044" rw_flags="RW" width="1" name="COEX_RF_FEC_WL_5G_TX_CFG" comment="RF Switch configuration to use when WLAN is transmitting at 5G."/>
|
||||
<register addr="00002048" rw_flags="RW" width="1" name="COEX_RF_FEC_WL_5G_RX_CFG" comment="RF Switch configuration to use when WLAN is receiving at 5G."/>
|
||||
<register addr="0000204c" rw_flags="RW" width="1" name="COEX_RF_FEC_WL_5G_DCOC_CFG" comment="RF Switch configuration to use during WLAN 5G DCOC."/>
|
||||
<register addr="00002050" rw_flags="RW" width="1" name="COEX_RF_FEC_WL_5G_DPD_CFG" comment="RF Switch configuration to use during WLAN 5G DPD training."/>
|
||||
<register addr="00002054" rw_flags="RW" width="4" name="COEX_RF_PROT_CHANGE_MODE" comment="Set this to 0xDEADBEEF in order to change the analogue protection. Should clear back to 0 after changing mode."/>
|
||||
<register addr="00002058" rw_flags="RW" width="1" name="COEX_RF_PROT_CFG" comment="Analogue protection configuration register."/>
|
||||
<register addr="0000205c" rw_flags="RW" width="2" name="AUX_BIST_ADC_CTRL" comment="Control register for auxiliary ADC"/>
|
||||
<register addr="00002060" rw_flags="RW" width="2" name="AUX_BIST_ADC_LEVEL" comment="DAC value driven to auxiliary ADC"/>
|
||||
<register addr="00002064" rw_flags="R" width="2" name="AUX_BIST_ADC_STATUS" comment="Returns the data from auxiliary ADC"/>
|
||||
<register addr="00002068" rw_flags="RW" width="2" name="BTWL_BIST_ADC_CTRL" comment="Control register for auxiliary ADC"/>
|
||||
<register addr="0000206c" rw_flags="RW" width="2" name="BTWL_BIST_ADC_LEVEL" comment="DAC value driven to auxiliary ADC"/>
|
||||
<register addr="00002070" rw_flags="R" width="2" name="BTWL_BIST_ADC_STATUS" comment="Returns the data from auxiliary ADC"/>
|
||||
<register addr="00002074" rw_flags="RW" width="4" name="RFIC_DEBUG_CFG" comment="BTWL Debug Config"/>
|
||||
<register addr="00002078" rw_flags="RW" width="4" name="RFIC_DEBUG_CFG2" comment="BTWL Debug Config register 2"/>
|
||||
<register addr="0000207c" rw_flags="RW" width="4" name="RFIC_DEBUG_CFG3" comment="BTWL Debug Config register 3"/>
|
||||
<register addr="00002080" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_DBG0" comment="Debug Mux for pin"/>
|
||||
<register addr="00002084" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_DBG1" comment="Debug Mux for pin"/>
|
||||
<register addr="00002088" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_DBG2" comment="Debug Mux for pin"/>
|
||||
<register addr="0000208c" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_DBG3" comment="Debug Mux for pin"/>
|
||||
<register addr="00002090" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_WL_SPDY_M" comment="Debug Mux for pin"/>
|
||||
<register addr="00002094" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_WL_SPDY_S" comment="Debug Mux for pin"/>
|
||||
<register addr="00002098" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_BT_SPDY_M" comment="Debug Mux for pin"/>
|
||||
<register addr="0000209c" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_BT_SPDY_S" comment="Debug Mux for pin"/>
|
||||
<register addr="000020a0" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_FM_SPDY_S" comment="Debug Mux for pin"/>
|
||||
<register addr="000020a4" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_FEM0" comment="Debug Mux for pin"/>
|
||||
<register addr="000020a8" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_FEM1" comment="Debug Mux for pin"/>
|
||||
<register addr="000020ac" rw_flags="RW" width="4" name="RFIC_DEBUG_MUX_SERIAL_BT" comment="Serialiser control for BT Debug bus"/>
|
||||
<register addr="000020b0" rw_flags="RW" width="4" name="RFIC_DEBUG_MUX_SERIAL_WL" comment="Serialiser control for WLan Debug bus"/>
|
||||
<register addr="000020b4" rw_flags="RW" width="4" name="RFIC_DEBUG_MUX_SERIAL_COEX" comment="Serialiser control for Coex Debug bus"/>
|
||||
<register addr="000020b8" rw_flags="RW" width="4" name="RFIC_DEBUG_MUX_SERIAL_MISC" comment="Serialiser control for Misc Debug bus"/>
|
||||
<register addr="000020bc" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_SERIAL_DATA" comment="Not used"/>
|
||||
<register addr="000020c0" rw_flags="R" width="2" name="RFIC_DEBUG_PAD_SDR_STATUS" comment="Debug Pad Inputs"/>
|
||||
<register addr="000020c4" rw_flags="R" width="2" name="RFIC_DEBUG_PAD_DDR_STATUS" comment="Debug Pad DDR Inputs"/>
|
||||
<register addr="000020c8" rw_flags="RW" width="1" name="RFIC_DEBUG_ACC_ADDR" comment="Debug Acc Addr"/>
|
||||
<register addr="000020cc" rw_flags="RW" width="4" name="RFIC_DEBUG_ACC_WDATA" comment="Debug Acc Write Data"/>
|
||||
<register addr="000020d0" rw_flags="R" width="4" name="RFIC_DEBUG_ACC_RDATA" comment="Debug Acc Read Data"/>
|
||||
<register addr="000020d4" rw_flags="R" width="2" name="RFIC_DEBUG_STATUS" comment="Main Debug Status register"/>
|
||||
<register addr="000020d8" rw_flags="RW" width="2" name="RFIC_DEBUG_WL_SPEEDY_S_MON_CTRL" comment="WL Speedy Slave Monitor Ctrl"/>
|
||||
<register addr="000020dc" rw_flags="RW" width="4" name="RFIC_DEBUG_WL_SPEEDY_M_MON_CTRL" comment="WL Speedy Master Monitor Ctrl"/>
|
||||
<register addr="000020e0" rw_flags="R" width="4" name="RFIC_DEBUG_WL_SPEEDY_MON_STATUS" comment="WL Speedy Monitor Status"/>
|
||||
<register addr="000020e4" rw_flags="RW" width="2" name="RFIC_DEBUG_BT_SPEEDY_S_MON_CTRL" comment="BT Speedy Slave Monitor Ctrl"/>
|
||||
<register addr="000020e8" rw_flags="RW" width="4" name="RFIC_DEBUG_BT_SPEEDY_M_MON_CTRL" comment="BT Speedy Master Monitor Ctrl"/>
|
||||
<register addr="000020ec" rw_flags="R" width="4" name="RFIC_DEBUG_BT_SPEEDY_MON_STATUS" comment="BT Speedy Monitor Status"/>
|
||||
<register addr="000020f0" rw_flags="RW" width="2" name="RFIC_DEBUG_ACC_TIMER" comment="Timer"/>
|
||||
<register addr="000020f4" rw_flags="R" width="4" name="RFIC_DEBUG_ACC_STATUS" comment="Status information for Debug Acc"/>
|
||||
<register addr="000020f8" rw_flags="RW" width="4" name="RFIC_MON_BT_DA_INV0" comment="Optional invert for each BT DA dynamic signal, excluding Dynamic Enables from timers"/>
|
||||
<register addr="000020fc" rw_flags="RW" width="4" name="RFIC_MON_WL_DA_INV0" comment="Optional invert for each WL DA dynamic signal, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002100" rw_flags="RW" width="4" name="RFIC_MON_WL_DA_INV1" comment="Optional invert for each WL DA dynamic signal, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002104" rw_flags="RW" width="4" name="RFIC_MON_WL_DA_INV2" comment="Optional invert for each WL DA dynamic signal, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002108" rw_flags="RW" width="4" name="RFIC_MON_COEX_DA_INV0" comment="Optional invert for each SH DA dynamic signal, excluding Dynamic Enables from timers"/>
|
||||
<register addr="0000210c" rw_flags="RW" width="4" name="RFIC_MON_COEX_DA_INV1" comment="Optional invert for each SH DA dynamic signal, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002110" rw_flags="RW" width="4" name="RFIC_MON_BT_DA_OFF0" comment="Set to turn off drive of each BT DA dynamic signal from core, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002114" rw_flags="RW" width="4" name="RFIC_MON_WL_DA_OFF0" comment="Set to turn off drive of each WL DA dynamic signal from core, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002118" rw_flags="RW" width="4" name="RFIC_MON_WL_DA_OFF1" comment="Set to turn off drive of each WL DA dynamic signal from core, excluding Dynamic Enables from timers"/>
|
||||
<register addr="0000211c" rw_flags="RW" width="4" name="RFIC_MON_WL_DA_OFF2" comment="Set to turn off drive of each WL DA dynamic signal from core, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002120" rw_flags="RW" width="4" name="RFIC_MON_COEX_DA_OFF0" comment="Set to turn off drive of each SH DA dynamic signal from core, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002124" rw_flags="RW" width="4" name="RFIC_MON_COEX_DA_OFF1" comment="Set to turn off drive of each SH DA dynamic signal from core, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002128" rw_flags="R" width="4" name="RFIC_MON_BT_AD0" comment="Monitor BT AD signals right at the AD interface"/>
|
||||
<register addr="0000212c" rw_flags="R" width="4" name="RFIC_MON_WL_AD0" comment="Monitor WL AD signals right at the AD interface"/>
|
||||
<register addr="00002130" rw_flags="R" width="4" name="RFIC_MON_WL_AD1" comment="Monitor WL AD signals right at the AD interface"/>
|
||||
<register addr="00002134" rw_flags="R" width="4" name="RFIC_MON_WL_AD2" comment="Monitor WL AD signals right at the AD interface"/>
|
||||
<register addr="00002138" rw_flags="R" width="4" name="RFIC_MON_COEX_AD0" comment="Monitor SH AD signals right at the AD interface"/>
|
||||
<register addr="0000213c" rw_flags="R" width="4" name="RFIC_MON_RS_ACC_BUF" comment="Rs Accumulation Buffer register"/>
|
||||
<register addr="00002140" rw_flags="R" width="2" name="RFIC_MON_RS_ACC_BUF2" comment="Rs Accumulation Buffer register2"/>
|
||||
</block>
|
||||
<block name="rfic_pad_control" comment="">
|
||||
<register addr="00001000" rw_flags="RW" width="1" name="PAD_CONTROL_FEM_CTRL0" comment="Control register for pad FEM_CTRL0"/>
|
||||
<register addr="00001004" rw_flags="RW" width="1" name="PAD_CONTROL_FEM_CTRL1" comment="Control register for pad FEM_CTRL1"/>
|
||||
<register addr="00001008" rw_flags="RW" width="1" name="PAD_CONTROL_FM_SPDY_S" comment="Control register for pad FM_SPDY_S"/>
|
||||
<register addr="0000100c" rw_flags="RW" width="1" name="PAD_CONTROL_BT_SPDY_M" comment="Control register for pad BT_SPDY_M"/>
|
||||
<register addr="00001010" rw_flags="RW" width="1" name="PAD_CONTROL_WL_SPDY_S" comment="Control register for pad WL_SPDY_S"/>
|
||||
<register addr="00001014" rw_flags="RW" width="1" name="PAD_CONTROL_BT_SPDY_S" comment="Control register for pad BT_SPDY_S"/>
|
||||
<register addr="00001018" rw_flags="RW" width="1" name="PAD_CONTROL_WL_SPDY_M" comment="Control register for pad WL_SPDY_M"/>
|
||||
</block>
|
||||
<block name="wlrf_radio" comment="">
|
||||
<register addr="00004000" rw_flags="RW" width="1" name="WLRF_RADIO_LNA_RSSI_THRESH_EXT_LOUD" comment="This register specifies the threshold value for the LNA RSSI module, turning off external LNA indication"/>
|
||||
<register addr="00004004" rw_flags="RW" width="1" name="WLRF_RADIO_LNA_RSSI_THRESH_LOUD" comment="This register specifies the threshold value for the LNA RSSI module, too loud indication (- 6dB gain change request)"/>
|
||||
<register addr="00004008" rw_flags="RW" width="1" name="WLRF_RADIO_LNA_RSSI_THRESH_V_LOUD" comment="This register specifies the threshold value for the LNA RSSI module, extra loud indication (-12dB gain change request)"/>
|
||||
<register addr="0000400c" rw_flags="RW" width="2" name="WLRF_RADIO_MIX_RSSI_THRESH_WEAK" comment="This register specifies the threshold value for the Mixer RSSI module, too weak indication (+ 6dB gain change request)"/>
|
||||
<register addr="00004010" rw_flags="RW" width="2" name="WLRF_RADIO_MIX_RSSI_THRESH_LOUD" comment="This register specifies the threshold value for the Mixer RSSI module, too loud indication (- 6dB gain change request)"/>
|
||||
<register addr="00004014" rw_flags="RW" width="2" name="WLRF_RADIO_MIX_RSSI_THRESH_V_LOUD" comment="This register specifies the threshold value for the Mixer RSSI module, extra loud indication (-12dB gain change request)"/>
|
||||
<register addr="00004018" rw_flags="RW" width="2" name="WLRF_RADIO_ABB_RSSI_THRESH_WEAK" comment="This register specifies the threshold value for the ABB RSSI module, too weak indication (+ 1.5dB gain change request)"/>
|
||||
<register addr="0000401c" rw_flags="RW" width="2" name="WLRF_RADIO_ABB_RSSI_THRESH_LOUD" comment="This register specifies the threshold value for the ABB RSSI module, too loud indication (- 6dB gain change request)"/>
|
||||
<register addr="00004020" rw_flags="RW" width="2" name="WLRF_RADIO_ABB_RSSI_THRESH_V_LOUD" comment="This register specifies the threshold value for the ABB RSSI module, extra loud indication (-12dB gain change request)"/>
|
||||
<register addr="00004024" rw_flags="R" width="2" name="WLRF_RADIO_RX_RSSI" comment="This register contains the RSSI of the receive chain. The lower byte is the 8 bit digital RSSI (fixed to 0 since this is a radio-only chip) and the upper byte is the final analogue gain in 3dB steps."/>
|
||||
<register addr="00004028" rw_flags="R" width="1" name="WLRF_RSSI_FILTERED_STATUS" comment="This register contains the analogue RSSI values for the receive chain, after initial processing in the rssi blocks block."/>
|
||||
<register addr="0000402c" rw_flags="RW" width="4" name="WLRF_WB_RSSI_LUT0" comment="First 6 locations of LUT used to generate RSSI values for WB RSSI. Note that fields are 5 bits but only LS 4 bits are used"/>
|
||||
<register addr="00004030" rw_flags="RW" width="4" name="WLRF_WB_RSSI_LUT1" comment="Last 6 locations of LUT used to generate RSSI values for WB RSSI. Note that fields are 5 bits but only LS 4 bits are used"/>
|
||||
<register addr="00004034" rw_flags="RW" width="4" name="WLRF_IB_RSSI_LUT0" comment="First 6 locations of LUT used to generate RSSI values for IB RSSI"/>
|
||||
<register addr="00004038" rw_flags="RW" width="4" name="WLRF_IB_RSSI_LUT1" comment="Last 6 locations of LUT used to generate RSSI values for IB RSSI"/>
|
||||
<register addr="0000403c" rw_flags="RW" width="4" name="WLRF_ABB_RSSI_LUT0" comment="First 6 locations of LUT used to generate RSSI values for ABB RSSI"/>
|
||||
<register addr="00004040" rw_flags="RW" width="4" name="WLRF_ABB_RSSI_LUT1" comment="Last 6 locations of LUT used to generate RSSI values for ABB RSSI"/>
|
||||
<register addr="00004044" rw_flags="RW" width="4" name="WLRF_RADIO_AGC_CONFIG1" comment="Miscellaneous config bits for the AGC as follows:"/>
|
||||
<register addr="00004048" rw_flags="RW" width="4" name="WLRF_RADIO_AGC_CONFIG2" comment="Configuration bits for the AGC: gains ranges definition. valid when AGC is active, and gain not forced."/>
|
||||
<register addr="0000404c" rw_flags="RW" width="2" name="WLRF_RADIO_RX_LEVEL" comment="This register contains the value to be sent to the analogue gain stages if the AGC is disabled."/>
|
||||
<register addr="00004050" rw_flags="R" width="2" name="WLRF_RADIO_GAIN_STATUS" comment="This register contains the current gain settings to all blocks in the analogue front end"/>
|
||||
<register addr="00004054" rw_flags="RW" width="4" name="WLRF_ANA_LNA_TRIM_LUT" comment="This register defines the LUT used to generate ZIN_TRIM values for 2G5 LNAs"/>
|
||||
<register addr="00004058" rw_flags="RW" width="1" name="WLRF_DEBUG_SELECT" comment="Selects which debug appears on the output of the WLAN block"/>
|
||||
<register addr="0000405c" rw_flags="R" width="2" name="WLRF_DEBUG_STATUS" comment="Returns the current value on the debug bus"/>
|
||||
<register addr="00004060" rw_flags="RW" width="1" name="WLRF_RADIO_CONFIG" comment="Miscellaneous config bits"/>
|
||||
<register addr="00004064" rw_flags="RW" width="4" name="WLRF_RADIO_TEMP_CTRL_CONFIG" comment="Control register for block interfacing to analogue temperature sensor"/>
|
||||
<register addr="00004068" rw_flags="RW" width="2" name="WLRF_ANA_INT_CFG" comment="Configure source for WL status interrupts"/>
|
||||
<register addr="0000406c" rw_flags="R" width="1" name="WLRF_ANA_INT_STATUS" comment="WL Status Interrupt status"/>
|
||||
<register addr="00004070" rw_flags="R" width="4" name="WLRF_ANA_RAW_INT_STATUS" comment="Raw status from the analogue module - intended for hardware debug"/>
|
||||
<register addr="00004074" rw_flags="R" width="2" name="WLRF_RADIO_TEMP" comment="Radio temperature, as measured by analogue sensors near PA"/>
|
||||
<register addr="00004078" rw_flags="R" width="4" name="WLRF_ANA_STATUS" comment="Returns the value on the ANA_STATUS bus"/>
|
||||
<register addr="0000407c" rw_flags="R" width="4" name="WLRF_ANA_RSSI_STATUS" comment="This register contains the raw analogue RSSI values for the receive chain"/>
|
||||
<register addr="00004080" rw_flags="R" width="4" name="WLRF_ANA_ENABLES_STATUS" comment="This register contains the current values of the Analogue Enables, after all masking and multiplexing."/>
|
||||
<register addr="00004084" rw_flags="RW" width="4" name="WLRF_ANA_ENABLES" comment="Default values for analogue enables signals should the mask register select this rather than the timer outputs"/>
|
||||
<register addr="00004088" rw_flags="RW" width="4" name="WLRF_ANA_ENABLES_MASK" comment="Selects use of ANA_ENABLES or timer outputs. A 1 in a given bit selects the timer output."/>
|
||||
<register addr="0000408c" rw_flags="RW" width="4" name="WLRF_ANA_TRAINING_ENABLES_MASK" comment="This masks the output of the Tx timer when it is not a DPD training frame. The idea is to be able to remove the extra Rx enables that are required for making DPD training work to improve power consumption on frames that don't need them. It should typically have all the Tx bits set and none of the Rx bits."/>
|
||||
<register addr="00004090" rw_flags="R" width="1" name="WLRF_ANA_TIMER_TX_SLOT" comment="This register contains the current slot selected by the Tx timer"/>
|
||||
<register addr="00004094" rw_flags="R" width="1" name="WLRF_ANA_TIMER_RX_SLOT" comment="This register contains the current slot selected by the Rx timer"/>
|
||||
<register addr="00004098" rw_flags="RW" width="4" name="WLRF_ANA_TRIM_TX" comment="This register sets the modulation dependent analogue trims in low power mode and when Ana Tx Test Mode is selected (in WLRF_RADIO_CONFIG register)"/>
|
||||
<register addr="0000409c" rw_flags="RW" width="4" name="WLRF_ANA_TX_CCK_TRIM_CONF" comment="CCK modulation dependent analogue trims"/>
|
||||
<register addr="000040a0" rw_flags="RW" width="4" name="WLRF_ANA_TX_OFDM0_TRIM_CONF" comment="OFDM modulation dependent analogue trims when corresponding bit in WL_RADIO_TX_CTRL_ANA_OFDM_SEL is set to 0"/>
|
||||
<register addr="000040a4" rw_flags="RW" width="4" name="WLRF_ANA_TX_OFDM1_TRIM_CONF" comment="OFDM modulation dependent analogue trims when corresponding bit in WL_RADIO_TX_CTRL_ANA_OFDM_SEL is set to 1"/>
|
||||
<register addr="000040a8" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT0_ENABLES" comment="This register sets the radio enables for transmit timer slot 0."/>
|
||||
<register addr="000040ac" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT1_ENABLES" comment="This register sets the radio enables for transmit timer slot 1."/>
|
||||
<register addr="000040b0" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT2_ENABLES" comment="This register sets the radio enables for transmit timer slot 2."/>
|
||||
<register addr="000040b4" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT3_ENABLES" comment="This register sets the radio enables for transmit timer slot 3."/>
|
||||
<register addr="000040b8" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT4_ENABLES" comment="This register sets the radio enables for transmit timer slot 4."/>
|
||||
<register addr="000040bc" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT5_ENABLES" comment="This register sets the radio enables for transmit timer slot 5."/>
|
||||
<register addr="000040c0" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT6_ENABLES" comment="This register sets the radio enables for transmit timer slot 6."/>
|
||||
<register addr="000040c4" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT7_ENABLES" comment="This register sets the radio enables for transmit timer slot 7."/>
|
||||
<register addr="000040c8" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT0_DELAY" comment="This register sets the delay from Tx timer enable to slot 0 becoming active in 50ns units"/>
|
||||
<register addr="000040cc" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT1_DELAY" comment="This register sets the delay from Tx timer enable to slot 1 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="000040d0" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT2_DELAY" comment="This register sets the delay from Tx timer enable to slot 2 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="000040d4" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT3_DELAY" comment="This register sets the delay from Tx timer enable to slot 3 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="000040d8" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT4_DELAY" comment="This register sets the delay from Tx timer enable to slot 4 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="000040dc" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT5_DELAY" comment="This register sets the delay from Tx timer enable to slot 5 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="000040e0" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT6_DELAY" comment="This register sets the delay from Tx timer enable to slot 6 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="000040e4" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT7_DELAY" comment="This register sets the delay from Tx timer enable to slot 7 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="000040e8" rw_flags="RW" width="2" name="WLRF_ANA_TIMER_TX_SLOT_ON_OFF_LAST" comment="This register sets the start and end of Tx turn on and off ramps, and the slot jumped to in the case of a Tx abort"/>
|
||||
<register addr="000040ec" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT0_ENABLES" comment="This register sets the radio enables for receive timer slot 0."/>
|
||||
<register addr="000040f0" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT1_ENABLES" comment="This register sets the radio enables for receive timer slot 1."/>
|
||||
<register addr="000040f4" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT2_ENABLES" comment="This register sets the radio enables for receive timer slot 2."/>
|
||||
<register addr="000040f8" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT3_ENABLES" comment="This register sets the radio enables for receive timer slot 3."/>
|
||||
<register addr="000040fc" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT4_ENABLES" comment="This register sets the radio enables for receive timer slot 4."/>
|
||||
<register addr="00004100" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT5_ENABLES" comment="This register sets the radio enables for receive timer slot 5."/>
|
||||
<register addr="00004104" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT6_ENABLES" comment="This register sets the radio enables for receive timer slot 6."/>
|
||||
<register addr="00004108" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT7_ENABLES" comment="This register sets the radio enables for receive timer slot 7."/>
|
||||
<register addr="0000410c" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT0_DELAY" comment="This register sets the delay from Rx timer enable to slot 0 becoming active in 50ns units"/>
|
||||
<register addr="00004110" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT1_DELAY" comment="This register sets the delay from Rx timer enable to slot 1 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="00004114" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT2_DELAY" comment="This register sets the delay from Rx timer enable to slot 2 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="00004118" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT3_DELAY" comment="This register sets the delay from Rx timer enable to slot 3 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="0000411c" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT4_DELAY" comment="This register sets the delay from Rx timer enable to slot 4 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="00004120" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT5_DELAY" comment="This register sets the delay from Rx timer enable to slot 5 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="00004124" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT6_DELAY" comment="This register sets the delay from Rx timer enable to slot 6 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="00004128" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT7_DELAY" comment="This register sets the delay from Rx timer enable to slot 7 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="0000412c" rw_flags="RW" width="2" name="WLRF_ANA_TIMER_RX_SLOT_ON_OFF_LAST" comment="This register sets the start and end of Rx turn on and off ramps, and the slot jumped to in the case of an Rx abort"/>
|
||||
<register addr="00004130" rw_flags="RW" width="2" name="WLRF_5G_TRIM_LUT0" comment="Values for LNA 5G trim buses when LNA gain is 0"/>
|
||||
<register addr="00004134" rw_flags="RW" width="2" name="WLRF_5G_TRIM_LUT1" comment="Values for LNA 5G trim buses when LNA gain is 1"/>
|
||||
<register addr="00004138" rw_flags="RW" width="2" name="WLRF_5G_TRIM_LUT2" comment="Values for LNA 5G trim buses when LNA gain is 2"/>
|
||||
<register addr="0000413c" rw_flags="RW" width="2" name="WLRF_5G_TRIM_LUT3" comment="Values for LNA 5G trim buses when LNA gain is 3"/>
|
||||
<register addr="00004140" rw_flags="RW" width="2" name="WLRF_5G_TRIM_LUT4" comment="Values for LNA 5G trim buses when LNA gain is 4"/>
|
||||
<register addr="00004144" rw_flags="RW" width="1" name="WLRF_INT_CLEAR" comment="Writing this register clears any interrupts whose corresponding bits are set in the write data. Bit allocations are as for WL_RF_INT_MASK"/>
|
||||
<register addr="00004148" rw_flags="RW" width="1" name="WLRF_INT_MASK" comment="This register masks events from causing interrupts. Only those interrupts whose mask bit is set will be delivered to the processors"/>
|
||||
<register addr="0000414c" rw_flags="R" width="2" name="WLRF_INT_STATUS" comment="This register has bits set in it for any interrupt that is currently active. In addition 'raw' bits are set for any active interrupt, whether it is masked or not"/>
|
||||
<register addr="00004150" rw_flags="RW" width="1" name="WL_ANA_BIAS_EN" comment="This register controls enabling of bias blocks within WLAN analogue"/>
|
||||
<register addr="00004154" rw_flags="RW" width="4" name="WL_ANA_TEST_EN" comment="This register controls enabling of test facilities"/>
|
||||
<register addr="00004158" rw_flags="RW" width="4" name="WL_ANA_DCOC_CTRL" comment="This register controls the DC offset compensation block"/>
|
||||
<register addr="0000415c" rw_flags="RW" width="4" name="WL_ANA_DCOC_CAL_GAINS" comment="This register contains the gains used during the calibration process by the DC offset compensation block"/>
|
||||
<register addr="00004160" rw_flags="RW" width="4" name="WL_ANA_DCOC_OVERRIDE" comment="This register controls the DC offset compensation block"/>
|
||||
<register addr="00004164" rw_flags="RW" width="4" name="WL_ANA_DCOC_OFFSET" comment="This register controls the DC offset compensation block fixed offsets"/>
|
||||
<register addr="00004168" rw_flags="RW" width="2" name="WL_ANA_ABB_DCOC_I_LUT" comment="This register is used to write the LUT that contains the DC offset values for the I receive channel. The location accessed is set by the current LNA and mixer gain"/>
|
||||
<register addr="0000416c" rw_flags="RW" width="2" name="WL_ANA_ABB_DCOC_Q_LUT" comment="This register is used to write the LUT that contains the DC offset values for the Q receive channel. The location accessed is set by the current LNA and mixer gain"/>
|
||||
<register addr="00004170" rw_flags="R" width="4" name="WL_ANA_ABB_DCOC_LUT_STATUS" comment="This register returns the value of the DC offset for the LUT entry corresponding to the current gain"/>
|
||||
<register addr="00004174" rw_flags="RW" width="4" name="WL_ANA_ABB_RX_CONFIG1" comment="This register controls Rx baseband"/>
|
||||
<register addr="00004178" rw_flags="RW" width="4" name="WL_ANA_ABB_RX_CONFIG2" comment="This register controls Rx baseband"/>
|
||||
<register addr="0000417c" rw_flags="RW" width="4" name="WL_ANA_ABB_RX_CONFIG3" comment="This register controls Rx baseband"/>
|
||||
<register addr="00004180" rw_flags="RW" width="2" name="WL_ANA_ABB_RX_CONFIG4" comment="This register controls Rx baseband"/>
|
||||
<register addr="00004184" rw_flags="RW" width="4" name="WL_ANA_ABB_RX_RSSI_CONFIG" comment="This register controls Rx RSSI blocks"/>
|
||||
<register addr="00004188" rw_flags="RW" width="4" name="WL_ANA_ABB_TX_CONFIG" comment="This register controls Rx baseband"/>
|
||||
<register addr="0000418c" rw_flags="RW" width="4" name="WL_ANA_ABB_PERIPH_CONFIG" comment="This register controls the peripheral block"/>
|
||||
<register addr="00004190" rw_flags="RW" width="4" name="WL_ANA_2G_RX_RF_CONFIG" comment="This register controls the 2G Rx RF block"/>
|
||||
<register addr="00004194" rw_flags="RW" width="2" name="WL_ANA_5G_RX_LNA_CONFIG" comment="This register controls the 5G Rx LNA block"/>
|
||||
<register addr="00004198" rw_flags="RW" width="4" name="WL_ANA_5G_RX_MIX_CONFIG" comment="This register controls the 5G Rx mixer block"/>
|
||||
<register addr="0000419c" rw_flags="RW" width="2" name="WL_ANA_RX_RF_MISC_CONFIG" comment="This register controls miscellaneous Rx RF features"/>
|
||||
<register addr="000041a0" rw_flags="RW" width="4" name="WL_ANA_TX_2G_MISC_CONFIG" comment="This register controls miscellaneous Tx RF features"/>
|
||||
<register addr="000041a4" rw_flags="RW" width="4" name="WL_ANA_TX_5G_MISC_CONFIG" comment="This register controls miscellaneous Tx RF features"/>
|
||||
<register addr="000041a8" rw_flags="RW" width="4" name="WL_ANA_TX_2G_MIX_DRV_CONFIG" comment="This register controls the Tx RF mixer and driver blocks"/>
|
||||
<register addr="000041ac" rw_flags="RW" width="4" name="WL_ANA_TX_5G_MIX_DRV_CONFIG" comment="This register controls the Tx RF mixer and driver blocks"/>
|
||||
<register addr="000041b0" rw_flags="RW" width="2" name="WL_ANA_TX_RF_PA_PROT_CONFIG" comment="This register controls the Tx RF PA and protection blocks"/>
|
||||
<register addr="000041b4" rw_flags="RW" width="4" name="WL_ANA_LO_TOP" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041b8" rw_flags="RW" width="4" name="WL_ANA_LO_CLKREF_ADC" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041bc" rw_flags="RW" width="4" name="WL_ANA_LO_D_FREQ1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041c0" rw_flags="RW" width="4" name="WL_ANA_LO_D_FREQ2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041c4" rw_flags="RW" width="1" name="WL_ANA_LO_PLL_STOP" comment="This register written to stop the PLL from running"/>
|
||||
<register addr="000041c8" rw_flags="RW" width="4" name="WL_ANA_LO_DPLL_CONF1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041cc" rw_flags="RW" width="4" name="WL_ANA_LO_PU_TDC_CONF" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041d0" rw_flags="RW" width="4" name="WL_ANA_LO_DCO_CONF1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041d4" rw_flags="RW" width="4" name="WL_ANA_LO_DCO_CONF2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041d8" rw_flags="RW" width="4" name="WL_ANA_LO_DPLL_CONF2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041dc" rw_flags="RW" width="4" name="WL_ANA_LO_TDC_NLMEM" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041e0" rw_flags="RW" width="4" name="WL_ANA_LO_PU_DCO_CONF" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041e4" rw_flags="RW" width="4" name="WL_ANA_LO_DCO_OPEN1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041e8" rw_flags="RW" width="4" name="WL_ANA_LO_DCO_OPEN2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041ec" rw_flags="RW" width="4" name="WL_ANA_LO_AREG_CONF" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041f0" rw_flags="RW" width="4" name="WL_ANA_LO_DCO_TEST" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041f4" rw_flags="RW" width="4" name="WL_ANA_LO_LOGEN1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041f8" rw_flags="RW" width="4" name="WL_ANA_LO_LOGEN2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041fc" rw_flags="RW" width="4" name="WL_ANA_LO_LDOREG_CFG2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="00004200" rw_flags="RW" width="4" name="WL_ANA_LO_DPLL_TEST" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="00004204" rw_flags="RW" width="4" name="WL_ANA_LO_TEST" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="00004208" rw_flags="RW" width="4" name="WL_ANA_LO_PLL_RESV" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="0000420c" rw_flags="R" width="4" name="WL_ANA_LO_DPLL_TEST_STATUS" comment="This register contains test outputs from the LO"/>
|
||||
</block>
|
||||
</subsystem>
|
||||
1275
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/hardware/moredump/wlan_sys_registers.xml
vendored
Normal file
1275
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/hardware/moredump/wlan_sys_registers.xml
vendored
Normal file
File diff suppressed because it is too large
Load diff
6475
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/hip_signals.xml
vendored
Normal file
6475
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/hip_signals.xml
vendored
Normal file
File diff suppressed because it is too large
Load diff
1
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/id.txt
vendored
Normal file
1
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/id.txt
vendored
Normal file
|
|
@ -0,0 +1 @@
|
|||
2018-07-18 10:26 javadXXdXX_core_hardmac_ram_gcc_integrated on5 498039164 adm-swbld@camsbugrd006@a3a6dcc086@HEAD (no branch)
|
||||
5175
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/mib_out.xml
vendored
Normal file
5175
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/mib_out.xml
vendored
Normal file
File diff suppressed because it is too large
Load diff
5840
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/symbols.dbg
vendored
Normal file
5840
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/symbols.dbg
vendored
Normal file
File diff suppressed because it is too large
Load diff
2229
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/unicli.dbg
vendored
Normal file
2229
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/unicli.dbg
vendored
Normal file
File diff suppressed because it is too large
Load diff
372
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/unitab.dbg
vendored
Normal file
372
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/unitab.dbg
vendored
Normal file
|
|
@ -0,0 +1,372 @@
|
|||
2 dot11RSNAStatsSTAAddress
|
||||
2 dot11RSNAStatsTKIPICVErrors
|
||||
2 dot11RSNAStatsTKIPLocalMICFailures
|
||||
2 dot11RSNAStatsTKIPRemoteMICFailures
|
||||
2 dot11RSNAStatsCCMPReplays
|
||||
2 dot11RSNAStatsCCMPDecryptErrors
|
||||
2 dot11RSNAStatsTKIPReplays
|
||||
2 dot11RSNAStatsRobustMgmtCCMPReplays
|
||||
0 dot11TDLSPeerUAPSDIndicationWindow
|
||||
0 dot11AssociationSAQueryMaximumTimeout
|
||||
0 dot11AssociationSAQueryRetryTimeout
|
||||
0 dot11PowerCapabilityMaxImplemented
|
||||
0 dot11PowerCapabilityMinImplemented
|
||||
0 dot11RTSThreshold
|
||||
0 dot11ShortRetryLimit
|
||||
0 dot11LongRetryLimit
|
||||
0 dot11FragmentationThreshold
|
||||
0 dot11RTSSuccessCount
|
||||
0 dot11ACKFailureCount
|
||||
0 dot11MulticastReceivedFrameCount
|
||||
0 dot11FCSErrorCount
|
||||
0 dot11WEPUndecryptableCount
|
||||
0 dot11manufacturerProductVersion
|
||||
0 unifiMLMEConnectionTimeOut
|
||||
0 unifiMLMEScanChannelMaxScanTime
|
||||
0 unifiMLMEScanChannelProbeInterval
|
||||
0 unifiMLMEDataReferenceTimeout
|
||||
0 unifiMLMEScanProbeInterval
|
||||
0 unifiMLMEScanHighRSSIThreshold
|
||||
0 unifiMLMEScanDeltaRSSIThreshold
|
||||
0 unifiMLMEScanMaximumAge
|
||||
0 unifiMLMEScanMaximumResults
|
||||
0 unifiMLMEAutonomousScanNoisy
|
||||
0 unifiFirmwareBuildID
|
||||
0 unifiChipVersion
|
||||
0 unifiFirmwarePatchBuildID
|
||||
0 unifiBasicCapabilities
|
||||
0 unifiExtendedCapabilities
|
||||
0 unifiHtCapabilities
|
||||
0 unifiRsnCapabilities
|
||||
0 unifi24G40MHZChannels
|
||||
0 unifiExtendedCapabilitiesDisabled
|
||||
0 unifiTestSetChannelBW
|
||||
0 unifiPLM689WorkaroundEnable
|
||||
0 unifiPLM689WorkaroundTriggerDHCPDiscoverCount
|
||||
0 unifiPLM689WorkaroundTriggerDHCPDiscoverTimeout
|
||||
0 unifiSupportedDataRates
|
||||
0 unifiPLM689WorkaroundAddresses
|
||||
0 unifiRadioMeasurementActivated
|
||||
0 unifiRadioMeasurementCapabilities
|
||||
0 unifiVhtActivated
|
||||
0 unifiHtActivated
|
||||
0 unifiPLM689WorkaroundTriggerStaticIPTimeout
|
||||
0 unifiPLM689WorkaroundTriggerARPCount
|
||||
0 unifiRoamingEnabled
|
||||
0 unifiRssiRoamScanTrigger
|
||||
0 unifiRoamDeltaTrigger
|
||||
0 unifiRoamCachedChannelScanPeriod
|
||||
0 unifiFullRoamScanPeriod
|
||||
0 unifiRoamScanBand
|
||||
0 unifiRoamScanMaxActiveChannelTime
|
||||
0 unifiRoamFullChannelScanFrequency
|
||||
0 unifiRoamMode
|
||||
0 unifiRssiRoamScanNoCandidateDeltaTrigger
|
||||
0 unifiRoamEAPTimeout
|
||||
0 unifiRoamScanControl
|
||||
0 unifiRoamDfsScanMode
|
||||
0 unifiRoamScanHomeTime
|
||||
0 unifiRoamScanHomeAwayTime
|
||||
0 unifiRoamScanNProbe
|
||||
0 unifiApOlbcDuration
|
||||
0 unifiApOlbcInterval
|
||||
0 unifiFrameResponseTimeOut
|
||||
0 unifiConnectionFailureTimeout
|
||||
0 unifiConnectingProbeTimeout
|
||||
0 unifiDisconnectTimeout
|
||||
0 unifiFrameResponseCfmTxLifetimeTimeOut
|
||||
0 unifiFrameResponseCfmFailureTimeOut
|
||||
0 unifiForceActiveDuration
|
||||
0 unifiMLMEScanMaxNumberOfProbeSets
|
||||
0 unifiMLMEScanStopIfLessThanXFrames
|
||||
0 unifiMLMEStationInactivityTimeOut
|
||||
0 unifiMLMECliInactivityTimeOut
|
||||
0 unifiMLMEStationInitialKickTimeOut
|
||||
0 unifiUartConfigure
|
||||
0 unifiUartPios
|
||||
0 unifiClockFrequency
|
||||
0 unifiCrystalFrequencyTrim
|
||||
0 unifiEnableDorm
|
||||
0 unifiDisableDormWhenBtOn
|
||||
0 unifiExternalClockDetect
|
||||
0 unifiExternalFastClockRequest
|
||||
0 unifiWatchdogTimeout
|
||||
0 unifiExternalFastClockRequestPIO
|
||||
0 unifiRSSI
|
||||
0 unifiLastBssRSSI
|
||||
0 unifiSNR
|
||||
0 unifiLastBssSNR
|
||||
0 unifiSwTxTimeout
|
||||
0 unifiHwTxTimeout
|
||||
0 unifiTxDataRate
|
||||
0 unifiSNRExtraOffsetCCK
|
||||
0 unifiRSSIMaxAveragingPeriod
|
||||
0 unifiRSSIMinReceivedFrames
|
||||
0 unifiLastBssTxDataRate
|
||||
0 unifiDiscardedFrameCount
|
||||
0 unifiMacrameDebugStats
|
||||
0 unifiCurrentTSFTime
|
||||
0 unifiBaTxEnableTid
|
||||
0 unifiBaConfig
|
||||
0 unifiMoveBKtoBE
|
||||
0 unifiBeaconReceived
|
||||
0 unifiRadioOnTime
|
||||
0 unifiRadioTxTime
|
||||
0 unifiRadioRxTime
|
||||
0 unifiRadioScanTime
|
||||
0 unifiPSLeakyAP
|
||||
0 unifiTqamActivated
|
||||
0 unifiNoAckActivationCount
|
||||
0 unifiRxFcsErrorCount
|
||||
0 unifiBeaconsReceivedPercentage
|
||||
0 unifiQueueStatsEnable
|
||||
0 unifiDpdMasterSwitch
|
||||
0 unifiGoogleMaxNumberOfPeriodicScans
|
||||
0 unifiGoogleMaxRSSISampleSize
|
||||
0 unifiGoogleMaxHotlistAPs
|
||||
0 unifiGoogleMaxSignificantWifiChangeAPs
|
||||
0 unifiGoogleMaxBssidHistoryEntries
|
||||
0 unifiMacBeaconTimeout
|
||||
0 UnifiRoamTrackingScanPeriod
|
||||
0 unifiRoamCuLocal
|
||||
0 unifiCuRoamScanNoCandidateDeltaTrigger
|
||||
0 unifiRoamAPSelectDeltaFactor
|
||||
0 unifiCURoamweight
|
||||
0 unifiRSSIRoamweight
|
||||
0 unifiRoamBSSLoadMonitoringFrequency
|
||||
0 unifiCUMeasurementInterval
|
||||
0 unifiCurrentBssNss
|
||||
0 unifiAPMimoUsed
|
||||
0 unifiRoamOffloaded4wshkTimeout
|
||||
0 unifiRoamingCount
|
||||
0 unifiRoamingAKM
|
||||
0 unifiCurrentBssBandwidth
|
||||
0 unifiCurrentBssChannelFrequency
|
||||
0 unifiLoggerEnabled
|
||||
0 unifiMaPacketFateEnabled
|
||||
0 unifiCSROnlyEIFSDuration
|
||||
0 unifiOverrideDefaultBETXOPForHT
|
||||
0 unifiOverrideDefaultBETXOP
|
||||
0 unifiRXABBTrimSettings
|
||||
0 unifiRadioTrimsEnable
|
||||
0 unifiHardwarePlatform
|
||||
0 unifiForceChannelBW
|
||||
0 unifiDPDTrainingDuration
|
||||
0 unifiCoexDebugOverrideBt
|
||||
0 unifiFastPowerSaveTimeout
|
||||
0 unifiFastPowerSaveTimeOutSmall
|
||||
0 unifiMLMESTAKeepAliveTimeout
|
||||
0 unifiMLMEAPKeepAliveTimeout
|
||||
0 unifiMLMEGOKeepAliveTimeout
|
||||
0 unifiSTARouterAdvertisementMinimumIntervalToForward
|
||||
0 unifiRoamConnectionQualityCheckWaitAfterConnect
|
||||
0 unifiApBeaconMaxDrift
|
||||
0 unifiBSSMaxIdlePeriodEnabled
|
||||
0 unifiVifIdleMonitorTime
|
||||
0 unifiDisableLegacyPowerSave
|
||||
0 unifiDebugForceActive
|
||||
0 unifiStationActivityIdleTime
|
||||
0 unifiPowerManagementDelayTimeout
|
||||
0 unifiAPSDServicePeriodTimeout
|
||||
0 unifiConcurrentPowerManagementDelayTimeout
|
||||
0 unifiStationQosInfo
|
||||
0 unifiListenIntervalSkippingDTIM
|
||||
0 unifiListenInterval
|
||||
0 unifiLegacyPsPollTimeout
|
||||
0 unifiTogglePowerDomain
|
||||
0 unifiP2PListenIntervalSkippingDTIM
|
||||
0 unifiFragmentationDuration
|
||||
0 unifiIdleModeLiteEnabled
|
||||
0 unifiIdleModeEnabled
|
||||
0 unifiDTIMWaitTimeout
|
||||
0 unifiListenIntervalMaxTime
|
||||
0 unifiScanMaxProbeTransmitLifetime
|
||||
0 unifiPowerSaveTransitionPacketThreshold
|
||||
0 unifiProbeResponseLifetime
|
||||
0 unifiProbeResponseMaxRetry
|
||||
0 unifiExitPowerSavePeriod
|
||||
0 unifiAggressivePowerSaveTransitionPeriod
|
||||
0 unifiActiveTimeAfterMoreBit
|
||||
0 unifiForcedScheduleDuration
|
||||
0 unifiVhtCapabilities
|
||||
0 unifiMAXVifScheduleDuration
|
||||
0 unifiVifLongIntervalTime
|
||||
0 unifiDisallowSchedRelinquish
|
||||
0 unifiRameDplaneOperationTimeout
|
||||
0 unifiDebugKeepRadioOn
|
||||
0 unifiScanAbsenceDuration
|
||||
0 unifiScanAbsencePeriod
|
||||
0 unifiMaxClient
|
||||
0 unifiTdlsInP2pActivated
|
||||
0 unifiTdlsActivated
|
||||
0 unifiTdlsTPThresholdPktSecs
|
||||
0 unifiTdlsRssiThreshold
|
||||
0 unifiTdlsMaximumRetry
|
||||
0 unifiTdlsTPMonitorSecs
|
||||
0 unifiTdlsBasicHtMcsSet
|
||||
0 unifiTdlsBasicVhtMcsSet
|
||||
0 dot11TDLSDiscoveryRequestWindow
|
||||
0 dot11TDLSResponseTimeout
|
||||
0 dot11TDLSChannelSwitchActivated
|
||||
0 unifiTdlsDesignForTestMode
|
||||
0 unifiTdlsKeyLifeTimeInterval
|
||||
0 unifiTdlsTeardownFrameTxTimeout
|
||||
0 unifiWifiSharingEnabled
|
||||
0 unifiWiFiSharing5GHzChannel
|
||||
0 unifiWifiSharingChannelSwitchCount
|
||||
0 unifiChannelAnnouncementCount
|
||||
0 unifiRATestStoredSA
|
||||
0 unifiRATestStoreFrame
|
||||
0 dot11TDLSPeerUAPSDBufferSTAActivated
|
||||
0 unifiCSROnlyMIBShield
|
||||
0 unifiPrivateBbbTxFilterConfig
|
||||
0 unifiPrivateSWAGCFrontEndGain
|
||||
0 unifiPrivateSWAGCFrontEndLoss
|
||||
0 unifiPrivateSWAGCExtThresh
|
||||
0 unifiCSROnlyPowerCalDelay
|
||||
0 unifiRxAgcControl
|
||||
0 unifiWapiQosMask
|
||||
0 unifiRaaMaxSpecTimerMultiplier
|
||||
0 unifiWMMStallEnable
|
||||
0 unifiRaaSpeculationInterval
|
||||
0 unifiRaaSpeculationPeriod
|
||||
0 unifiRaaNumbSpeculationFrames
|
||||
0 unifiRaaTxHostRate
|
||||
0 unifiFallbackShortFrameRetryDistribution
|
||||
0 unifiPreEBRTWindow
|
||||
0 unifiPostEBRTWindow
|
||||
0 unifiPsPollThreshold
|
||||
0 unifiTxUsingLdpcEnabled
|
||||
0 unifiTxSGI20Enabled
|
||||
0 unifiTxSGI40Enabled
|
||||
0 unifiTxSGI80Enabled
|
||||
0 unifiTxSGI160Enabled
|
||||
0 unifiMacAddressRandomisation
|
||||
0 unifiSuBeamformerEnabled
|
||||
0 unifiMuBeamformerEnabled
|
||||
0 unifiTxOfdmSelect
|
||||
0 unifiTxDigGain
|
||||
0 unifiChipTemperature
|
||||
0 UnifiBatteryVoltage
|
||||
0 unifiForceShortSlotTime
|
||||
0 unifiDebugDisableRadioNannyActions
|
||||
0 unifiRxCckModemSensitivity
|
||||
0 unifiDpdPerBandwidth
|
||||
0 unifiBBVersion
|
||||
0 unifiRFVersion
|
||||
0 unifiClearRadioTrimCache
|
||||
0 unifiRxRadioCsMode
|
||||
0 unifiRxPriEnergyDetThreshold
|
||||
0 unifiRxSecEnergyDetThreshold
|
||||
0 unifiCCAMasterSwitch
|
||||
0 unifiRxSyncCCACfg
|
||||
0 unifiMacSecChanClearTime
|
||||
0 unifiLnaControlEnabled
|
||||
0 unifiLnaControlRssiThresholdLower
|
||||
0 unifiLnaControlRssiThresholdUpper
|
||||
0 unifiLowPowerRxConfig
|
||||
0 unifiTPCEnabled
|
||||
0 unifiCurrentTxpowerLevel
|
||||
0 unifiUserSetTxpowerLevel
|
||||
0 unifiTPCMaxPowerRSSIThreshold
|
||||
0 unifiTPCMinPowerRSSIThreshold
|
||||
0 unifiTPCMinPower2G
|
||||
0 unifiTPCMinPower5G
|
||||
0 unifiRadioLpRxRssiThresholdLower
|
||||
0 unifiRadioLpRxRssiThresholdUpper
|
||||
0 unifiPMFAssociationComebackTimeDelta
|
||||
0 unifiTestTspecHack
|
||||
0 unifiTestTspecHackValue
|
||||
0 unifiDebugInstantDelivery
|
||||
0 unifiDebugEnable
|
||||
0 unifiDPlaneDebug
|
||||
0 unifiNANEnabled
|
||||
0 unifiNANBeaconCapabilities
|
||||
0 hutsReadWriteDataElementInt32
|
||||
0 hutsReadWriteDataElementBoolean
|
||||
0 hutsReadWriteDataElementOctetString
|
||||
0 hutsReadWriteRemoteProcedureCallInt32
|
||||
0 hutsReadWriteInternalAPIInt16
|
||||
0 hutsReadWriteInternalAPIUint16
|
||||
0 hutsReadWriteInternalAPIUint32
|
||||
0 hutsReadWriteInternalAPIInt64
|
||||
0 hutsReadWriteInternalAPIBoolean
|
||||
0 hutsReadWriteInternalAPIOctetString
|
||||
0 unifiTestScanNoMedium
|
||||
0 unifiDualBandConcurrency
|
||||
0 unifiSupportedChannels
|
||||
0 unifiCountryList
|
||||
0 unifiNoCellIncludedChannels
|
||||
2 hutsReadWriteInternalAPIFixSizeTableKeyRow
|
||||
1 hutsReadWriteInternalAPIFixSizeTableKey1Row
|
||||
1 hutsReadWriteInternalAPIFixSizeTableKey2Row
|
||||
1 hutsReadWriteInternalAPIFixVarSizeTableKey1Row
|
||||
1 hutsReadWriteInternalAPIFixVarSizeTableKey2Row
|
||||
1 hutsReadWriteInternalAPIFixedSizeTableRow
|
||||
1 hutsReadWriteInternalAPIVarSizeTableRow
|
||||
2 hutsReadWriteInternalAPIVarSizeTableKeyRow
|
||||
2 hutsReadWriteRemoteProcedureCallOctetString
|
||||
1 hutsReadWriteTableInt16Row
|
||||
1 hutsReadWriteTableOctetStringRow
|
||||
1 unifiACRetries
|
||||
1 unifiTxDataConfirm
|
||||
1 unifiCCACSThresh
|
||||
1 unifiCURoamScanTrigger
|
||||
1 unifiCURoamfactor
|
||||
1 unifiDPDTrainPacketConfig
|
||||
1 unifiDebugModuleControl
|
||||
1 unifiDefaultCountry
|
||||
1 unifiDpdPredistortGains
|
||||
2 unifiLoadDpdLut
|
||||
2 unifiOverrideDpdLut
|
||||
2 unifiMacCCABusyTime
|
||||
2 unifiModemSgiOffset
|
||||
1 unifiNoCellMaxPower
|
||||
1 unifiOperatingClassParamters
|
||||
1 unifiPeerBandwidth
|
||||
1 unifiCurrentPeerNss
|
||||
1 unifiPeerTxDataRate
|
||||
1 unifiPeerRSSI
|
||||
1 unifiSwToHwQueueStats
|
||||
1 unifiHostToSwQueueStats
|
||||
1 unifiRSSICURoamScanTrigger
|
||||
1 unifiRSSIRoamfactor
|
||||
2 unifiRadioCCADebug
|
||||
1 unifiRadioCCAThresholds
|
||||
2 unifiRadioRXSettingsRead
|
||||
2 unifiRadioTXSettingsRead
|
||||
1 unifiRadioTxPowerOverride
|
||||
1 unifiRateStatsRxSuccessCount
|
||||
1 unifiRateStatsTxSuccessCount
|
||||
1 unifiRateStatsRate
|
||||
1 unifiRaaTxSuccessesCount
|
||||
1 unifiRaaTxFailuresCount
|
||||
1 unifiRaaTxPer
|
||||
1 unifiRaaResetStats
|
||||
1 unifiRaaTxMTPer
|
||||
2 unifiReadHardwareCounter
|
||||
1 unifiReadReg
|
||||
1 unifiRegulatoryParameters
|
||||
1 unifiRoamRSSIBoost
|
||||
1 unifiRxExternalGainFrequency
|
||||
1 unifiRxExternalGain
|
||||
1 unifiSarBackoff
|
||||
1 unifiScanParameters
|
||||
1 unifiThroughputDebug
|
||||
1 unifiTxAntennaConnectionLossFrequency
|
||||
1 unifiTxAntennaConnectionLoss
|
||||
1 unifiTxAntennaMaxGainFrequency
|
||||
1 unifiTxAntennaMaxGain
|
||||
1 unifiTxDetectorFrequencyCompensation
|
||||
1 unifiTxDetectorTemperatureCompensation
|
||||
1 unifiTxFtrimSettings
|
||||
1 unifiTxGainSettings
|
||||
1 unifiTxGainStepSettings
|
||||
1 unifiTxOOBConstraints
|
||||
1 unifiTxOpenLoopFrequencyCompensation
|
||||
1 unifiTxOpenLoopTemperatureCompensation
|
||||
1 unifiTxPaGainDpdFrequencyCompensation
|
||||
1 unifiTxPaGainDpdTemperatureCompensation
|
||||
1 unifiTxPowerDetectorResponse
|
||||
1 unifiTxPowerTrimConfig
|
||||
1 unifiTxSettings
|
||||
372
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/univif.dbg
vendored
Normal file
372
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/univif.dbg
vendored
Normal file
|
|
@ -0,0 +1,372 @@
|
|||
z dot11RSNAStatsSTAAddress
|
||||
z dot11RSNAStatsTKIPICVErrors
|
||||
z dot11RSNAStatsTKIPLocalMICFailures
|
||||
z dot11RSNAStatsTKIPRemoteMICFailures
|
||||
z dot11RSNAStatsCCMPReplays
|
||||
z dot11RSNAStatsCCMPDecryptErrors
|
||||
z dot11RSNAStatsTKIPReplays
|
||||
z dot11RSNAStatsRobustMgmtCCMPReplays
|
||||
z dot11TDLSPeerUAPSDIndicationWindow
|
||||
z dot11AssociationSAQueryMaximumTimeout
|
||||
z dot11AssociationSAQueryRetryTimeout
|
||||
z dot11PowerCapabilityMaxImplemented
|
||||
z dot11PowerCapabilityMinImplemented
|
||||
p dot11RTSThreshold
|
||||
p dot11ShortRetryLimit
|
||||
p dot11LongRetryLimit
|
||||
p dot11FragmentationThreshold
|
||||
p dot11RTSSuccessCount
|
||||
p dot11ACKFailureCount
|
||||
p dot11MulticastReceivedFrameCount
|
||||
p dot11FCSErrorCount
|
||||
p dot11WEPUndecryptableCount
|
||||
z dot11manufacturerProductVersion
|
||||
z unifiMLMEConnectionTimeOut
|
||||
z unifiMLMEScanChannelMaxScanTime
|
||||
z unifiMLMEScanChannelProbeInterval
|
||||
z unifiMLMEDataReferenceTimeout
|
||||
z unifiMLMEScanProbeInterval
|
||||
z unifiMLMEScanHighRSSIThreshold
|
||||
z unifiMLMEScanDeltaRSSIThreshold
|
||||
z unifiMLMEScanMaximumAge
|
||||
z unifiMLMEScanMaximumResults
|
||||
z unifiMLMEAutonomousScanNoisy
|
||||
z unifiFirmwareBuildID
|
||||
z unifiChipVersion
|
||||
z unifiFirmwarePatchBuildID
|
||||
z unifiBasicCapabilities
|
||||
z unifiExtendedCapabilities
|
||||
z unifiHtCapabilities
|
||||
z unifiRsnCapabilities
|
||||
z unifi24G40MHZChannels
|
||||
z unifiExtendedCapabilitiesDisabled
|
||||
p unifiTestSetChannelBW
|
||||
z unifiPLM689WorkaroundEnable
|
||||
z unifiPLM689WorkaroundTriggerDHCPDiscoverCount
|
||||
z unifiPLM689WorkaroundTriggerDHCPDiscoverTimeout
|
||||
z unifiSupportedDataRates
|
||||
z unifiPLM689WorkaroundAddresses
|
||||
z unifiRadioMeasurementActivated
|
||||
z unifiRadioMeasurementCapabilities
|
||||
z unifiVhtActivated
|
||||
z unifiHtActivated
|
||||
z unifiPLM689WorkaroundTriggerStaticIPTimeout
|
||||
z unifiPLM689WorkaroundTriggerARPCount
|
||||
z unifiRoamingEnabled
|
||||
z unifiRssiRoamScanTrigger
|
||||
z unifiRoamDeltaTrigger
|
||||
z unifiRoamCachedChannelScanPeriod
|
||||
z unifiFullRoamScanPeriod
|
||||
z unifiRoamScanBand
|
||||
z unifiRoamScanMaxActiveChannelTime
|
||||
z unifiRoamFullChannelScanFrequency
|
||||
z unifiRoamMode
|
||||
z unifiRssiRoamScanNoCandidateDeltaTrigger
|
||||
z unifiRoamEAPTimeout
|
||||
z unifiRoamScanControl
|
||||
z unifiRoamDfsScanMode
|
||||
z unifiRoamScanHomeTime
|
||||
z unifiRoamScanHomeAwayTime
|
||||
z unifiRoamScanNProbe
|
||||
z unifiApOlbcDuration
|
||||
z unifiApOlbcInterval
|
||||
z unifiFrameResponseTimeOut
|
||||
z unifiConnectionFailureTimeout
|
||||
z unifiConnectingProbeTimeout
|
||||
z unifiDisconnectTimeout
|
||||
z unifiFrameResponseCfmTxLifetimeTimeOut
|
||||
z unifiFrameResponseCfmFailureTimeOut
|
||||
z unifiForceActiveDuration
|
||||
z unifiMLMEScanMaxNumberOfProbeSets
|
||||
z unifiMLMEScanStopIfLessThanXFrames
|
||||
z unifiMLMEStationInactivityTimeOut
|
||||
z unifiMLMECliInactivityTimeOut
|
||||
z unifiMLMEStationInitialKickTimeOut
|
||||
z unifiUartConfigure
|
||||
z unifiUartPios
|
||||
z unifiClockFrequency
|
||||
z unifiCrystalFrequencyTrim
|
||||
z unifiEnableDorm
|
||||
z unifiDisableDormWhenBtOn
|
||||
z unifiExternalClockDetect
|
||||
z unifiExternalFastClockRequest
|
||||
z unifiWatchdogTimeout
|
||||
z unifiExternalFastClockRequestPIO
|
||||
p unifiRSSI
|
||||
z unifiLastBssRSSI
|
||||
p unifiSNR
|
||||
z unifiLastBssSNR
|
||||
z unifiSwTxTimeout
|
||||
z unifiHwTxTimeout
|
||||
p unifiTxDataRate
|
||||
z unifiSNRExtraOffsetCCK
|
||||
z unifiRSSIMaxAveragingPeriod
|
||||
z unifiRSSIMinReceivedFrames
|
||||
z unifiLastBssTxDataRate
|
||||
p unifiDiscardedFrameCount
|
||||
z unifiMacrameDebugStats
|
||||
p unifiCurrentTSFTime
|
||||
z unifiBaTxEnableTid
|
||||
z unifiBaConfig
|
||||
z unifiMoveBKtoBE
|
||||
p unifiBeaconReceived
|
||||
z unifiRadioOnTime
|
||||
z unifiRadioTxTime
|
||||
z unifiRadioRxTime
|
||||
z unifiRadioScanTime
|
||||
p unifiPSLeakyAP
|
||||
z unifiTqamActivated
|
||||
z unifiNoAckActivationCount
|
||||
z unifiRxFcsErrorCount
|
||||
p unifiBeaconsReceivedPercentage
|
||||
p unifiQueueStatsEnable
|
||||
z unifiDpdMasterSwitch
|
||||
z unifiGoogleMaxNumberOfPeriodicScans
|
||||
z unifiGoogleMaxRSSISampleSize
|
||||
z unifiGoogleMaxHotlistAPs
|
||||
z unifiGoogleMaxSignificantWifiChangeAPs
|
||||
z unifiGoogleMaxBssidHistoryEntries
|
||||
z unifiMacBeaconTimeout
|
||||
z UnifiRoamTrackingScanPeriod
|
||||
z unifiRoamCuLocal
|
||||
z unifiCuRoamScanNoCandidateDeltaTrigger
|
||||
z unifiRoamAPSelectDeltaFactor
|
||||
z unifiCURoamweight
|
||||
z unifiRSSIRoamweight
|
||||
z unifiRoamBSSLoadMonitoringFrequency
|
||||
z unifiCUMeasurementInterval
|
||||
z unifiCurrentBssNss
|
||||
z unifiAPMimoUsed
|
||||
z unifiRoamOffloaded4wshkTimeout
|
||||
z unifiRoamingCount
|
||||
z unifiRoamingAKM
|
||||
z unifiCurrentBssBandwidth
|
||||
z unifiCurrentBssChannelFrequency
|
||||
z unifiLoggerEnabled
|
||||
z unifiMaPacketFateEnabled
|
||||
z unifiCSROnlyEIFSDuration
|
||||
z unifiOverrideDefaultBETXOPForHT
|
||||
z unifiOverrideDefaultBETXOP
|
||||
z unifiRXABBTrimSettings
|
||||
z unifiRadioTrimsEnable
|
||||
z unifiHardwarePlatform
|
||||
z unifiForceChannelBW
|
||||
z unifiDPDTrainingDuration
|
||||
z unifiCoexDebugOverrideBt
|
||||
z unifiFastPowerSaveTimeout
|
||||
z unifiFastPowerSaveTimeOutSmall
|
||||
z unifiMLMESTAKeepAliveTimeout
|
||||
z unifiMLMEAPKeepAliveTimeout
|
||||
z unifiMLMEGOKeepAliveTimeout
|
||||
z unifiSTARouterAdvertisementMinimumIntervalToForward
|
||||
z unifiRoamConnectionQualityCheckWaitAfterConnect
|
||||
z unifiApBeaconMaxDrift
|
||||
z unifiBSSMaxIdlePeriodEnabled
|
||||
z unifiVifIdleMonitorTime
|
||||
z unifiDisableLegacyPowerSave
|
||||
z unifiDebugForceActive
|
||||
z unifiStationActivityIdleTime
|
||||
z unifiPowerManagementDelayTimeout
|
||||
p unifiAPSDServicePeriodTimeout
|
||||
z unifiConcurrentPowerManagementDelayTimeout
|
||||
z unifiStationQosInfo
|
||||
z unifiListenIntervalSkippingDTIM
|
||||
z unifiListenInterval
|
||||
p unifiLegacyPsPollTimeout
|
||||
z unifiTogglePowerDomain
|
||||
z unifiP2PListenIntervalSkippingDTIM
|
||||
p unifiFragmentationDuration
|
||||
z unifiIdleModeLiteEnabled
|
||||
z unifiIdleModeEnabled
|
||||
z unifiDTIMWaitTimeout
|
||||
z unifiListenIntervalMaxTime
|
||||
z unifiScanMaxProbeTransmitLifetime
|
||||
z unifiPowerSaveTransitionPacketThreshold
|
||||
z unifiProbeResponseLifetime
|
||||
z unifiProbeResponseMaxRetry
|
||||
z unifiExitPowerSavePeriod
|
||||
z unifiAggressivePowerSaveTransitionPeriod
|
||||
z unifiActiveTimeAfterMoreBit
|
||||
p unifiForcedScheduleDuration
|
||||
z unifiVhtCapabilities
|
||||
z unifiMAXVifScheduleDuration
|
||||
z unifiVifLongIntervalTime
|
||||
z unifiDisallowSchedRelinquish
|
||||
z unifiRameDplaneOperationTimeout
|
||||
z unifiDebugKeepRadioOn
|
||||
z unifiScanAbsenceDuration
|
||||
z unifiScanAbsencePeriod
|
||||
z unifiMaxClient
|
||||
z unifiTdlsInP2pActivated
|
||||
z unifiTdlsActivated
|
||||
z unifiTdlsTPThresholdPktSecs
|
||||
z unifiTdlsRssiThreshold
|
||||
z unifiTdlsMaximumRetry
|
||||
z unifiTdlsTPMonitorSecs
|
||||
z unifiTdlsBasicHtMcsSet
|
||||
z unifiTdlsBasicVhtMcsSet
|
||||
z dot11TDLSDiscoveryRequestWindow
|
||||
z dot11TDLSResponseTimeout
|
||||
z dot11TDLSChannelSwitchActivated
|
||||
z unifiTdlsDesignForTestMode
|
||||
z unifiTdlsKeyLifeTimeInterval
|
||||
z unifiTdlsTeardownFrameTxTimeout
|
||||
z unifiWifiSharingEnabled
|
||||
z unifiWiFiSharing5GHzChannel
|
||||
z unifiWifiSharingChannelSwitchCount
|
||||
z unifiChannelAnnouncementCount
|
||||
z unifiRATestStoredSA
|
||||
z unifiRATestStoreFrame
|
||||
z dot11TDLSPeerUAPSDBufferSTAActivated
|
||||
z unifiCSROnlyMIBShield
|
||||
z unifiPrivateBbbTxFilterConfig
|
||||
z unifiPrivateSWAGCFrontEndGain
|
||||
z unifiPrivateSWAGCFrontEndLoss
|
||||
z unifiPrivateSWAGCExtThresh
|
||||
z unifiCSROnlyPowerCalDelay
|
||||
z unifiRxAgcControl
|
||||
z unifiWapiQosMask
|
||||
z unifiRaaMaxSpecTimerMultiplier
|
||||
z unifiWMMStallEnable
|
||||
z unifiRaaSpeculationInterval
|
||||
z unifiRaaSpeculationPeriod
|
||||
z unifiRaaNumbSpeculationFrames
|
||||
z unifiRaaTxHostRate
|
||||
z unifiFallbackShortFrameRetryDistribution
|
||||
p unifiPreEBRTWindow
|
||||
p unifiPostEBRTWindow
|
||||
p unifiPsPollThreshold
|
||||
z unifiTxUsingLdpcEnabled
|
||||
z unifiTxSGI20Enabled
|
||||
z unifiTxSGI40Enabled
|
||||
z unifiTxSGI80Enabled
|
||||
z unifiTxSGI160Enabled
|
||||
z unifiMacAddressRandomisation
|
||||
z unifiSuBeamformerEnabled
|
||||
z unifiMuBeamformerEnabled
|
||||
z unifiTxOfdmSelect
|
||||
z unifiTxDigGain
|
||||
z unifiChipTemperature
|
||||
z UnifiBatteryVoltage
|
||||
z unifiForceShortSlotTime
|
||||
z unifiDebugDisableRadioNannyActions
|
||||
z unifiRxCckModemSensitivity
|
||||
z unifiDpdPerBandwidth
|
||||
z unifiBBVersion
|
||||
z unifiRFVersion
|
||||
z unifiClearRadioTrimCache
|
||||
z unifiRxRadioCsMode
|
||||
z unifiRxPriEnergyDetThreshold
|
||||
z unifiRxSecEnergyDetThreshold
|
||||
z unifiCCAMasterSwitch
|
||||
z unifiRxSyncCCACfg
|
||||
z unifiMacSecChanClearTime
|
||||
z unifiLnaControlEnabled
|
||||
z unifiLnaControlRssiThresholdLower
|
||||
z unifiLnaControlRssiThresholdUpper
|
||||
z unifiLowPowerRxConfig
|
||||
z unifiTPCEnabled
|
||||
p unifiCurrentTxpowerLevel
|
||||
z unifiUserSetTxpowerLevel
|
||||
z unifiTPCMaxPowerRSSIThreshold
|
||||
z unifiTPCMinPowerRSSIThreshold
|
||||
z unifiTPCMinPower2G
|
||||
z unifiTPCMinPower5G
|
||||
z unifiRadioLpRxRssiThresholdLower
|
||||
z unifiRadioLpRxRssiThresholdUpper
|
||||
z unifiPMFAssociationComebackTimeDelta
|
||||
z unifiTestTspecHack
|
||||
z unifiTestTspecHackValue
|
||||
z unifiDebugInstantDelivery
|
||||
z unifiDebugEnable
|
||||
z unifiDPlaneDebug
|
||||
z unifiNANEnabled
|
||||
z unifiNANBeaconCapabilities
|
||||
z hutsReadWriteDataElementInt32
|
||||
z hutsReadWriteDataElementBoolean
|
||||
z hutsReadWriteDataElementOctetString
|
||||
p hutsReadWriteRemoteProcedureCallInt32
|
||||
z hutsReadWriteInternalAPIInt16
|
||||
z hutsReadWriteInternalAPIUint16
|
||||
z hutsReadWriteInternalAPIUint32
|
||||
p hutsReadWriteInternalAPIInt64
|
||||
z hutsReadWriteInternalAPIBoolean
|
||||
z hutsReadWriteInternalAPIOctetString
|
||||
z unifiTestScanNoMedium
|
||||
z unifiDualBandConcurrency
|
||||
z unifiSupportedChannels
|
||||
z unifiCountryList
|
||||
z unifiNoCellIncludedChannels
|
||||
z hutsReadWriteInternalAPIFixSizeTableKeyRow
|
||||
p hutsReadWriteInternalAPIFixSizeTableKey1Row
|
||||
p hutsReadWriteInternalAPIFixSizeTableKey2Row
|
||||
z hutsReadWriteInternalAPIFixVarSizeTableKey1Row
|
||||
z hutsReadWriteInternalAPIFixVarSizeTableKey2Row
|
||||
z hutsReadWriteInternalAPIFixedSizeTableRow
|
||||
z hutsReadWriteInternalAPIVarSizeTableRow
|
||||
z hutsReadWriteInternalAPIVarSizeTableKeyRow
|
||||
z hutsReadWriteRemoteProcedureCallOctetString
|
||||
p hutsReadWriteTableInt16Row
|
||||
z hutsReadWriteTableOctetStringRow
|
||||
p unifiACRetries
|
||||
z unifiTxDataConfirm
|
||||
z unifiCCACSThresh
|
||||
z unifiCURoamScanTrigger
|
||||
z unifiCURoamfactor
|
||||
z unifiDPDTrainPacketConfig
|
||||
z unifiDebugModuleControl
|
||||
z unifiDefaultCountry
|
||||
z unifiDpdPredistortGains
|
||||
z unifiLoadDpdLut
|
||||
z unifiOverrideDpdLut
|
||||
z unifiMacCCABusyTime
|
||||
z unifiModemSgiOffset
|
||||
z unifiNoCellMaxPower
|
||||
z unifiOperatingClassParamters
|
||||
z unifiPeerBandwidth
|
||||
z unifiCurrentPeerNss
|
||||
z unifiPeerTxDataRate
|
||||
z unifiPeerRSSI
|
||||
p unifiSwToHwQueueStats
|
||||
p unifiHostToSwQueueStats
|
||||
z unifiRSSICURoamScanTrigger
|
||||
z unifiRSSIRoamfactor
|
||||
z unifiRadioCCADebug
|
||||
z unifiRadioCCAThresholds
|
||||
z unifiRadioRXSettingsRead
|
||||
z unifiRadioTXSettingsRead
|
||||
z unifiRadioTxPowerOverride
|
||||
p unifiRateStatsRxSuccessCount
|
||||
p unifiRateStatsTxSuccessCount
|
||||
z unifiRateStatsRate
|
||||
p unifiRaaTxSuccessesCount
|
||||
p unifiRaaTxFailuresCount
|
||||
p unifiRaaTxPer
|
||||
p unifiRaaResetStats
|
||||
p unifiRaaTxMTPer
|
||||
z unifiReadHardwareCounter
|
||||
z unifiReadReg
|
||||
z unifiRegulatoryParameters
|
||||
z unifiRoamRSSIBoost
|
||||
z unifiRxExternalGainFrequency
|
||||
z unifiRxExternalGain
|
||||
z unifiSarBackoff
|
||||
z unifiScanParameters
|
||||
p unifiThroughputDebug
|
||||
z unifiTxAntennaConnectionLossFrequency
|
||||
z unifiTxAntennaConnectionLoss
|
||||
z unifiTxAntennaMaxGainFrequency
|
||||
z unifiTxAntennaMaxGain
|
||||
z unifiTxDetectorFrequencyCompensation
|
||||
z unifiTxDetectorTemperatureCompensation
|
||||
z unifiTxFtrimSettings
|
||||
z unifiTxGainSettings
|
||||
z unifiTxGainStepSettings
|
||||
z unifiTxOOBConstraints
|
||||
z unifiTxOpenLoopFrequencyCompensation
|
||||
z unifiTxOpenLoopTemperatureCompensation
|
||||
z unifiTxPaGainDpdFrequencyCompensation
|
||||
z unifiTxPaGainDpdTemperatureCompensation
|
||||
z unifiTxPowerDetectorResponse
|
||||
z unifiTxPowerTrimConfig
|
||||
z unifiTxSettings
|
||||
372
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/xide_mib.dbg
vendored
Normal file
372
universal7570-common/proprietary/vendor/etc/wifi/mx140/debug/wlan/xide_mib.dbg
vendored
Normal file
File diff suppressed because one or more lines are too long
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140_t.bin
vendored
Normal file
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140_t.bin
vendored
Normal file
Binary file not shown.
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/conf/wlan/hydra_config.sdb
vendored
Normal file
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/conf/wlan/hydra_config.sdb
vendored
Normal file
Binary file not shown.
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/conf/wlan/wlan.hcf
vendored
Normal file
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/conf/wlan/wlan.hcf
vendored
Normal file
Binary file not shown.
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/conf/wlan/wlan_t.hcf
vendored
Normal file
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/conf/wlan/wlan_t.hcf
vendored
Normal file
Binary file not shown.
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/common/log-strings.bin
vendored
Normal file
BIN
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/common/log-strings.bin
vendored
Normal file
Binary file not shown.
56
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/hardware/moredump/Memory.xsd
vendored
Normal file
56
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/hardware/moredump/Memory.xsd
vendored
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<xs:schema attributeFormDefault="unqualified" elementFormDefault="qualified" xmlns:xs="http://www.w3.org/2001/XMLSchema">
|
||||
|
||||
<!-- Define an address range -->
|
||||
<xs:complexType name="addressRange">
|
||||
<xs:attribute name="startAddr" type="xs:hexBinary" use="required" />
|
||||
<xs:attribute name="endAddr" type="xs:hexBinary" use="required" />
|
||||
</xs:complexType>
|
||||
|
||||
<!-- Define a region -->
|
||||
<xs:complexType name="region">
|
||||
<xs:complexContent>
|
||||
<xs:extension base="addressRange">
|
||||
<xs:attribute name="name" type="xs:string" use="optional" />
|
||||
<xs:attribute name="comment" type="xs:string" use="optional" />
|
||||
</xs:extension>
|
||||
</xs:complexContent>
|
||||
</xs:complexType>
|
||||
|
||||
<xs:element name="memory">
|
||||
<xs:complexType>
|
||||
<xs:sequence>
|
||||
<xs:choice maxOccurs="unbounded">
|
||||
<!-- Define the mmap range -->
|
||||
<!-- Memory regions outwith R4/M4 that fall within the mmap range will use the mmap interface (android only) -->
|
||||
<xs:element name="mmap" minOccurs="1" maxOccurs="1" type ="addressRange" />
|
||||
|
||||
<!-- Memory that will be read over any available interface, mmap, r4 or m4 (in that order) -->
|
||||
<!-- This element can occur before R4 and/or between R4/M4 and/or after M4-->
|
||||
<xs:element minOccurs="0" maxOccurs="unbounded" name="region" type="region" />
|
||||
|
||||
<!-- Memory specific to (and will only be read via) R4 -->
|
||||
<!-- will also be wrapped with IF (CPUIS("CortexR4")) in CMM -->
|
||||
<xs:element name="R4" minOccurs="0" maxOccurs="1">
|
||||
<xs:complexType>
|
||||
<xs:sequence>
|
||||
<xs:element minOccurs="0" maxOccurs="unbounded" name="region" type="region" />
|
||||
</xs:sequence>
|
||||
</xs:complexType>
|
||||
</xs:element>
|
||||
|
||||
<!-- Memory specific to (and will only be read via) M4 -->
|
||||
<!-- will also be wrapped with IF (CPUIS("CortexM4")) in CMM -->
|
||||
<xs:element name="M4" minOccurs="0" maxOccurs="1">
|
||||
<xs:complexType>
|
||||
<xs:sequence>
|
||||
<xs:element minOccurs="0" maxOccurs="unbounded" name="region" type="region" />
|
||||
</xs:sequence>
|
||||
</xs:complexType>
|
||||
</xs:element>
|
||||
|
||||
</xs:choice>
|
||||
</xs:sequence>
|
||||
</xs:complexType>
|
||||
</xs:element>
|
||||
</xs:schema>
|
||||
150
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/hardware/moredump/Registers.xsd
vendored
Normal file
150
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/hardware/moredump/Registers.xsd
vendored
Normal file
|
|
@ -0,0 +1,150 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<xs:schema attributeFormDefault="unqualified"
|
||||
elementFormDefault="qualified"
|
||||
xmlns:xs="http://www.w3.org/2001/XMLSchema">
|
||||
|
||||
<!-- Define the permissible memory classes -->
|
||||
<xs:simpleType name="class">
|
||||
<xs:restriction base="xs:string">
|
||||
<!-- Data memory -->
|
||||
<xs:enumeration value="D" />
|
||||
<!-- Data memory (supervisor access) -->
|
||||
<xs:enumeration value="S" />
|
||||
<!-- CP14 -->
|
||||
<xs:enumeration value="C14" />
|
||||
<!-- CP15 -->
|
||||
<xs:enumeration value="C15" />
|
||||
</xs:restriction>
|
||||
</xs:simpleType>
|
||||
|
||||
<!-- Define the permissible set of register widths in octets -->
|
||||
<xs:simpleType name="width">
|
||||
<xs:restriction base="xs:unsignedByte">
|
||||
<xs:enumeration value="1" />
|
||||
<xs:enumeration value="2" />
|
||||
<xs:enumeration value="4" />
|
||||
</xs:restriction>
|
||||
</xs:simpleType>
|
||||
|
||||
<!-- Define the read/write capability flags -->
|
||||
<xs:simpleType name="rw_flags">
|
||||
<xs:restriction base="xs:string">
|
||||
<xs:enumeration value="R" />
|
||||
<xs:enumeration value="W" />
|
||||
<xs:enumeration value="RW" />
|
||||
</xs:restriction>
|
||||
</xs:simpleType>
|
||||
|
||||
<!-- Define a basic register -->
|
||||
<xs:complexType name="register">
|
||||
<xs:attribute name="addr" type="xs:hexBinary" use="required" />
|
||||
<xs:attribute name="width" type="width" use="required" />
|
||||
<xs:attribute name="rw_flags" type="rw_flags" use="required" />
|
||||
<xs:attribute name="name" type="xs:string" use="optional" />
|
||||
<xs:attribute name="comment" type="xs:string" use="optional" />
|
||||
</xs:complexType>
|
||||
|
||||
<!-- Define a bit-field within a register -->
|
||||
<xs:complexType name="registerfield">
|
||||
<xs:complexContent>
|
||||
<xs:extension base="register">
|
||||
<xs:attribute name="shift" type="xs:unsignedShort" use="required" />
|
||||
<xs:attribute name="mask" type="xs:string" use="required" />
|
||||
</xs:extension>
|
||||
</xs:complexContent>
|
||||
</xs:complexType>
|
||||
|
||||
<!-- Define an index register -->
|
||||
<xs:complexType name="indexregister">
|
||||
<xs:complexContent>
|
||||
<xs:extension base="register">
|
||||
<xs:choice minOccurs="1" maxOccurs="1">
|
||||
<!-- Either an absolute count -->
|
||||
<xs:element name="count">
|
||||
<xs:complexType>
|
||||
<xs:attribute name="value" type="xs:unsignedShort" use="required" />
|
||||
</xs:complexType>
|
||||
</xs:element>
|
||||
<!-- or obtained indirectly from a register field -->
|
||||
<xs:element name="countfrom" type="registerfield" />
|
||||
</xs:choice>
|
||||
</xs:extension>
|
||||
</xs:complexContent>
|
||||
</xs:complexType>
|
||||
|
||||
<!-- Define a table -->
|
||||
<xs:complexType name="table">
|
||||
<xs:sequence>
|
||||
<!-- The one and only index register -->
|
||||
<xs:element name="indexregister" type="indexregister" minOccurs="1" maxOccurs="1" />
|
||||
<!-- and at least 1 other register in the table -->
|
||||
<xs:element name="register" type="register" minOccurs="1" maxOccurs="unbounded" />
|
||||
</xs:sequence>
|
||||
<xs:attribute name="name" type="xs:string" use="required" />
|
||||
</xs:complexType>
|
||||
|
||||
|
||||
<!-- Define a block -->
|
||||
<xs:complexType name="block">
|
||||
<!-- containing a number of tables or registers -->
|
||||
<xs:choice maxOccurs="unbounded">
|
||||
<xs:element name="register" type="register" />
|
||||
<xs:element name="table" type="table" />
|
||||
</xs:choice>
|
||||
<xs:attribute name="name" type="xs:string" use="optional" />
|
||||
<xs:attribute name="comment" type="xs:string" use="optional" />
|
||||
<xs:attribute name="description" type="xs:string" use="optional" />
|
||||
</xs:complexType>
|
||||
|
||||
<!-- Define a memory-mapped region -->
|
||||
<xs:complexType name="memory">
|
||||
<xs:choice maxOccurs="unbounded">
|
||||
<xs:element minOccurs="1" maxOccurs="unbounded" name="register" type="register" />
|
||||
<xs:element name="block" type="block" />
|
||||
<xs:element name="table" type="table" />
|
||||
</xs:choice>
|
||||
<xs:attribute name="name" type="xs:string" use="required" />
|
||||
<xs:attribute name="class" type="class" use="required"/>
|
||||
</xs:complexType>
|
||||
|
||||
<!-- Define a Cortex R4 co-processor -->
|
||||
<xs:complexType name="coprocessor">
|
||||
<xs:sequence>
|
||||
<xs:element name="block" minOccurs="1" maxOccurs="unbounded">
|
||||
<xs:complexType>
|
||||
<xs:choice maxOccurs="unbounded">
|
||||
<xs:element name="register" type="register" />
|
||||
<xs:element name="table" type="table" />
|
||||
</xs:choice>
|
||||
<xs:attribute name="name" type="xs:string" use="required" />
|
||||
</xs:complexType>
|
||||
</xs:element>
|
||||
</xs:sequence>
|
||||
<xs:attribute name="name" type="xs:string" use="required" />
|
||||
<xs:attribute name="id" type="class" use="required" />
|
||||
</xs:complexType>
|
||||
|
||||
<!-- Define a subsystem, top-level element for 'digits' registers -->
|
||||
<xs:element name="subsystem">
|
||||
<xs:complexType>
|
||||
<xs:sequence>
|
||||
<!-- containing a number of blocks -->
|
||||
<xs:element minOccurs="1" maxOccurs="unbounded" name="block" type="block" />
|
||||
</xs:sequence>
|
||||
<xs:attribute name="name" type="xs:string" use="required" />
|
||||
</xs:complexType>
|
||||
</xs:element>
|
||||
|
||||
<!-- Define a Cortex processor -->
|
||||
<xs:element name="processor">
|
||||
<xs:complexType>
|
||||
<xs:choice minOccurs="1" maxOccurs="unbounded">
|
||||
<xs:element name="coprocessor" type="coprocessor" />
|
||||
<xs:element name="memory" type="memory" />
|
||||
</xs:choice>
|
||||
<xs:attribute name="name" type="xs:string" use="required" />
|
||||
<xs:attribute name="comment" type="xs:string" use="required" />
|
||||
</xs:complexType>
|
||||
</xs:element>
|
||||
|
||||
</xs:schema>
|
||||
241
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/hardware/moredump/bt_registers.xml
vendored
Normal file
241
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/hardware/moredump/bt_registers.xml
vendored
Normal file
|
|
@ -0,0 +1,241 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!--
|
||||
(c) SCSC 2015-2016 autogenerated by moredump.py as part of 'drun prep'.
|
||||
Changes made to this file may cause incorrect behaviour and will be lost if it is regenerated.
|
||||
|
||||
XML file defining registers for bt subsystem moredump
|
||||
Chip hash: db95
|
||||
|
||||
|
||||
-->
|
||||
|
||||
<subsystem xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.samsung.com Registers.xsd"
|
||||
name="bt">
|
||||
<block name="bt_audio_pipe" comment="">
|
||||
<register addr="40330000" rw_flags="RW" width="4" name="AUDIO_PIPE_CONFIG" comment="Config register for audio pipe"/>
|
||||
<register addr="40330004" rw_flags="RW" width="4" name="AUDIO_PIPE_FREQ" comment="Config register for frequency select of audio pipe. Rising and falling halves are specified independently to allow more accurate selection of frequencies"/>
|
||||
</block>
|
||||
<block name="bt_bb_clkgen" comment="">
|
||||
<register addr="40300000" rw_flags="R" width="4" name="CLKGEN_SYSTEM_TIME" comment="The current microsecond system time."/>
|
||||
<register addr="40300004" rw_flags="RW" width="4" name="CLKGEN_ENABLES" comment="This register enables the core clocks on the chip. When a corresponding bit is set, the clock is enabled, regardless of any corresponding clock request"/>
|
||||
</block>
|
||||
<block name="bt_bb_modem" comment="">
|
||||
<register addr="40310000" rw_flags="RW" width="4" name="BT_DEBUG_MUX" comment="BT Debug Mux Selection."/>
|
||||
<register addr="40310004" rw_flags="RW" width="4" name="BT_WBREE_CONFIG" comment="Enables Wibree featues."/>
|
||||
<register addr="40310008" rw_flags="RW" width="4" name="BT_WBREE_CONFIG_EXT" comment="Extra Wibree controls."/>
|
||||
<register addr="4031000c" rw_flags="RW" width="4" name="BT_WBREE_CONFIG_EXTENDED" comment="Extended length Wibree controls."/>
|
||||
<register addr="40310010" rw_flags="RW" width="4" name="BT_WBREE_CONFIG_FUTURE" comment="Future Wibree controls."/>
|
||||
<register addr="40310014" rw_flags="RW" width="4" name="BT_WBREE_LEN_PARAMS" comment="Configure BLE length paramters"/>
|
||||
<register addr="40310018" rw_flags="RW" width="1" name="BT_WBREE_ADV_LEN_PARAMS" comment="Configure BLE length paramters"/>
|
||||
<register addr="4031001c" rw_flags="RW" width="4" name="BT_LEN_PARAMS" comment="Configure BR, EDR length paramters"/>
|
||||
<register addr="40310020" rw_flags="RW" width="2" name="BT_ANTPLUS_CONFIG" comment="Enables ANT+ featues."/>
|
||||
<register addr="40310024" rw_flags="RW" width="4" name="BT_LLR_TRIGGER_LSW" comment="LLR Access Code to transmit or receive LSW"/>
|
||||
<register addr="40310028" rw_flags="RW" width="4" name="BT_LLR_TRIGGER_MSW" comment="LLR Access Code to transmit or receive MSW"/>
|
||||
<register addr="4031002c" rw_flags="RW" width="4" name="BT_AES_ACL_CFG_1" comment="Enable BT AES and AES CCM modes on ACL packets"/>
|
||||
<register addr="40310030" rw_flags="RW" width="4" name="BT_AES_ACL_CFG_2" comment="Enable BT AES and AES CCM modes on ACL packets"/>
|
||||
<register addr="40310034" rw_flags="RW" width="4" name="BT_AES_ACL_CFG_3" comment="Enable BT AES and AES CCM modes on ACL packets"/>
|
||||
<register addr="40310038" rw_flags="RW" width="4" name="BT_AES_ACL23_CFG_1" comment="Enable BT AES and AES CCM modes on EDR ACL packets"/>
|
||||
<register addr="4031003c" rw_flags="RW" width="4" name="BT_AES_ACL23_CFG_2" comment="Enable BT AES and AES CCM modes on EDR ACL packets"/>
|
||||
<register addr="40310040" rw_flags="RW" width="4" name="BT_AES_ACL23_CFG_3" comment="Enable BT AES and AES CCM modes on EDR ACL packets"/>
|
||||
<register addr="40310044" rw_flags="RW" width="2" name="BT_AES_ACL23_CFG_4" comment="Enable BT AES and AES CCM modes on EDR ACL packets"/>
|
||||
<register addr="40310048" rw_flags="RW" width="4" name="BT_AES_ESCO_CFG" comment="Enable BT AES modes on ESCO packets"/>
|
||||
<register addr="4031004c" rw_flags="RW" width="4" name="BT_AES_ESCO23_CFG" comment="Enable BT AES modes on EDR ESCO packets"/>
|
||||
<register addr="40310050" rw_flags="RW" width="2" name="BT_AES_MISC41_CFG" comment="Miscellaneous BT AES config"/>
|
||||
<register addr="40310054" rw_flags="RW" width="4" name="BT_AES_MISC_CFG" comment="Miscellaneous BT AES config"/>
|
||||
<register addr="40310058" rw_flags="R" width="2" name="BT_AHB_STATUS" comment="AHB Status for BTLC"/>
|
||||
<register addr="4031005c" rw_flags="RW" width="4" name="BT_CONFIG_TX" comment="BT Config TX on Bitstream processing control"/>
|
||||
<register addr="40310060" rw_flags="RW" width="4" name="BT_TX_AUTO_START_TIME" comment="Automatically turn on the Tx Bitstream digital at this time when TX_AUTO_START_EN is set."/>
|
||||
<register addr="40310064" rw_flags="RW" width="4" name="BT_CONFIG_RX" comment="BT Config RX on Bitstream processing control"/>
|
||||
<register addr="40310068" rw_flags="RW" width="4" name="BT_RX_AUTO_START_TIME" comment="Automatically turn on the Rx Bitstream digital at this time when RX_AUTO_START_EN is set."/>
|
||||
<register addr="4031006c" rw_flags="RW" width="2" name="BT_CONFIG_COEX" comment="BT Config Coex Masking "/>
|
||||
<register addr="40310070" rw_flags="RW" width="1" name="BT_SPEEDY_RST" comment="BT reset on Bitstream processing control"/>
|
||||
<register addr="40310074" rw_flags="RW" width="4" name="BT_SPEEDY_S_MON_CTRL" comment="BT Speedy Slave Monitor Ctrl"/>
|
||||
<register addr="40310078" rw_flags="RW" width="4" name="BT_SPEEDY_M_MON_CTRL" comment="BT Speedy Master Monitor Ctrl"/>
|
||||
<register addr="4031007c" rw_flags="R" width="4" name="BT_SPEEDY_MON_STATUS" comment="BT Speedy Monitor Status"/>
|
||||
<register addr="40310080" rw_flags="RW" width="1" name="BT_TX_LINK_TYPE" comment=""/>
|
||||
<register addr="40310084" rw_flags="RW" width="2" name="BT_TX_PACKET_HEADER" comment="Bluetooth packet header data."/>
|
||||
<register addr="40310088" rw_flags="RW" width="2" name="BT_TX_PAYLOAD_HEADER" comment="Bluetooth payload header data."/>
|
||||
<register addr="4031008c" rw_flags="RW" width="4" name="BT_TX_VOICE_BUFFER" comment="Buffer Handle for voice data"/>
|
||||
<register addr="40310090" rw_flags="RW" width="4" name="BT_TX_DATA_BUFFER" comment="Buffer Handle for data"/>
|
||||
<register addr="40310094" rw_flags="RW" width="4" name="BT_TX_PACKET_CONFIG1" comment=""/>
|
||||
<register addr="40310098" rw_flags="RW" width="2" name="BT_TX_PACKET_CONFIG2" comment=""/>
|
||||
<register addr="4031009c" rw_flags="RW" width="2" name="BT_TX_ESCO_NUM_VOICE_BYTES" comment=""/>
|
||||
<register addr="403100a0" rw_flags="RW" width="2" name="BT_TX_CRC_L2CAP_SEED" comment=""/>
|
||||
<register addr="403100a4" rw_flags="R" width="2" name="BT_TX_CRC_L2CAP_STATE" comment=""/>
|
||||
<register addr="403100a8" rw_flags="R" width="1" name="BT_TX_STATE" comment=""/>
|
||||
<register addr="403100ac" rw_flags="R" width="1" name="BT_TX_EVENT_TYPE" comment="Status of last transmitted packet"/>
|
||||
<register addr="403100b0" rw_flags="R" width="1" name="BT_TX_EVENT_TYPE_BIT" comment="Latch of Status/Errors of last transmitted packet - each bit corresponds to event type value"/>
|
||||
<register addr="403100b4" rw_flags="RW" width="4" name="BT_TX_WBREE_ACCESS_ADDR" comment="Wibree transmit sync word"/>
|
||||
<register addr="403100b8" rw_flags="RW" width="2" name="BT_TX_WBREE_HDR_DATA" comment="Wibree tranamit header"/>
|
||||
<register addr="403100bc" rw_flags="RW" width="4" name="BT_TX_WBREE_AD_ADDR_LSW" comment="Wibree Advertiser address - transmitted by master in an advertising packet LSW"/>
|
||||
<register addr="403100c0" rw_flags="RW" width="2" name="BT_TX_WBREE_AD_ADDR_MSW" comment="Wibree Advertiser address - transmitted by master in an advertising packet MSW"/>
|
||||
<register addr="403100c4" rw_flags="RW" width="4" name="BT_TX_WBREE_CRC_SEED" comment="Seed value for Wibree CRC and ICV checksum"/>
|
||||
<register addr="403100c8" rw_flags="RW" width="4" name="BT_TX_WBREE_BUFFER" comment="Buffer handle for Wibree data"/>
|
||||
<register addr="403100cc" rw_flags="R" width="4" name="BT_TX_WBREE_CRC" comment="Transmitted Wibree CRC/ICV"/>
|
||||
<register addr="403100d0" rw_flags="RW" width="1" name="BT_TX_WBREE_DBG_CRC_CORRUPT" comment="Corrupt transmitted Wibree CRC/ICV"/>
|
||||
<register addr="403100d4" rw_flags="RW" width="1" name="BT_TX_ANTPLUS_LENGTH" comment="Length of ANT+ frame to transmit in bytes (including access code, etc.). For example, a standard fixed frame length should be 18."/>
|
||||
<register addr="403100d8" rw_flags="RW" width="4" name="BT_TX_PLDFIFO_CONFIG" comment="Tx Voice Fifo Configuration"/>
|
||||
<register addr="403100dc" rw_flags="R" width="1" name="BT_TX_PLDFIFO_STATUS" comment="Tx Voice Fifo Status"/>
|
||||
<register addr="403100e0" rw_flags="RW" width="2" name="BT_TX_LLR_CONFIG" comment="Transmit LLR config : "/>
|
||||
<register addr="403100e4" rw_flags="RW" width="2" name="BT_TX_LLR_REPETTIONS" comment="Number of times to repeat the LLR Trigger code"/>
|
||||
<register addr="403100e8" rw_flags="RW" width="1" name="BT_TX_WAIT_FOR_RFIC_DONE" comment="Wait for the TxDone acknowledgement to come back from the RFIC before firing the end of packet interrupt"/>
|
||||
<register addr="403100ec" rw_flags="RW" width="1" name="BT_RX_MEMBER_ADDRESS" comment="Receive member address"/>
|
||||
<register addr="403100f0" rw_flags="RW" width="2" name="BT_RX_LINK_TYPE" comment="Bluetooth link type"/>
|
||||
<register addr="403100f4" rw_flags="RW" width="4" name="BT_RX_FHS_BUFFER" comment="MMU FHS buffer handle"/>
|
||||
<register addr="403100f8" rw_flags="RW" width="4" name="BT_RX_LMP_BUFFER" comment="MMU LMP buffer handle"/>
|
||||
<register addr="403100fc" rw_flags="RW" width="4" name="BT_RX_VOICE_BUFFER" comment="MMU Voice buffer handle"/>
|
||||
<register addr="40310100" rw_flags="RW" width="4" name="BT_RX_DATA_BUFFER" comment="MMU Data buffer handle"/>
|
||||
<register addr="40310104" rw_flags="RW" width="2" name="BT_RX_FHS_BUF_SIZE" comment="MMU FHS buffer size "/>
|
||||
<register addr="40310108" rw_flags="RW" width="2" name="BT_RX_LMP_BUF_SIZE" comment="MMU LMP buffer size "/>
|
||||
<register addr="4031010c" rw_flags="RW" width="2" name="BT_RX_VOICE_BUF_SIZE" comment="MMU Voice buffer size"/>
|
||||
<register addr="40310110" rw_flags="RW" width="2" name="BT_RX_DATA_BUF_SIZE" comment="MMU Data buffer size"/>
|
||||
<register addr="40310114" rw_flags="RW" width="4" name="BT_RX_CONFIG" comment=""/>
|
||||
<register addr="40310118" rw_flags="RW" width="4" name="BT_RX_PACKET_CONFIG1" comment="Receive packet configuration - part1"/>
|
||||
<register addr="4031011c" rw_flags="RW" width="4" name="BT_RX_PACKET_CONFIG2" comment="Receive packet configuration - part2"/>
|
||||
<register addr="40310120" rw_flags="RW" width="2" name="BT_RX_ESCO_NUM_VOICE_BYTES" comment=""/>
|
||||
<register addr="40310124" rw_flags="RW" width="2" name="BT_RX_CRC_L2CAP_SEED" comment="L2CAP CRC seed"/>
|
||||
<register addr="40310128" rw_flags="RW" width="4" name="BT_RX_MLE_LEN" comment="Length increments for MLE escon length info"/>
|
||||
<register addr="4031012c" rw_flags="RW" width="1" name="BT_RX_MR_DEBUG_CONFIG" comment="Enable EDR debug - non zero"/>
|
||||
<register addr="40310130" rw_flags="R" width="1" name="BT_RX_STATE" comment="Debug register - current state of rx_control"/>
|
||||
<register addr="40310134" rw_flags="R" width="2" name="BT_RX_CRC_L2CAP_STATE" comment="Debug register - received L2CAP syndrome register"/>
|
||||
<register addr="40310138" rw_flags="R" width="1" name="BT_RX_FEC_NUM_CORR_HEADER_ERRORS" comment="FEC correctable header error count"/>
|
||||
<register addr="4031013c" rw_flags="R" width="2" name="BT_RX_PACKET_HEADER" comment="Received packet header"/>
|
||||
<register addr="40310140" rw_flags="R" width="2" name="BT_RX_PAYLOAD_HEADER" comment="Received payload header"/>
|
||||
<register addr="40310144" rw_flags="R" width="2" name="BT_RX_PAYLOAD_NUM_VOICE_BYTES" comment="Number of voice bytes received"/>
|
||||
<register addr="40310148" rw_flags="R" width="2" name="BT_RX_PAYLOAD_NUM_DATA_BYTES" comment="Number of data bytes received"/>
|
||||
<register addr="4031014c" rw_flags="R" width="1" name="BT_RX_FEC_NUM_CORR_ERRORS" comment="FEC correctable error count"/>
|
||||
<register addr="40310150" rw_flags="R" width="1" name="BT_RX_FEC_NUM_UNCORR_ERRORS" comment="FEC un-correctable error count"/>
|
||||
<register addr="40310154" rw_flags="RW" width="1" name="BT_RX_EVENT_CLEAR" comment="Write to clear receive event and interrupt without disabling the RX (need to toggle the bit)"/>
|
||||
<register addr="40310158" rw_flags="R" width="1" name="BT_RX_EVENT_TYPE" comment="Received event type"/>
|
||||
<register addr="4031015c" rw_flags="R" width="4" name="BT_RX_EVENT_TYPE_BIT" comment="Received event type - Latch of bits for each error/event type"/>
|
||||
<register addr="40310160" rw_flags="RW" width="4" name="BT_RX_WBREE_ACCESS_ADDR_BB" comment="Wibree Access Address. Sync word to seacrhg for in received packets"/>
|
||||
<register addr="40310164" rw_flags="R" width="2" name="BT_RX_WBREE_HDR_DATA" comment="Wibree received header"/>
|
||||
<register addr="40310168" rw_flags="R" width="4" name="BT_RX_WBREE_AD_ADDR_LSW" comment="Received Advertiser address - applicable to adverting packets only LSW"/>
|
||||
<register addr="4031016c" rw_flags="R" width="2" name="BT_RX_WBREE_AD_ADDR_MSW" comment="Received Advertiser address - applicable to adverting packets only MSW"/>
|
||||
<register addr="40310170" rw_flags="RW" width="4" name="BT_RX_WBREE_CRC_SEED" comment="Wibree CRC seed"/>
|
||||
<register addr="40310174" rw_flags="RW" width="4" name="BT_RX_WBREE_BUFFER" comment="Wibree receive buffer handle"/>
|
||||
<register addr="40310178" rw_flags="RW" width="2" name="BT_RX_WBREE_BUF_SIZE" comment="Wibree receive buffer size"/>
|
||||
<register addr="4031017c" rw_flags="R" width="4" name="BT_RX_WBREE_CRC" comment=""/>
|
||||
<register addr="40310180" rw_flags="RW" width="4" name="BT_RX_PLDFIFO_CONFIG" comment="Tx Voice Fifo Configuration"/>
|
||||
<register addr="40310184" rw_flags="R" width="1" name="BT_RX_PLDFIFO_STATUS" comment="Tx Voice Fifo Status"/>
|
||||
<register addr="40310188" rw_flags="RW" width="4" name="BT41_ZL_NONCE_CFG" comment="Set zero flag on Rcv Nonce for zero length packets received with following types:"/>
|
||||
<register addr="4031018c" rw_flags="R" width="4" name="AES_CCM_DATA" comment="Received encrypted MIC"/>
|
||||
<register addr="40310190" rw_flags="R" width="4" name="AES_EXP_CCM_DATA" comment="Expected encrypted MIC"/>
|
||||
<register addr="40310194" rw_flags="RW" width="1" name="BT41_SNIFF_MODE" comment="Prevent decryption of incoming data stream"/>
|
||||
<register addr="40310198" rw_flags="RW" width="1" name="BT_RX_ANTPLUS_LENGTH" comment="ANT plus packet length (for receive state machine)"/>
|
||||
<register addr="4031019c" rw_flags="RW" width="1" name="BT_RX_WAIT_FOR_RFIC_DONE" comment="Wait for the RxDone acknowledgement to come back from the RFIC before firing the end of packet interrupt"/>
|
||||
<register addr="403101a0" rw_flags="RW" width="2" name="BT_RX_MLE_ACL_PAYLOAD_ESTIMATE" comment="An estimate of the ACL payload length. This is used to ensure the MLE demodulator doesn't stop tracing back before we get the correct payload length across to the RFIC."/>
|
||||
<register addr="403101a4" rw_flags="RW" width="1" name="BT_RX_MLE_ACL_PAYLOAD_DELAY" comment="Number of clock cycles to delay sending the ACL payload to the RFIC. This is used to correct a potential timing issue (see SB-17048)"/>
|
||||
<register addr="403101a8" rw_flags="RW" width="4" name="BT_TXRX_MASTER_CLOCK" comment="Master clock seed for BT encryption LSFR"/>
|
||||
<register addr="403101ac" rw_flags="RW" width="4" name="BT_TXRX_MASTER_ADDRESS_LSW" comment="Master address seed for BT encryption LSFR"/>
|
||||
<register addr="403101b0" rw_flags="RW" width="2" name="BT_TXRX_MASTER_ADDRESS_MSW" comment="Master address seed for BT encryption LSFR"/>
|
||||
<register addr="403101b4" rw_flags="RW" width="1" name="BT_TXRX_HOP_MODE" comment="0: 79 hops, 1: 23 hops"/>
|
||||
<register addr="403101b8" rw_flags="RW" width="1" name="BT_TXRX_HOP_SEQ_TYPE" comment="Configure HOP sequence type"/>
|
||||
<register addr="403101bc" rw_flags="RW" width="4" name="BT_TXRX_HOP_UAP_LAP" comment="Upper and Lower BT address to determine frequecy hopping sequence"/>
|
||||
<register addr="403101c0" rw_flags="RW" width="4" name="BT_TXRX_HOP_CLOCK" comment="Master clock"/>
|
||||
<register addr="403101c4" rw_flags="RW" width="1" name="BT_TXRX_HOP_Y1" comment="Y1 from BT specification,"/>
|
||||
<register addr="403101c8" rw_flags="RW" width="1" name="BT_TXRX_HOP_K_SEL" comment="K from BT specification, 0: Koffset=24, 1: Koffset=8"/>
|
||||
<register addr="403101cc" rw_flags="RW" width="1" name="BT_TXRX_HOP_N" comment="Number of channels in adapted hop sequence"/>
|
||||
<register addr="403101d0" rw_flags="RW" width="1" name="BT_TXRX_HOP_F" comment="Adapted Hop sequence mapping (F from BT specification)"/>
|
||||
<register addr="403101d4" rw_flags="RW" width="4" name="BT_TXRX_ACCESS_CODE_LAP" comment="Lower 24 bits of BT address to generate access code - bit 24 causes an invertion of the generated access code."/>
|
||||
<register addr="403101d8" rw_flags="RW" width="1" name="BT_TXRX_WHITEN_ACTIVE" comment="Enable data whitening"/>
|
||||
<register addr="403101dc" rw_flags="RW" width="1" name="BT_TXRX_WHITEN_SEED" comment="Whitener seed for BT and Wibree packets"/>
|
||||
<register addr="403101e0" rw_flags="RW" width="1" name="BT_TXRX_ENCRYPT_ACTIVE" comment="Enable BT encryption"/>
|
||||
<register addr="403101e4" rw_flags="RW" width="4" name="BT_TXRX_ENCRYPT_KEY_0" comment="BT encryption key"/>
|
||||
<register addr="403101e8" rw_flags="RW" width="4" name="BT_TXRX_ENCRYPT_KEY_1" comment="BT encryption key"/>
|
||||
<register addr="403101ec" rw_flags="RW" width="4" name="BT_TXRX_ENCRYPT_KEY_2" comment="BT encryption key"/>
|
||||
<register addr="403101f0" rw_flags="RW" width="4" name="BT_TXRX_ENCRYPT_KEY_3" comment="BT encryption key"/>
|
||||
<register addr="403101f4" rw_flags="RW" width="1" name="BT_TXRX_HEC_CRC_SEED" comment="Transmit and receive Header Error CRC seed"/>
|
||||
<register addr="403101f8" rw_flags="R" width="2" name="BT_TXRX_HOP_INDEX_PRE_MOD" comment="Index of required hop before final modulus"/>
|
||||
<register addr="403101fc" rw_flags="R" width="1" name="BT_TXRX_HOP_INDEX" comment="Index of required hop (0 to 78 or 0 to 22)"/>
|
||||
<register addr="40310200" rw_flags="RW" width="1" name="BT_TXRX_AES_DBG_ADDR" comment="Select data to be read in AES_DBG_DATA"/>
|
||||
<register addr="40310204" rw_flags="R" width="2" name="BT_TXRX_AES_DBG_DATA" comment="P and K debug data"/>
|
||||
<register addr="40310208" rw_flags="RW" width="4" name="BT_TXRX_AES_KEY_0" comment="AES key"/>
|
||||
<register addr="4031020c" rw_flags="RW" width="4" name="BT_TXRX_AES_KEY_1" comment="AES key"/>
|
||||
<register addr="40310210" rw_flags="RW" width="4" name="BT_TXRX_AES_KEY_2" comment="AES key"/>
|
||||
<register addr="40310214" rw_flags="RW" width="4" name="BT_TXRX_AES_KEY_3" comment="AES key"/>
|
||||
<register addr="40310218" rw_flags="RW" width="4" name="BT_TXRX_AES_NONCE_0" comment="AES Nonce to be encrypted"/>
|
||||
<register addr="4031021c" rw_flags="RW" width="4" name="BT_TXRX_AES_NONCE_1" comment="AES Nonce to be encrypted"/>
|
||||
<register addr="40310220" rw_flags="RW" width="4" name="BT_TXRX_AES_NONCE_2" comment="AES Nonce to be encrypted"/>
|
||||
<register addr="40310224" rw_flags="RW" width="1" name="BT_TXRX_AES_NONCE_3" comment="AES Nonce to be encrypted"/>
|
||||
<register addr="40310228" rw_flags="RW" width="4" name="BT_TXRX_AES_NONCE2_0" comment="AES Additional Nonce to be encrypted"/>
|
||||
<register addr="4031022c" rw_flags="RW" width="4" name="BT_TXRX_AES_NONCE2_1" comment="AES Additional Nonce to be encrypted"/>
|
||||
<register addr="40310230" rw_flags="RW" width="4" name="BT_TXRX_AES_NONCE2_2" comment="AES Additional Nonce to be encrypted"/>
|
||||
<register addr="40310234" rw_flags="RW" width="1" name="BT_TXRX_AES_NONCE2_3" comment="AES Additional Nonce to be encrypted"/>
|
||||
<register addr="40310238" rw_flags="RW" width="2" name="BT_TXRX_AES_CCM_HDR_EN1" comment="Select which bits of header make up B0 key for AES-CCM"/>
|
||||
<register addr="4031023c" rw_flags="RW" width="2" name="BT_TXRX_AES_CCM_HDR_EN2" comment="Select which bits of header make up B0 key for AES-CCM"/>
|
||||
<register addr="40310240" rw_flags="RW" width="1" name="BT_TXRX_AES_CCM_FLAG_B0" comment="Aes-Ccm B0 flag"/>
|
||||
<register addr="40310244" rw_flags="RW" width="1" name="BT_TXRX_AES_CCM_FLAG_C0" comment="Aes-Ccm C0 flag"/>
|
||||
<register addr="40310248" rw_flags="RW" width="2" name="BT_TXRX_AES_CONFIG" comment="AES config CMM select / Nonce Select"/>
|
||||
<register addr="4031024c" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_KEY_0" comment="AES key for standalone engine"/>
|
||||
<register addr="40310250" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_KEY_1" comment="AES key for standalone engine"/>
|
||||
<register addr="40310254" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_KEY_2" comment="AES key for standalone engine"/>
|
||||
<register addr="40310258" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_KEY_3" comment="AES key for standalone engine"/>
|
||||
<register addr="4031025c" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_PLAINTEXT_0" comment="Plaintext for standalone AES engine"/>
|
||||
<register addr="40310260" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_PLAINTEXT_1" comment="Plaintext for standalone AES engine"/>
|
||||
<register addr="40310264" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_PLAINTEXT_2" comment="Plaintext for standalone AES engine"/>
|
||||
<register addr="40310268" rw_flags="RW" width="4" name="BT_TXRX_STANDALONE_AES_PLAINTEXT_3" comment="Plaintext for standalone AES engine"/>
|
||||
<register addr="4031026c" rw_flags="R" width="4" name="BT_TXRX_STANDALONE_AES_CRYPTTEXT_0" comment="Enciphered text for standalone AES engine"/>
|
||||
<register addr="40310270" rw_flags="R" width="4" name="BT_TXRX_STANDALONE_AES_CRYPTTEXT_1" comment="Enciphered text for standalone AES engine"/>
|
||||
<register addr="40310274" rw_flags="R" width="4" name="BT_TXRX_STANDALONE_AES_CRYPTTEXT_2" comment="Enciphered text for standalone AES engine"/>
|
||||
<register addr="40310278" rw_flags="R" width="4" name="BT_TXRX_STANDALONE_AES_CRYPTTEXT_3" comment="Enciphered text for standalone AES engine"/>
|
||||
<register addr="4031027c" rw_flags="RW" width="2" name="BT_TXRX_STANDALONE_AES_CONTROL" comment="Write to start standalone AES engine"/>
|
||||
<register addr="40310280" rw_flags="R" width="1" name="BT_TXRX_STANDALONE_AES_BUSY" comment="Indicates that the AES engine is currently busy. Goes high immediately when BT_TXRX_STANDALONE_AES_START is written. BT_TXRX_STANDALONE_AES_CRYPTTEXT is not valid until it goes low."/>
|
||||
<register addr="40310284" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_0" comment="Update the CVSD codec state 279:0"/>
|
||||
<register addr="40310288" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_1" comment=""/>
|
||||
<register addr="4031028c" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_2" comment=""/>
|
||||
<register addr="40310290" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_3" comment=""/>
|
||||
<register addr="40310294" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_4" comment=""/>
|
||||
<register addr="40310298" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_5" comment=""/>
|
||||
<register addr="4031029c" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_6" comment=""/>
|
||||
<register addr="403102a0" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_7" comment=""/>
|
||||
<register addr="403102a4" rw_flags="W" width="4" name="BT_CVSD_OLD_STATE_8" comment=""/>
|
||||
<register addr="403102a8" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_0" comment="Current voice codec state bits 279:0 "/>
|
||||
<register addr="403102ac" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_1" comment=""/>
|
||||
<register addr="403102b0" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_2" comment=""/>
|
||||
<register addr="403102b4" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_3" comment=""/>
|
||||
<register addr="403102b8" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_4" comment=""/>
|
||||
<register addr="403102bc" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_5" comment=""/>
|
||||
<register addr="403102c0" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_6" comment=""/>
|
||||
<register addr="403102c4" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_7" comment=""/>
|
||||
<register addr="403102c8" rw_flags="R" width="4" name="BT_CVSD_NEW_STATE_8" comment=""/>
|
||||
<register addr="403102cc" rw_flags="RW" width="2" name="BT_VOICE_SETTING" comment="SCO voice setting"/>
|
||||
</block>
|
||||
<block name="bt_dmah" comment="">
|
||||
<register addr="40100000" rw_flags="R" width="1" name="BTDMAH_CH0_STATUS" comment="Channel 0 - Status word"/>
|
||||
<register addr="40100004" rw_flags="RW" width="4" name="BTDMAH_CH0_SRC_ADDR" comment="Channel 0 - Base address of the source block"/>
|
||||
<register addr="40100008" rw_flags="RW" width="4" name="BTDMAH_CH0_DST_ADDR" comment="Channel 0 - Base address of the destination block"/>
|
||||
<register addr="4010000c" rw_flags="RW" width="4" name="BTDMAH_CH0_CONTROL" comment="Channel 0 - Control word"/>
|
||||
<register addr="40100010" rw_flags="R" width="1" name="BTDMAH_CH1_STATUS" comment="Channel 1 - Status word"/>
|
||||
<register addr="40100014" rw_flags="RW" width="4" name="BTDMAH_CH1_SRC_ADDR" comment="Channel 1 - Base address of the source block"/>
|
||||
<register addr="40100018" rw_flags="RW" width="4" name="BTDMAH_CH1_DST_ADDR" comment="Channel 1 - Base address of the destination block"/>
|
||||
<register addr="4010001c" rw_flags="RW" width="4" name="BTDMAH_CH1_CONTROL" comment="Channel 1 - Control word"/>
|
||||
<register addr="40100020" rw_flags="R" width="1" name="BTDMAH_CH2_STATUS" comment="Channel 2 - Status word"/>
|
||||
<register addr="40100024" rw_flags="RW" width="4" name="BTDMAH_CH2_SRC_ADDR" comment="Channel 2 - Base address of the source block"/>
|
||||
<register addr="40100028" rw_flags="R" width="2" name="BTDMAH_CH2_PTR" comment="Channel 2 - Current Buffer Pointer"/>
|
||||
<register addr="4010002c" rw_flags="RW" width="4" name="BTDMAH_CH2_CONTROL" comment="Channel 2 - Control word"/>
|
||||
<register addr="40100030" rw_flags="R" width="1" name="BTDMAH_CH3_STATUS" comment="Channel 3 - Status word"/>
|
||||
<register addr="40100034" rw_flags="RW" width="4" name="BTDMAH_CH3_DST_ADDR" comment="Channel 3 - Base address of the destination block"/>
|
||||
<register addr="40100038" rw_flags="R" width="2" name="BTDMAH_CH3_PTR" comment="Channel 3 - Current Buffer Pointer"/>
|
||||
<register addr="4010003c" rw_flags="RW" width="4" name="BTDMAH_CH3_CONTROL" comment="Channel 3 - Control word"/>
|
||||
</block>
|
||||
<block name="bt_pp_config" comment="">
|
||||
<register addr="40200000" rw_flags="R" width="4" name="BTPP_VERSION" comment="Processor platform version signature - actually a 32-bit value in ctime format"/>
|
||||
<register addr="40200004" rw_flags="RW" width="4" name="BTPP_POR_CONFIG" comment="Processor platform Configuration - NOTE Currently not in use."/>
|
||||
<register addr="40200008" rw_flags="RW" width="4" name="BTPP_RST_CONFIG" comment="Processor platform Configuration - NOTE Currently not in use."/>
|
||||
<register addr="4020000c" rw_flags="R" width="2" name="BT_PROC_STATUS" comment="Pio Status"/>
|
||||
<register addr="40200010" rw_flags="RW" width="2" name="BT_PROC_DRIVE" comment="Pio Drive"/>
|
||||
<register addr="40200014" rw_flags="RW" width="2" name="BT_PROC_DRIVE_EN" comment="Pio Drive En"/>
|
||||
<register addr="40200018" rw_flags="RW" width="1" name="BT_PROC_BLOCK_ACCESS_TO_R4" comment="Block the CPU access to R4 resources"/>
|
||||
<register addr="4020001c" rw_flags="RW" width="1" name="BTPP_IRQ2R4_SET" comment="Write 1 in the corresponding bit to raise an IRQ line to WLAN. Writing 0 has no any effect"/>
|
||||
<register addr="40200020" rw_flags="RW" width="1" name="BTPP_IRQ2R4_CLR" comment="Write 1 in the corresponding bit to clear an IRQ line to WLAN. Writing 0 has no any effect"/>
|
||||
<register addr="40200024" rw_flags="R" width="1" name="BTPP_IRQ2R4" comment="Status of the IRQ lines to WLAN"/>
|
||||
</block>
|
||||
<block name="speedy" comment="">
|
||||
<register addr="40320000" rw_flags="RW" width="4" name="SPEEDY_ADDR_CTRL" comment="Address and control flags for a Speedy transaction. Write this register to create an APB cycle on the remote chip (set up the write data first for write cycles). NOTE: usage of bit 19 (spare)"/>
|
||||
<register addr="40320004" rw_flags="RW" width="4" name="SPEEDY_WRITE_DATA" comment="Data to write to APB over Speedy"/>
|
||||
<register addr="40320008" rw_flags="R" width="4" name="SPEEDY_READ_DATA" comment="Data read back for APB over Speedy"/>
|
||||
<register addr="4032000c" rw_flags="R" width="1" name="SPEEDY_APB_STATUS" comment="Status of the current APB cycle"/>
|
||||
</block>
|
||||
</subsystem>
|
||||
313
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/hardware/moredump/cortexM4.xml
vendored
Normal file
313
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/hardware/moredump/cortexM4.xml
vendored
Normal file
|
|
@ -0,0 +1,313 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!--
|
||||
(c) SCSC 2015.
|
||||
|
||||
XML file defining Cortex M4 moredump
|
||||
-->
|
||||
|
||||
<processor xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||
xsi:schemaLocation="http://www.samsung.com Registers.xsd"
|
||||
name="Cortex M4" comment="Cortex M4 On-Chip Peripherals">
|
||||
<memory name="System Control" class="S">
|
||||
<register addr="e000e008" rw_flags="RW" width="4" name="ACTLR" comment="Auxiliary Control Register"/>
|
||||
<register addr="e000e010" rw_flags="RW" width="4" name="STCSR" comment="SysTick Control and Status Register"/>
|
||||
<register addr="e000e014" rw_flags="RW" width="4" name="STRVR" comment="SysTick Reload Value Register"/>
|
||||
<register addr="e000e018" rw_flags="RW" width="4" name="STCVR" comment="SysTick Current Value Register"/>
|
||||
<register addr="e000e01c" rw_flags="RW" width="4" name="STCR" comment="SysTick Calibration Value Register"/>
|
||||
<register addr="e000ed00" rw_flags="RW" width="4" name="CPUID" comment="CPU ID Base Register"/>
|
||||
<register addr="e000ed04" rw_flags="RW" width="4" name="ICSR" comment="Interrupt Control State Register"/>
|
||||
<register addr="e000ed08" rw_flags="RW" width="4" name="VTOR" comment="Vector Table Offset Register"/>
|
||||
<register addr="e000ed0c" rw_flags="RW" width="4" name="AIRCR" comment="Application Interrupt and Reset Control Register"/>
|
||||
<register addr="e000ed10" rw_flags="RW" width="4" name="SCR" comment="System Control Register"/>
|
||||
<register addr="e000ed14" rw_flags="RW" width="4" name="CCR" comment="Configuration Control Register"/>
|
||||
<register addr="e000ed18" rw_flags="RW" width="4" name="SHPR1" comment="System Handler Priority Register 1"/>
|
||||
<register addr="e000ed1c" rw_flags="RW" width="4" name="SHPR2" comment="System Handler Priority Register 2"/>
|
||||
<register addr="e000ed20" rw_flags="RW" width="4" name="SHPR3" comment="System Handler Priority Register 3"/>
|
||||
<register addr="e000ed24" rw_flags="RW" width="4" name="SHCSR" comment="System Handler Control and State Register"/>
|
||||
<register addr="e000ed28" rw_flags="RW" width="4" name="CFSR" comment="Configurable Fault Status Register"/>
|
||||
<register addr="e000ed2c" rw_flags="RW" width="4" name="HFSR" comment="Hard Fault Status Register"/>
|
||||
<register addr="e000ed30" rw_flags="RW" width="4" name="DFSR" comment="Debug Fault Status Register"/>
|
||||
<register addr="e000ed34" rw_flags="RW" width="4" name="MMFAR" comment="MemManage Fault Address Register"/>
|
||||
<register addr="e000ed38" rw_flags="RW" width="4" name="BFAR" comment="BusFault Address Register"/>
|
||||
<register addr="e000ed3c" rw_flags="RW" width="4" name="AFSR" comment="Auxiliary Fault Status Register"/>
|
||||
<register addr="e000ed88" rw_flags="RW" width="4" name="CPACR" comment="Coprocessor Access Control Register"/>
|
||||
<block name="Feature Registers">
|
||||
<register addr="e000ed40" rw_flags="RW" width="4" name="ID_PFR0" comment="Processor Feature Register 0"/>
|
||||
<register addr="e000ed44" rw_flags="RW" width="4" name="ID_PFR1" comment="Processor Feature Register 1"/>
|
||||
<register addr="e000ed48" rw_flags="RW" width="4" name="ID_DFR0" comment="Debug Feature Register 0"/>
|
||||
<register addr="e000ed4c" rw_flags="RW" width="4" name="ID_AFR0" comment="Auxiliary Feature Register 0"/>
|
||||
<register addr="e000ed50" rw_flags="RW" width="4" name="ID_MMFR0" comment="Memory Model Feature Register 0"/>
|
||||
<register addr="e000ed54" rw_flags="RW" width="4" name="ID_MMFR1" comment="Memory Model Feature Register 1"/>
|
||||
<register addr="e000ed58" rw_flags="RW" width="4" name="ID_MMFR2" comment="Memory Model Feature Register 2"/>
|
||||
<register addr="e000ed5c" rw_flags="RW" width="4" name="ID_MMFR3" comment="Memory Model Feature Register 3"/>
|
||||
<register addr="e000ed60" rw_flags="RW" width="4" name="ID_ISAR0" comment="Instruction Set Attribute Feature Register 0"/>
|
||||
<register addr="e000ed64" rw_flags="RW" width="4" name="ID_ISAR1" comment="Instruction Set Attribute Feature Register 1"/>
|
||||
<register addr="e000ed68" rw_flags="RW" width="4" name="ID_ISAR2" comment="Instruction Set Attribute Feature Register 2"/>
|
||||
<register addr="e000ed6c" rw_flags="RW" width="4" name="ID_ISAR3" comment="Instruction Set Attribute Feature Register 3"/>
|
||||
<register addr="e000ed70" rw_flags="RW" width="4" name="ID_ISAR4" comment="Instruction Set Attribute Feature Register 4"/>
|
||||
</block>
|
||||
<block name="Coresight identification Registers">
|
||||
<register addr="e000efd0" rw_flags="RW" width="4" name="PID4" comment="Peripheral Identification Register 4"/>
|
||||
<register addr="e000efe0" rw_flags="RW" width="4" name="PID0" comment="Peripheral ID0"/>
|
||||
<register addr="e000efe4" rw_flags="RW" width="4" name="PID1" comment="Peripheral ID1"/>
|
||||
<register addr="e000efe8" rw_flags="RW" width="4" name="PID2" comment="Peripheral ID2"/>
|
||||
<register addr="e000efec" rw_flags="RW" width="4" name="PID3" comment="Peripheral ID3"/>
|
||||
<register addr="e000eff0" rw_flags="RW" width="4" name="CID0" comment="Component ID0 (Preamble)"/>
|
||||
<register addr="e000eff4" rw_flags="RW" width="4" name="CID1" comment="Component ID1"/>
|
||||
<register addr="e000eff8" rw_flags="RW" width="4" name="CID2" comment="Component ID2"/>
|
||||
<register addr="e000effc" rw_flags="RW" width="4" name="CID3" comment="Component ID3"/>
|
||||
</block>
|
||||
</memory>
|
||||
|
||||
<memory name="Memory Protection Unit" class="S">
|
||||
<register addr="e000ed90" rw_flags="RW" width="4" name="MPUTYPE" comment="MPU Type Register"/>
|
||||
<register addr="e000ed94" rw_flags="RW" width="4" name="MPUCONTROL" comment="MPU Control Register"/>
|
||||
<table name="MPU Regions">
|
||||
<indexregister addr="e000ed98" rw_flags="RW" width="4" name="MPUREGION" comment="MPU Region Number Register">
|
||||
<countfrom addr="e000ed90" rw_flags="RW" width="4" name="MPUTYPE" comment="MPU type register" shift="8" mask="000F"/>
|
||||
</indexregister>
|
||||
<register addr="e000ed9c" rw_flags="RW" width="4" name="MBUREGBASEADD" comment="MPU Region Base Address Register"/>
|
||||
<register addr="e000eda0" rw_flags="RW" width="4" name="MPUREGATTRIB" comment="MPU Region Attribute and Size Register"/>
|
||||
</table>
|
||||
</memory>
|
||||
|
||||
<memory name="Nested Vectored Interrupt Controller" class="S">
|
||||
<register addr="e000e004" rw_flags="RW" width="4" name="ICTR" comment="Interrupt Controller Type Register"/>
|
||||
<block name="Interrupt Set/Clear Enable Registers">
|
||||
<register addr="e000e100" rw_flags="RW" width="4" name="IRQ0_31SET/CLREN" comment="Interrupt Set/Clear Enable Register"/>
|
||||
<register addr="e000e104" rw_flags="RW" width="4" name="IRQ32_63SET/CLREN" comment="Interrupt Set/Clear Enable Register"/>
|
||||
<register addr="e000e108" rw_flags="RW" width="4" name="IRQ64_95SET/CLREN" comment="Interrupt Set/Clear Enable Register"/>
|
||||
<register addr="e000e10c" rw_flags="RW" width="4" name="IRQ96_127SET/CLREN" comment="Interrupt Set/Clear Enable Register"/>
|
||||
<register addr="e000e110" rw_flags="RW" width="4" name="IRQ128_159SET/CLREN" comment="Interrupt Set/Clear Enable Register"/>
|
||||
<register addr="e000e114" rw_flags="RW" width="4" name="IRQ160_191SET/CLREN" comment="Interrupt Set/Clear Enable Register"/>
|
||||
<register addr="e000e118" rw_flags="RW" width="4" name="IRQ192_223SET/CLREN" comment="Interrupt Set/Cleared Enable Register"/>
|
||||
<register addr="e000e11c" rw_flags="RW" width="4" name="IRQ224_239SET/CLREN" comment="Interrupt Set/Clear Enable Register"/>
|
||||
</block>
|
||||
<block name="Interrupt Set/Clear Pending Registers">
|
||||
<register addr="e000e200" rw_flags="RW" width="4" name="IRQ0_31_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
<register addr="e000e204" rw_flags="RW" width="4" name="IRQ32_63_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
<register addr="e000e208" rw_flags="RW" width="4" name="IRQ64_95_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
<register addr="e000e20c" rw_flags="RW" width="4" name="IRQ96_127_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
<register addr="e000e210" rw_flags="RW" width="4" name="IRQ128_159_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
<register addr="e000e214" rw_flags="RW" width="4" name="IRQ160_191_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
<register addr="e000e218" rw_flags="RW" width="4" name="IRQ192_223_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
<register addr="e000e21c" rw_flags="RW" width="4" name="IRQ224_239_SET/CLRPEN" comment="Interrupt Set/Clear Pending Register"/>
|
||||
</block>
|
||||
<block name="Interrupt Active Bit Registers">
|
||||
<register addr="e000e300" rw_flags="RW" width="4" name="ACTIVE1" comment="Active Bit Register 1"/>
|
||||
<register addr="e000e304" rw_flags="RW" width="4" name="ACTIVE2" comment="Active Bit Register 2"/>
|
||||
<register addr="e000e308" rw_flags="RW" width="4" name="ACTIVE3" comment="Active Bit Register 3"/>
|
||||
<register addr="e000e30c" rw_flags="RW" width="4" name="ACTIVE4" comment="Active Bit Register 4"/>
|
||||
<register addr="e000e310" rw_flags="RW" width="4" name="ACTIVE5" comment="Active Bit Register 5"/>
|
||||
<register addr="e000e314" rw_flags="RW" width="4" name="ACTIVE6" comment="Active Bit Register 6"/>
|
||||
<register addr="e000e318" rw_flags="RW" width="4" name="ACTIVE7" comment="Active Bit Register 7"/>
|
||||
<register addr="e000e31c" rw_flags="RW" width="4" name="ACTIVE8" comment="Active Bit Register 8"/>
|
||||
</block>
|
||||
<block name="Interrupt Priority Registers">
|
||||
<register addr="e000e400" rw_flags="RW" width="4" name="INT0" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e404" rw_flags="RW" width="4" name="INT1" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e408" rw_flags="RW" width="4" name="INT2" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e40c" rw_flags="RW" width="4" name="INT3" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e410" rw_flags="RW" width="4" name="INT4" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e414" rw_flags="RW" width="4" name="INT5" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e418" rw_flags="RW" width="4" name="INT6" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e41c" rw_flags="RW" width="4" name="INT7" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e420" rw_flags="RW" width="4" name="INT8" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e424" rw_flags="RW" width="4" name="INT9" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e428" rw_flags="RW" width="4" name="INT10" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e42c" rw_flags="RW" width="4" name="INT11" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e430" rw_flags="RW" width="4" name="INT12" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e434" rw_flags="RW" width="4" name="INT13" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e438" rw_flags="RW" width="4" name="INT14" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e43c" rw_flags="RW" width="4" name="INT15" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e440" rw_flags="RW" width="4" name="INT16" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e444" rw_flags="RW" width="4" name="INT17" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e448" rw_flags="RW" width="4" name="INT18" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e44c" rw_flags="RW" width="4" name="INT19" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e450" rw_flags="RW" width="4" name="INT20" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e454" rw_flags="RW" width="4" name="INT21" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e458" rw_flags="RW" width="4" name="INT22" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e45c" rw_flags="RW" width="4" name="INT23" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e460" rw_flags="RW" width="4" name="INT24" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e464" rw_flags="RW" width="4" name="INT25" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e468" rw_flags="RW" width="4" name="INT26" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e46c" rw_flags="RW" width="4" name="INT27" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e470" rw_flags="RW" width="4" name="INT28" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e474" rw_flags="RW" width="4" name="INT29" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e478" rw_flags="RW" width="4" name="INT30" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e47c" rw_flags="RW" width="4" name="INT31" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e480" rw_flags="RW" width="4" name="INT32" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e484" rw_flags="RW" width="4" name="INT33" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e488" rw_flags="RW" width="4" name="INT34" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e48c" rw_flags="RW" width="4" name="INT35" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e490" rw_flags="RW" width="4" name="INT36" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e494" rw_flags="RW" width="4" name="INT37" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e498" rw_flags="RW" width="4" name="INT38" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e49c" rw_flags="RW" width="4" name="INT39" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4a0" rw_flags="RW" width="4" name="INT40" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4a4" rw_flags="RW" width="4" name="INT41" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4a8" rw_flags="RW" width="4" name="INT42" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4ac" rw_flags="RW" width="4" name="INT43" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4b0" rw_flags="RW" width="4" name="INT44" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4b4" rw_flags="RW" width="4" name="INT45" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4b8" rw_flags="RW" width="4" name="INT46" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4bc" rw_flags="RW" width="4" name="INT47" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4c0" rw_flags="RW" width="4" name="INT48" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4c4" rw_flags="RW" width="4" name="INT49" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4c8" rw_flags="RW" width="4" name="INT50" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4cc" rw_flags="RW" width="4" name="INT51" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4d0" rw_flags="RW" width="4" name="INT52" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4d4" rw_flags="RW" width="4" name="INT53" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4d8" rw_flags="RW" width="4" name="INT54" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4dc" rw_flags="RW" width="4" name="INT55" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4e0" rw_flags="RW" width="4" name="INT56" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4e4" rw_flags="RW" width="4" name="INT57" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4e8" rw_flags="RW" width="4" name="INT58" comment="Interrupt Priority Register"/>
|
||||
<register addr="e000e4ec" rw_flags="RW" width="4" name="INT59" comment="Interrupt Priority Register"/>
|
||||
</block>
|
||||
</memory>
|
||||
|
||||
<memory name="Floating-point Unit (FPU)" class="S">
|
||||
<register addr="e000ef34" rw_flags="RW" width="4" name="FPCCR" comment="Floating-Point Context Control Register"/>
|
||||
<register addr="e000ef38" rw_flags="RW" width="4" name="FPCAR" comment="Floating-Point Context Address Register"/>
|
||||
<register addr="e000ef3c" rw_flags="RW" width="4" name="FPDSCR" comment="Floating-Point Default Status Control Register"/>
|
||||
<register addr="e000ef40" rw_flags="RW" width="4" name="MVFR0" comment="Media and FP Feature Register 0"/>
|
||||
<register addr="e000ef44" rw_flags="RW" width="4" name="MVFR1" comment="Media and FP Feature Register 1"/>
|
||||
</memory>
|
||||
|
||||
<memory name="Debug" class="D">
|
||||
<register addr="e000edf0" rw_flags="RW" width="4" name="DHCSR" comment="Debug Halting Control and Status Register"/>
|
||||
<register addr="e000edf8" rw_flags="RW" width="4" name="DCRDR" comment="Debug Core Register Data Register"/>
|
||||
<register addr="e000edfc" rw_flags="RW" width="4" name="DEMCR" comment="Debug Exception and Monitor Control Register"/>
|
||||
<block name="Debug components">
|
||||
<register addr="e00ff000" rw_flags="RW" width="4" name="SCS" comment="System Control Space"/>
|
||||
<register addr="e00ff004" rw_flags="RW" width="4" name="DWT" comment="Data Watchpoint and Trace Unit"/>
|
||||
<register addr="e00ff008" rw_flags="RW" width="4" name="FPB" comment="Flash Patch and Breakpoint Unit"/>
|
||||
<register addr="e00ff00c" rw_flags="RW" width="4" name="ITM" comment="Instrumentation Trace Macrocell"/>
|
||||
<register addr="e00ff010" rw_flags="RW" width="4" name="TPIU" comment="Trace Port Interface Unit"/>
|
||||
<register addr="e00ff014" rw_flags="RW" width="4" name="ETM" comment="Embedded Trace Macrocell"/>
|
||||
<register addr="e00ff018" rw_flags="RW" width="4" name="EndMarker" comment="EndMarker"/>
|
||||
<register addr="e00fffcc" rw_flags="RW" width="4" name="SYSTEM_ACCESS" comment="SYSTEM_ACCESS"/>
|
||||
</block>
|
||||
<block name="Coresight identification Registers">
|
||||
<register addr="e00fffd0" rw_flags="RW" width="4" name="PID4" comment="Peripheral Identification Register 4"/>
|
||||
<register addr="e00fffe0" rw_flags="RW" width="4" name="PID0" comment="Peripheral ID0"/>
|
||||
<register addr="e00fffe4" rw_flags="RW" width="4" name="PID1" comment="Peripheral ID1"/>
|
||||
<register addr="e00fffe8" rw_flags="RW" width="4" name="PID2" comment="Peripheral ID2"/>
|
||||
<register addr="e00fffec" rw_flags="RW" width="4" name="PID3" comment="Peripheral ID3"/>
|
||||
<register addr="e00ffff0" rw_flags="RW" width="4" name="CID0" comment="Component ID0 (Preamble)"/>
|
||||
<register addr="e00ffff4" rw_flags="RW" width="4" name="CID1" comment="Component ID1"/>
|
||||
<register addr="e00ffff8" rw_flags="RW" width="4" name="CID2" comment="Component ID2"/>
|
||||
<register addr="e00ffffc" rw_flags="RW" width="4" name="CID3" comment="Component ID3"/>
|
||||
</block>
|
||||
<block name="Flash Patch and Breakpoint Unit (FPB)">
|
||||
<register addr="e0002000" rw_flags="RW" width="4" name="FP_CTRL" comment="Flash Patch Control Register"/>
|
||||
<register addr="e0002004" rw_flags="RW" width="4" name="FP_REMAP" comment="Flash Patch Remap Register"/>
|
||||
<register addr="e0002008" rw_flags="RW" width="4" name="FP_COMP0" comment="Flash Patch Comparator Register 0"/>
|
||||
<register addr="e000200c" rw_flags="RW" width="4" name="FP_COMP1" comment="Flash Patch Comparator Register 1"/>
|
||||
<register addr="e0002010" rw_flags="RW" width="4" name="FP_COMP2" comment="Flash Patch Comparator Register 2"/>
|
||||
<register addr="e0002014" rw_flags="RW" width="4" name="FP_COMP3" comment="Flash Patch Comparator Register 3"/>
|
||||
<register addr="e0002018" rw_flags="RW" width="4" name="FP_COMP4" comment="Flash Patch Comparator Register 4"/>
|
||||
<register addr="e000201c" rw_flags="RW" width="4" name="FP_COMP5" comment="Flash Patch Comparator Register 5"/>
|
||||
<register addr="e0002020" rw_flags="RW" width="4" name="FP_COMP6" comment="Flash Patch Comparator Register 6"/>
|
||||
<register addr="e0002024" rw_flags="RW" width="4" name="FP_COMP7" comment="Flash Patch Comparator Register 7"/>
|
||||
</block>
|
||||
<block name="Coresight Management Registers">
|
||||
<register addr="e0002fd0" rw_flags="RW" width="4" name="PID4" comment="Peripheral Identification Register 4"/>
|
||||
<register addr="e0002fe0" rw_flags="RW" width="4" name="PID0" comment="Peripheral ID0"/>
|
||||
<register addr="e0002fe4" rw_flags="RW" width="4" name="PID1" comment="Peripheral ID1"/>
|
||||
<register addr="e0002fe8" rw_flags="RW" width="4" name="PID2" comment="Peripheral ID2"/>
|
||||
<register addr="e0002fec" rw_flags="RW" width="4" name="PID3" comment="Peripheral ID3"/>
|
||||
<register addr="e0002f10" rw_flags="RW" width="4" name="CID0" comment="Component ID0 (Preamble)"/>
|
||||
<register addr="e0002f14" rw_flags="RW" width="4" name="CID1" comment="Component ID1"/>
|
||||
<register addr="e0002f18" rw_flags="RW" width="4" name="CID2" comment="Component ID2"/>
|
||||
<register addr="e0002f1c" rw_flags="RW" width="4" name="CID3" comment="Component ID3"/>
|
||||
</block>
|
||||
</memory>
|
||||
|
||||
<memory name="Data Watchpoint and Trace Unit" class="S">
|
||||
<register addr="e0001000" rw_flags="RW" width="4" name="DWT_CTRL" comment="DWT Control Register"/>
|
||||
<register addr="e0001004" rw_flags="RW" width="4" name="DWT_CYCCNT" comment="Cycle Count register"/>
|
||||
<register addr="e0001008" rw_flags="RW" width="4" name="DWT_CPICNT" comment="CPI Count register"/>
|
||||
<register addr="e000100c" rw_flags="RW" width="4" name="DWT_EXCCNT" comment="DWT Exception Overhead Count Register"/>
|
||||
<register addr="e0001010" rw_flags="RW" width="4" name="DWT_SLEEPCNT" comment="DWT Sleep Count Register"/>
|
||||
<register addr="e0001014" rw_flags="RW" width="4" name="DWT_LSUCNT" comment="DWT LSU Count Register"/>
|
||||
<register addr="e0001018" rw_flags="RW" width="4" name="DWT_FOLDCNT" comment="DWT Fold Count Register"/>
|
||||
<register addr="e000101c" rw_flags="RW" width="4" name="DWT_PCSR" comment="Program Counter Sample register"/>
|
||||
<register addr="e0001020" rw_flags="RW" width="4" name="DWT_COMP0" comment="DWT Comparator Register 0"/>
|
||||
<register addr="e0001024" rw_flags="RW" width="4" name="DWT_MASK0" comment="DWT Mask Registers 0"/>
|
||||
<register addr="e0001028" rw_flags="RW" width="4" name="DWT_FUNCTION0" comment="DWT Function Registers 0"/>
|
||||
<register addr="e0001030" rw_flags="RW" width="4" name="DWT_COMP1" comment="DWT Comparator Register 1"/>
|
||||
<register addr="e0001034" rw_flags="RW" width="4" name="DWT_MASK1" comment="DWT Mask Registers 1"/>
|
||||
<register addr="e0001038" rw_flags="RW" width="4" name="DWT_FUNCTION1" comment="DWT Function Registers 1"/>
|
||||
<register addr="e0001040" rw_flags="RW" width="4" name="DWT_COMP2" comment="DWT Comparator Register 2"/>
|
||||
<register addr="e0001044" rw_flags="RW" width="4" name="DWT_MASK2" comment="DWT Mask Registers 2"/>
|
||||
<register addr="e0001048" rw_flags="RW" width="4" name="DWT_FUNCTION2" comment="DWT Function Registers 2"/>
|
||||
<register addr="e0001050" rw_flags="RW" width="4" name="DWT_COMP3" comment="DWT Comparator Register 3"/>
|
||||
<register addr="e0001054" rw_flags="RW" width="4" name="DWT_MASK3" comment="DWT Mask Registers 3"/>
|
||||
<register addr="e0001058" rw_flags="RW" width="4" name="DWT_FUNCTION3" comment="DWT Function Registers 3"/>
|
||||
<block name="Coresight Management Registers">
|
||||
<register addr="e0001fd0" rw_flags="RW" width="4" name="PID4" comment="Peripheral Identification Register 4"/>
|
||||
<register addr="e0001fe0" rw_flags="RW" width="4" name="PID0" comment="Peripheral ID0"/>
|
||||
<register addr="e0001fe4" rw_flags="RW" width="4" name="PID1" comment="Peripheral ID1"/>
|
||||
<register addr="e0001fe8" rw_flags="RW" width="4" name="PID2" comment="Peripheral ID2"/>
|
||||
<register addr="e0001fec" rw_flags="RW" width="4" name="PID3" comment="Peripheral ID3"/>
|
||||
<register addr="e0001ff0" rw_flags="RW" width="4" name="CID0" comment="Component ID0 (Preamble)"/>
|
||||
<register addr="e0001ff4" rw_flags="RW" width="4" name="CID1" comment="Component ID1"/>
|
||||
<register addr="e0001ff8" rw_flags="RW" width="4" name="CID2" comment="Component ID2"/>
|
||||
<register addr="e0001ffc" rw_flags="RW" width="4" name="CID3" comment="Component ID3"/>
|
||||
</block>
|
||||
</memory>
|
||||
|
||||
<memory name="Instrumentation Trace Macrocell (ITM)" class="S">
|
||||
<block name="Stimulus Port registers 0-31">
|
||||
<register addr="e0000000" rw_flags="RW" width="4" name="SPR0" comment="Stimulus Port Register 0"/>
|
||||
<register addr="e0000004" rw_flags="RW" width="4" name="SPR1" comment="Stimulus Port Register 1"/>
|
||||
<register addr="e0000008" rw_flags="RW" width="4" name="SPR2" comment="Stimulus Port Register 2"/>
|
||||
<register addr="e000000c" rw_flags="RW" width="4" name="SPR3" comment="Stimulus Port Register 3"/>
|
||||
<register addr="e0000010" rw_flags="RW" width="4" name="SPR4" comment="Stimulus Port Register 4"/>
|
||||
<register addr="e0000014" rw_flags="RW" width="4" name="SPR5" comment="Stimulus Port Register 5"/>
|
||||
<register addr="e0000018" rw_flags="RW" width="4" name="SPR6" comment="Stimulus Port Register 6"/>
|
||||
<register addr="e000001c" rw_flags="RW" width="4" name="SPR7" comment="Stimulus Port Register 7"/>
|
||||
<register addr="e0000020" rw_flags="RW" width="4" name="SPR8" comment="Stimulus Port Register 8"/>
|
||||
<register addr="e0000024" rw_flags="RW" width="4" name="SPR9" comment="Stimulus Port Register 9"/>
|
||||
<register addr="e0000028" rw_flags="RW" width="4" name="SPR10" comment="Stimulus Port Register 10"/>
|
||||
<register addr="e000002c" rw_flags="RW" width="4" name="SPR11" comment="Stimulus Port Register 11"/>
|
||||
<register addr="e0000030" rw_flags="RW" width="4" name="SPR12" comment="Stimulus Port Register 12"/>
|
||||
<register addr="e0000034" rw_flags="RW" width="4" name="SPR13" comment="Stimulus Port Register 13"/>
|
||||
<register addr="e0000038" rw_flags="RW" width="4" name="SPR14" comment="Stimulus Port Register 14"/>
|
||||
<register addr="e000003c" rw_flags="RW" width="4" name="SPR15" comment="Stimulus Port Register 15"/>
|
||||
<register addr="e0000040" rw_flags="RW" width="4" name="SPR16" comment="Stimulus Port Register 16"/>
|
||||
<register addr="e0000044" rw_flags="RW" width="4" name="SPR17" comment="Stimulus Port Register 17"/>
|
||||
<register addr="e0000048" rw_flags="RW" width="4" name="SPR18" comment="Stimulus Port Register 18"/>
|
||||
<register addr="e000004c" rw_flags="RW" width="4" name="SPR19" comment="Stimulus Port Register 19"/>
|
||||
<register addr="e0000050" rw_flags="RW" width="4" name="SPR20" comment="Stimulus Port Register 20"/>
|
||||
<register addr="e0000054" rw_flags="RW" width="4" name="SPR21" comment="Stimulus Port Register 21"/>
|
||||
<register addr="e0000058" rw_flags="RW" width="4" name="SPR22" comment="Stimulus Port Register 22"/>
|
||||
<register addr="e000005c" rw_flags="RW" width="4" name="SPR23" comment="Stimulus Port Register 23"/>
|
||||
<register addr="e0000060" rw_flags="RW" width="4" name="SPR24" comment="Stimulus Port Register 24"/>
|
||||
<register addr="e0000064" rw_flags="RW" width="4" name="SPR25" comment="Stimulus Port Register 25"/>
|
||||
<register addr="e0000068" rw_flags="RW" width="4" name="SPR26" comment="Stimulus Port Register 26"/>
|
||||
<register addr="e000006c" rw_flags="RW" width="4" name="SPR27" comment="Stimulus Port Register 27"/>
|
||||
<register addr="e0000070" rw_flags="RW" width="4" name="SPR28" comment="Stimulus Port Register 28"/>
|
||||
<register addr="e0000074" rw_flags="RW" width="4" name="SPR29" comment="Stimulus Port Register 29"/>
|
||||
<register addr="e0000078" rw_flags="RW" width="4" name="SPR30" comment="Stimulus Port Register 30"/>
|
||||
<register addr="e000007c" rw_flags="RW" width="4" name="SPR31" comment="Stimulus Port Register 31"/>
|
||||
</block>
|
||||
<register addr="e0000e00" rw_flags="RW" width="4" name="ITM_TER" comment="ITM Trace Enable Register"/>
|
||||
<register addr="e0000e40" rw_flags="RW" width="4" name="ITM_TPR" comment="Trace Privilege Register"/>
|
||||
<register addr="e0000e80" rw_flags="RW" width="4" name="ITM_TCR" comment="Trace Control Register"/>
|
||||
<block name="Coresight identification Registers">
|
||||
<register addr="e0000fd0" rw_flags="RW" width="4" name="PID4" comment="Peripheral Identification Register 4"/>
|
||||
<register addr="e0000fe0" rw_flags="RW" width="4" name="PID0" comment="Peripheral ID0"/>
|
||||
<register addr="e0000fe4" rw_flags="RW" width="4" name="PID1" comment="Peripheral ID1"/>
|
||||
<register addr="e0000fe8" rw_flags="RW" width="4" name="PID2" comment="Peripheral ID2"/>
|
||||
<register addr="e0000fec" rw_flags="RW" width="4" name="PID3" comment="Peripheral ID3"/>
|
||||
<register addr="e0000ff0" rw_flags="RW" width="4" name="CID0" comment="Component ID0 (Preamble)"/>
|
||||
<register addr="e0000ff4" rw_flags="RW" width="4" name="CID1" comment="Component ID1"/>
|
||||
<register addr="e0000ff8" rw_flags="RW" width="4" name="CID2" comment="Component ID2"/>
|
||||
<register addr="e0000ffc" rw_flags="RW" width="4" name="CID3" comment="Component ID3"/>
|
||||
</block>
|
||||
</memory>
|
||||
</processor>
|
||||
278
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/hardware/moredump/cortexR4.xml
vendored
Normal file
278
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/hardware/moredump/cortexR4.xml
vendored
Normal file
|
|
@ -0,0 +1,278 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!--
|
||||
(c) SCSC 2015.
|
||||
|
||||
XML file defining Cortex R4 moredump
|
||||
-->
|
||||
|
||||
<processor xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||
xsi:schemaLocation="http://www.samsung.com Registers.xsd"
|
||||
name="Cortex R4" comment="Cortex R4 On-Chip Peripherals">
|
||||
<coprocessor name="System Control" id="C15">
|
||||
<block name="ID Registers">
|
||||
<register addr="0000" rw_flags="RW" width="4" name="MIDR" comment="Main ID Register"/>
|
||||
<register addr="0100" rw_flags="RW" width="4" name="CTR" comment="Cache Type Register"/>
|
||||
<register addr="0200" rw_flags="RW" width="4" name="TCMTR" comment="Tightly-Coupled Memory Status Register"/>
|
||||
<register addr="0400" rw_flags="RW" width="4" name="MPUIR" comment="MPU type register"/>
|
||||
<register addr="0500" rw_flags="RW" width="4" name="MPIDR" comment="Multiprocessor Affinity Register"/>
|
||||
<register addr="0410" rw_flags="RW" width="4" name="MMFR0" comment="Memory Model Feature Register 0"/>
|
||||
<register addr="0510" rw_flags="RW" width="4" name="MMFR1" comment="Memory Model Feature Register 1"/>
|
||||
<register addr="0610" rw_flags="RW" width="4" name="MMFR2" comment="Memory Model Feature Register 2"/>
|
||||
<register addr="0710" rw_flags="RW" width="4" name="MMFR3" comment="Memory Model Feature Register 3"/>
|
||||
<register addr="0020" rw_flags="RW" width="4" name="ISAR0" comment="Instruction Set Attribute Register 0"/>
|
||||
<register addr="0120" rw_flags="RW" width="4" name="ISAR1" comment="Instruction Set Attribute Register 1"/>
|
||||
<register addr="0220" rw_flags="RW" width="4" name="ISAR2" comment="Instruction Set Attribute Register 2"/>
|
||||
<register addr="0320" rw_flags="RW" width="4" name="ISAR3" comment="Instruction Set Attribute Register 3"/>
|
||||
<register addr="0420" rw_flags="RW" width="4" name="ISAR4" comment="Instruction Set Attribute Register 4"/>
|
||||
<register addr="0520" rw_flags="RW" width="4" name="ISAR5" comment="Instruction Set Attribute Registers 5 (Reserved)"/>
|
||||
<register addr="0620" rw_flags="RW" width="4" name="ISAR6" comment="Instruction Set Attribute Registers 6 (Reserved)"/>
|
||||
<register addr="0720" rw_flags="RW" width="4" name="ISAR7" comment="Instruction Set Attribute Registers 7 (Reserved)"/>
|
||||
<register addr="0010" rw_flags="RW" width="4" name="PFR0" comment="Processor Feature Register 0"/>
|
||||
<register addr="0110" rw_flags="RW" width="4" name="PFR1" comment="Processor Feature Register 1"/>
|
||||
<register addr="0210" rw_flags="RW" width="4" name="DFR0" comment="Debug Feature Register 0"/>
|
||||
<register addr="0310" rw_flags="RW" width="4" name="AFR0" comment="Auxiliary Feature Register 0"/>
|
||||
</block>
|
||||
|
||||
<block name="System Control and Configuration">
|
||||
<register addr="0101" rw_flags="RW" width="4" name="ACTLR" comment="Auxiliary Control Register"/>
|
||||
<register addr="0201" rw_flags="RW" width="4" name="CPACR" comment="Coprocessor Access Control Register"/>
|
||||
<register addr="000b" rw_flags="RW" width="4" name="SPC" comment="Slave Port Control"/>
|
||||
</block>
|
||||
|
||||
<block name="MPU Control and Configuration">
|
||||
<register addr="0005" rw_flags="RW" width="4" name="DFSR" comment="Data Fault Status Register"/>
|
||||
<register addr="0006" rw_flags="RW" width="4" name="DFAR" comment="Data Fault Address Register"/>
|
||||
<register addr="0105" rw_flags="RW" width="4" name="IFSR" comment="Instruction Fault Status Register"/>
|
||||
<register addr="0206" rw_flags="RW" width="4" name="IFAR" comment="Instruction Fault Address Register"/>
|
||||
<register addr="0015" rw_flags="RW" width="4" name="ADFSR" comment="Auxiliary Data Fault Status Register"/>
|
||||
<register addr="0115" rw_flags="RW" width="4" name="AIFSR" comment="Auxiliary Instruction Fault Status Register"/>
|
||||
<register addr="010d" rw_flags="RW" width="4" name="CONTEXTIDR" comment="Context ID Register"/>
|
||||
<table name="MPU Regions">
|
||||
<indexregister addr="0026" rw_flags="RW" width="4" name="MRNR" comment="Memory Region Number Register">
|
||||
<countfrom addr="0400" rw_flags="RW" width="4" name="MPUIR" comment="MPU type register" shift="8" mask="000F"/>
|
||||
</indexregister>
|
||||
<register addr="0016" rw_flags="RW" width="4" name="RBAR" comment="Region Base Address Register"/>
|
||||
<register addr="0216" rw_flags="RW" width="4" name="RSER" comment="Region Size and Enable Register"/>
|
||||
<register addr="0416" rw_flags="RW" width="4" name="RACR" comment="Region Access Control Register"/>
|
||||
</table>
|
||||
<!-- Must restore this after MPU -->
|
||||
<register addr="0001" rw_flags="RW" width="4" name="SCTLR" comment="Control Register"/>
|
||||
</block>
|
||||
|
||||
<block name="Cache Control and Configuration">
|
||||
<register addr="1100" rw_flags="RW" width="4" name="CLIDR" comment="Cache Level ID Register"/>
|
||||
<register addr="1000" rw_flags="RW" width="4" name="CCSIDR" comment="Current Cache Size ID Register"/>
|
||||
<register addr="2000" rw_flags="RW" width="4" name="CSSELR" comment="Cache Size Selection Register"/>
|
||||
<register addr="003f" rw_flags="RW" width="4" name="CFLR" comment="Correctable Fault Location Register"/>
|
||||
</block>
|
||||
|
||||
<block name="TCM Control and Configuration">
|
||||
<register addr="0019" rw_flags="RW" width="4" name="BTCM" comment="Data TCM Region Register"/>
|
||||
<register addr="0119" rw_flags="RW" width="4" name="ATCM" comment="Instruction TCM Region Register"/>
|
||||
<register addr="0029" rw_flags="RW" width="4" name="TCMSEL" comment="TCM Selection Register"/>
|
||||
</block>
|
||||
|
||||
<block name="System Performance Monitor">
|
||||
<register addr="00C9" rw_flags="RW" width="4" name="PMNC" comment="Performance Monitor Control Register"/>
|
||||
<register addr="01C9" rw_flags="RW" width="4" name="CNTENS" comment="Count Enable Set Register"/>
|
||||
<register addr="02C9" rw_flags="RW" width="4" name="CNTENC" comment="Count Enable Clear Register"/>
|
||||
<register addr="03C9" rw_flags="RW" width="4" name="FLAG" comment="Overflow Flag Status Register"/>
|
||||
<register addr="00D9" rw_flags="RW" width="4" name="CCNT" comment="Cycle Count Register"/>
|
||||
<register addr="00E9" rw_flags="RW" width="4" name="USEREN" comment="User Enable Register"/>
|
||||
<register addr="01E9" rw_flags="RW" width="4" name="INTENS" comment="Interrupt Enable Set Register"/>
|
||||
<register addr="02E9" rw_flags="RW" width="4" name="INTENC" comment="Interrupt Enable Clear Register"/>
|
||||
<table name="Performance Counters">
|
||||
<indexregister addr="05C9" rw_flags="RW" width="4" name="PMNXSEL" comment="Performance Counter Selection Register">
|
||||
<count value="3"/>
|
||||
</indexregister>
|
||||
<register addr="01d9" rw_flags="RW" width="4" name="ESR" comment="Event Selection Register"/>
|
||||
<register addr="02d9" rw_flags="RW" width="4" name="PMCR" comment="Performance Monitor Count Register"/>
|
||||
</table>
|
||||
</block>
|
||||
</coprocessor>
|
||||
|
||||
<coprocessor name="Debug Registers" id="C14">
|
||||
<block name="Processor Identifier Registers">
|
||||
<register addr="0340" rw_flags="RW" width="4" name="CPUID" comment="Main ID Register"/>
|
||||
<register addr="0341" rw_flags="RW" width="4" name="CACHETYPE" comment="Cache Type Register"/>
|
||||
<register addr="0343" rw_flags="RW" width="4" name="TLBTYPE" comment="TLB Type Register"/>
|
||||
<register addr="0348" rw_flags="RW" width="4" name="ID_PFR0" comment="Processor Feature Register 0"/>
|
||||
<register addr="0349" rw_flags="RW" width="4" name="ID_PFR1" comment="Processor Feature Register 1"/>
|
||||
<register addr="034a" rw_flags="RW" width="4" name="ID_DFR0" comment="Debug Feature Register 0"/>
|
||||
<register addr="034b" rw_flags="RW" width="4" name="ID_AFR0" comment="Auxiliary Feature Register 0"/>
|
||||
<register addr="034c" rw_flags="RW" width="4" name="ID_MMFR0" comment="Processor Feature Register 0"/>
|
||||
<register addr="034d" rw_flags="RW" width="4" name="ID_MMFR1" comment="Processor Feature Register 1"/>
|
||||
<register addr="034e" rw_flags="RW" width="4" name="ID_MMFR2" comment="Processor Feature Register 2"/>
|
||||
<register addr="034f" rw_flags="RW" width="4" name="ID_MMFR3" comment="Processor Feature Register 3"/>
|
||||
<register addr="0350" rw_flags="RW" width="4" name="ID_ISAR0" comment="ISA Feature Register 0"/>
|
||||
<register addr="0351" rw_flags="RW" width="4" name="ID_ISAR1" comment="ISA Feature Register 1"/>
|
||||
<register addr="0352" rw_flags="RW" width="4" name="ID_ISAR2" comment="ISA Feature Register 2"/>
|
||||
<register addr="0353" rw_flags="RW" width="4" name="ID_ISAR3" comment="ISA Feature Register 3"/>
|
||||
<register addr="0354" rw_flags="RW" width="4" name="ID_ISAR4" comment="ISA Feature Register 4"/>
|
||||
<register addr="0355" rw_flags="RW" width="4" name="ID_ISAR5" comment="ISA Feature Register 5"/>
|
||||
</block>
|
||||
|
||||
<block name="Coresight Management Registers">
|
||||
<register addr="03bf" rw_flags="RW" width="4" name="DBGITMISCIN" comment="Integration Test Input Register"/>
|
||||
<register addr="03c0" rw_flags="RW" width="4" name="DBGITCTRL" comment="Integration Mode Control Register"/>
|
||||
<register addr="03e8" rw_flags="RW" width="4" name="DBGCLAIMSET" comment="Claim Tag Set Register"/>
|
||||
<register addr="03e9" rw_flags="RW" width="4" name="DBGCLAIMCLR" comment="Claim Tag Clear Register"/>
|
||||
<register addr="03ed" rw_flags="RW" width="4" name="DBGLSR" comment="Lock Status Register"/>
|
||||
<register addr="03ee" rw_flags="RW" width="4" name="DBGAUTHSTATUS" comment="Authentication Status Register"/>
|
||||
<register addr="03f2" rw_flags="RW" width="4" name="DBGDEVID" comment="Device Identifier (RESERVED)"/>
|
||||
<register addr="03f3" rw_flags="RW" width="4" name="DBGDEVTYPE" comment="Device Type"/>
|
||||
<register addr="03f8" rw_flags="RW" width="4" name="PID0" comment="Peripheral ID0"/>
|
||||
<register addr="03f9" rw_flags="RW" width="4" name="PID1" comment="Peripheral ID1"/>
|
||||
<register addr="03fa" rw_flags="RW" width="4" name="PID2" comment="Peripheral ID2"/>
|
||||
<register addr="03fb" rw_flags="RW" width="4" name="PID3" comment="Peripheral ID3"/>
|
||||
<register addr="03f4" rw_flags="RW" width="4" name="PID4" comment="Peripheral ID4"/>
|
||||
<register addr="03fc" rw_flags="RW" width="4" name="COMPONENTID0" comment="Component ID0"/>
|
||||
<register addr="03fd" rw_flags="RW" width="4" name="COMPONENTID1" comment="Component ID1"/>
|
||||
<register addr="03fe" rw_flags="RW" width="4" name="COMPONENTID2" comment="Component ID2"/>
|
||||
<register addr="03ff" rw_flags="RW" width="4" name="COMPONENTID3" comment="Component ID3"/>
|
||||
<register addr="0000" rw_flags="RW" width="4" name="DBGDIDR" comment="Debug ID Register"/>
|
||||
<register addr="0022" rw_flags="RW" width="4" name="DBGDSCR" comment="Debug Status and Control Register"/>
|
||||
<register addr="0007" rw_flags="RW" width="4" name="DBGVCR" comment="Vector Catch Register"/>
|
||||
<register addr="0023" rw_flags="RW" width="4" name="DBGDTRTX" comment="Host -> Target Data Transfer Register"/>
|
||||
<register addr="000a" rw_flags="RW" width="4" name="DBGDSCCR" comment="Debug State Cache Control Register"/>
|
||||
<register addr="00c1" rw_flags="RW" width="4" name="DBGOSLSR" comment="Operating System Lock Status Register"/>
|
||||
<register addr="00c4" rw_flags="RW" width="4" name="DBGPRCR" comment="Device Power-Down and Reset Control Register"/>
|
||||
</block>
|
||||
|
||||
<block name="Breakpoint Registers">
|
||||
<register addr="0040" rw_flags="RW" width="4" name="DBGBVR0" comment="Breakpoint Value Register 0"/>
|
||||
<register addr="0050" rw_flags="RW" width="4" name="DBGBCR0" comment="Breakpoint Control Register 0"/>
|
||||
<register addr="0041" rw_flags="RW" width="4" name="DBGBVR1" comment="Breakpoint Value Register 1"/>
|
||||
<register addr="0051" rw_flags="RW" width="4" name="DBGBCR1" comment="Breakpoint Control Register 1"/>
|
||||
<register addr="0042" rw_flags="RW" width="4" name="DBGBVR2" comment="Breakpoint Value Register 2"/>
|
||||
<register addr="0052" rw_flags="RW" width="4" name="DBGBCR2" comment="Breakpoint Control Register 2"/>
|
||||
<register addr="0043" rw_flags="RW" width="4" name="DBGBVR3" comment="Breakpoint Value Register 3"/>
|
||||
<register addr="0053" rw_flags="RW" width="4" name="DBGBCR3" comment="Breakpoint Control Register 3"/>
|
||||
<register addr="0044" rw_flags="RW" width="4" name="DBGBVR4" comment="Breakpoint Value Register 4"/>
|
||||
<register addr="0054" rw_flags="RW" width="4" name="DBGBCR4" comment="Breakpoint Control Register 4"/>
|
||||
<register addr="0045" rw_flags="RW" width="4" name="DBGBVR5" comment="Breakpoint Value Register 5"/>
|
||||
<register addr="0055" rw_flags="RW" width="4" name="DBGBCR5" comment="Breakpoint Control Register 5"/>
|
||||
<register addr="0046" rw_flags="RW" width="4" name="DBGBVR6" comment="Breakpoint Value Register 6"/>
|
||||
<register addr="0056" rw_flags="RW" width="4" name="DBGBCR6" comment="Breakpoint Control Register 6"/>
|
||||
<register addr="0047" rw_flags="RW" width="4" name="DBGBVR7" comment="Breakpoint Value Register 7"/>
|
||||
<register addr="0057" rw_flags="RW" width="4" name="DBGBCR7" comment="Breakpoint Control Register 7"/>
|
||||
</block>
|
||||
|
||||
<block name="Watchpoint Control Registers">
|
||||
<register addr="0060" rw_flags="RW" width="4" name="DBGWVR0" comment="Watchpoint Value Register 0"/>
|
||||
<register addr="0070" rw_flags="RW" width="4" name="DBGWCR0" comment="Watchpoint Control Register 0"/>
|
||||
<register addr="0061" rw_flags="RW" width="4" name="DBGWVR1" comment="Watchpoint Value Register 1"/>
|
||||
<register addr="0071" rw_flags="RW" width="4" name="DBGWCR1" comment="Watchpoint Control Register 1"/>
|
||||
<register addr="0062" rw_flags="RW" width="4" name="DBGWVR2" comment="Watchpoint Value Register 2"/>
|
||||
<register addr="0072" rw_flags="RW" width="4" name="DBGWCR2" comment="Watchpoint Control Register 2"/>
|
||||
<register addr="0063" rw_flags="RW" width="4" name="DBGWVR3" comment="Watchpoint Value Register 3"/>
|
||||
<register addr="0073" rw_flags="RW" width="4" name="DBGWCR3" comment="Watchpoint Control Register 3"/>
|
||||
<register addr="0064" rw_flags="RW" width="4" name="DBGWVR4" comment="Watchpoint Value Register 4"/>
|
||||
<register addr="0074" rw_flags="RW" width="4" name="DBGWCR4" comment="Watchpoint Control Register 4"/>
|
||||
<register addr="0065" rw_flags="RW" width="4" name="DBGWVR5" comment="Watchpoint Value Register 5"/>
|
||||
<register addr="0075" rw_flags="RW" width="4" name="DBGWCR5" comment="Watchpoint Control Register 5"/>
|
||||
<register addr="0066" rw_flags="RW" width="4" name="DBGWVR6" comment="Watchpoint Value Register 6"/>
|
||||
<register addr="0076" rw_flags="RW" width="4" name="DBGWCR6" comment="Watchpoint Control Register 6"/>
|
||||
<register addr="0067" rw_flags="RW" width="4" name="DBGWVR7" comment="Watchpoint Value Register 7"/>
|
||||
<register addr="0077" rw_flags="RW" width="4" name="DBGWCR7" comment="Watchpoint Control Register 7"/>
|
||||
<register addr="0006" rw_flags="RW" width="4" name="DBGWFAR" comment="Watchpoint Fault Address Register"/>
|
||||
</block>
|
||||
</coprocessor>
|
||||
|
||||
<memory name="Vectored interrupt controller" class="D">
|
||||
<!-- From ARM PrimeCell VectoredInterrupt Controller (PL192) TRM -->
|
||||
<block name ="Common">
|
||||
<register addr="dfff0000" rw_flags="R" width="4" name="VICIRQSTATUS" comment="IRQ Status Register"/>
|
||||
<register addr="dfff0004" rw_flags="R" width="4" name="VICFIQSTATUS" comment="FIQ Status Register"/>
|
||||
<register addr="dfff0008" rw_flags="R" width="4" name="VICRAWINTR" comment="Raw Interrupt Status Register"/>
|
||||
<register addr="dfff000C" rw_flags="RW" width="4" name="VICINTSELECT" comment="Interrupt Select Register"/>
|
||||
<register addr="dfff0010" rw_flags="RW" width="4" name="VICINTENABLE" comment="Interrupt Enable Register"/>
|
||||
<register addr="dfff0014" rw_flags="W" width="4" name="VICINTENCLEAR" comment="Interrupt Enable Clear Register"/>
|
||||
<register addr="dfff0018" rw_flags="RW" width="4" name="VICSOFTINT" comment="Software Interrupt Register"/>
|
||||
<register addr="dfff001C" rw_flags="W" width="4" name="VICSOFTINTCLEAR" comment="Software Interrupt Clear Register"/>
|
||||
<register addr="dfff0020" rw_flags="RW" width="1" name="VICPROTECTION" comment="Protection Enable Register"/>
|
||||
<register addr="dfff0024" rw_flags="RW" width="2" name="VICSWPRIORITY MASK" comment="Software Priority Mask Register"/>
|
||||
<register addr="dfff0028" rw_flags="RW" width="1" name="VICPRIORITYDAISY" comment="Vector Priority Register for Daisy Chain"/>
|
||||
</block>
|
||||
<block name ="Vector addresses">
|
||||
<register addr="dfff0100" rw_flags="RW" width="4" name="VICVECTADDR0" comment="Vector Address 0 Register"/>
|
||||
<register addr="dfff0104" rw_flags="RW" width="4" name="VICVECTADDR1" comment="Vector Address 1 Register"/>
|
||||
<register addr="dfff0108" rw_flags="RW" width="4" name="VICVECTADDR2" comment="Vector Address 2 Register"/>
|
||||
<register addr="dfff010C" rw_flags="RW" width="4" name="VICVECTADDR3" comment="Vector Address 3 Register"/>
|
||||
<register addr="dfff0110" rw_flags="RW" width="4" name="VICVECTADDR4" comment="Vector Address 4 Register"/>
|
||||
<register addr="dfff0114" rw_flags="RW" width="4" name="VICVECTADDR5" comment="Vector Address 5 Register"/>
|
||||
<register addr="dfff0118" rw_flags="RW" width="4" name="VICVECTADDR6" comment="Vector Address 6 Register"/>
|
||||
<register addr="dfff011C" rw_flags="RW" width="4" name="VICVECTADDR7" comment="Vector Address 7 Register"/>
|
||||
<register addr="dfff0120" rw_flags="RW" width="4" name="VICVECTADDR8" comment="Vector Address 8 Register"/>
|
||||
<register addr="dfff0124" rw_flags="RW" width="4" name="VICVECTADDR9" comment="Vector Address 9 Register"/>
|
||||
<register addr="dfff0128" rw_flags="RW" width="4" name="VICVECTADDR10" comment="Vector Address 10 Register"/>
|
||||
<register addr="dfff012C" rw_flags="RW" width="4" name="VICVECTADDR11" comment="Vector Address 11 Register"/>
|
||||
<register addr="dfff0130" rw_flags="RW" width="4" name="VICVECTADDR12" comment="Vector Address 12 Register"/>
|
||||
<register addr="dfff0134" rw_flags="RW" width="4" name="VICVECTADDR13" comment="Vector Address 13 Register"/>
|
||||
<register addr="dfff0138" rw_flags="RW" width="4" name="VICVECTADDR14" comment="Vector Address 14 Register"/>
|
||||
<register addr="dfff013C" rw_flags="RW" width="4" name="VICVECTADDR15" comment="Vector Address 15 Register"/>
|
||||
<register addr="dfff0140" rw_flags="RW" width="4" name="VICVECTADDR16" comment="Vector Address 16 Register"/>
|
||||
<register addr="dfff0144" rw_flags="RW" width="4" name="VICVECTADDR17" comment="Vector Address 17 Register"/>
|
||||
<register addr="dfff0148" rw_flags="RW" width="4" name="VICVECTADDR18" comment="Vector Address 18 Register"/>
|
||||
<register addr="dfff014C" rw_flags="RW" width="4" name="VICVECTADDR19" comment="Vector Address 19 Register"/>
|
||||
<register addr="dfff0150" rw_flags="RW" width="4" name="VICVECTADDR20" comment="Vector Address 20 Register"/>
|
||||
<register addr="dfff0154" rw_flags="RW" width="4" name="VICVECTADDR21" comment="Vector Address 21 Register"/>
|
||||
<register addr="dfff0158" rw_flags="RW" width="4" name="VICVECTADDR22" comment="Vector Address 22 Register"/>
|
||||
<register addr="dfff015C" rw_flags="RW" width="4" name="VICVECTADDR23" comment="Vector Address 23 Register"/>
|
||||
<register addr="dfff0160" rw_flags="RW" width="4" name="VICVECTADDR24" comment="Vector Address 24 Register"/>
|
||||
<register addr="dfff0164" rw_flags="RW" width="4" name="VICVECTADDR25" comment="Vector Address 25 Register"/>
|
||||
<register addr="dfff0168" rw_flags="RW" width="4" name="VICVECTADDR26" comment="Vector Address 26 Register"/>
|
||||
<register addr="dfff016C" rw_flags="RW" width="4" name="VICVECTADDR27" comment="Vector Address 27 Register"/>
|
||||
<register addr="dfff0170" rw_flags="RW" width="4" name="VICVECTADDR28" comment="Vector Address 28 Register"/>
|
||||
<register addr="dfff0174" rw_flags="RW" width="4" name="VICVECTADDR29" comment="Vector Address 29 Register"/>
|
||||
<register addr="dfff0178" rw_flags="RW" width="4" name="VICVECTADDR30" comment="Vector Address 30 Register"/>
|
||||
<register addr="dfff017C" rw_flags="RW" width="4" name="VICVECTADDR31" comment="Vector Address 31 Register"/>
|
||||
</block>
|
||||
<block name ="Vector priorities">
|
||||
<register addr="dfff0200" rw_flags="RW" width="1" name="VICVECTPRIORITY0" comment="Vector Priority 0 Register"/>
|
||||
<register addr="dfff0204" rw_flags="RW" width="1" name="VICVECTPRIORITY1" comment="Vector Priority 1 Register"/>
|
||||
<register addr="dfff0208" rw_flags="RW" width="1" name="VICVECTPRIORITY2" comment="Vector Priority 2 Register"/>
|
||||
<register addr="dfff020C" rw_flags="RW" width="1" name="VICVECTPRIORITY3" comment="Vector Priority 3 Register"/>
|
||||
<register addr="dfff0210" rw_flags="RW" width="1" name="VICVECTPRIORITY4" comment="Vector Priority 4 Register"/>
|
||||
<register addr="dfff0214" rw_flags="RW" width="1" name="VICVECTPRIORITY5" comment="Vector Priority 5 Register"/>
|
||||
<register addr="dfff0218" rw_flags="RW" width="1" name="VICVECTPRIORITY6" comment="Vector Priority 6 Register"/>
|
||||
<register addr="dfff021C" rw_flags="RW" width="1" name="VICVECTPRIORITY7" comment="Vector Priority 7 Register"/>
|
||||
<register addr="dfff0220" rw_flags="RW" width="1" name="VICVECTPRIORITY8" comment="Vector Priority 8 Register"/>
|
||||
<register addr="dfff0224" rw_flags="RW" width="1" name="VICVECTPRIORITY9" comment="Vector Priority 9 Register"/>
|
||||
<register addr="dfff0228" rw_flags="RW" width="1" name="VICVECTPRIORITY10" comment="Vector Priority 10 Register"/>
|
||||
<register addr="dfff022C" rw_flags="RW" width="1" name="VICVECTPRIORITY11" comment="Vector Priority 11 Register"/>
|
||||
<register addr="dfff0230" rw_flags="RW" width="1" name="VICVECTPRIORITY12" comment="Vector Priority 12 Register"/>
|
||||
<register addr="dfff0234" rw_flags="RW" width="1" name="VICVECTPRIORITY13" comment="Vector Priority 13 Register"/>
|
||||
<register addr="dfff0238" rw_flags="RW" width="1" name="VICVECTPRIORITY14" comment="Vector Priority 14 Register"/>
|
||||
<register addr="dfff023C" rw_flags="RW" width="1" name="VICVECTPRIORITY15" comment="Vector Priority 15 Register"/>
|
||||
<register addr="dfff0240" rw_flags="RW" width="1" name="VICVECTPRIORITY16" comment="Vector Priority 16 Register"/>
|
||||
<register addr="dfff0244" rw_flags="RW" width="1" name="VICVECTPRIORITY17" comment="Vector Priority 17 Register"/>
|
||||
<register addr="dfff0248" rw_flags="RW" width="1" name="VICVECTPRIORITY18" comment="Vector Priority 18 Register"/>
|
||||
<register addr="dfff024C" rw_flags="RW" width="1" name="VICVECTPRIORITY19" comment="Vector Priority 19 Register"/>
|
||||
<register addr="dfff0250" rw_flags="RW" width="1" name="VICVECTPRIORITY20" comment="Vector Priority 20 Register"/>
|
||||
<register addr="dfff0254" rw_flags="RW" width="1" name="VICVECTPRIORITY21" comment="Vector Priority 21 Register"/>
|
||||
<register addr="dfff0258" rw_flags="RW" width="1" name="VICVECTPRIORITY22" comment="Vector Priority 22 Register"/>
|
||||
<register addr="dfff025C" rw_flags="RW" width="1" name="VICVECTPRIORITY23" comment="Vector Priority 23 Register"/>
|
||||
<register addr="dfff0260" rw_flags="RW" width="1" name="VICVECTPRIORITY24" comment="Vector Priority 24 Register"/>
|
||||
<register addr="dfff0264" rw_flags="RW" width="1" name="VICVECTPRIORITY25" comment="Vector Priority 25 Register"/>
|
||||
<register addr="dfff0268" rw_flags="RW" width="1" name="VICVECTPRIORITY26" comment="Vector Priority 26 Register"/>
|
||||
<register addr="dfff026C" rw_flags="RW" width="1" name="VICVECTPRIORITY27" comment="Vector Priority 27 Register"/>
|
||||
<register addr="dfff0270" rw_flags="RW" width="1" name="VICVECTPRIORITY28" comment="Vector Priority 28 Register"/>
|
||||
<register addr="dfff0274" rw_flags="RW" width="1" name="VICVECTPRIORITY29" comment="Vector Priority 29 Register"/>
|
||||
<register addr="dfff0278" rw_flags="RW" width="1" name="VICVECTPRIORITY30" comment="Vector Priority 30 Register"/>
|
||||
<register addr="dfff027C" rw_flags="RW" width="1" name="VICVECTPRIORITY31" comment="Vector Priority 31 Register"/>
|
||||
</block>
|
||||
<block name ="Coresight Management Registers">
|
||||
<register addr="dfff0F00" rw_flags="RW" width="4" name="VICADDRESS" comment="Vector Address Register"/>
|
||||
<register addr="dfff0FE0" rw_flags="R" width="1" name="VICPERIPHID0" comment="Peripheral Identification Register bits 7:0"/>
|
||||
<register addr="dfff0FE4" rw_flags="R" width="1" name="VICPERIPHID1" comment="Peripheral Identification Register bits 15:8"/>
|
||||
<register addr="dfff0FE8" rw_flags="R" width="1" name="VICPERIPHID2" comment="Peripheral Identification Register bits 23:16"/>
|
||||
<register addr="dfff0FEC" rw_flags="R" width="1" name="VICPERIPHID3" comment="Peripheral Identification Register bits 31:24"/>
|
||||
<register addr="dfff0FF0" rw_flags="R" width="1" name="VICPCELLID0" comment="PrimeCell Identification Register bits 7:0"/>
|
||||
<register addr="dfff0FF4" rw_flags="R" width="1" name="VICPCELLID1" comment="PrimeCell Identification Register bits 15:8"/>
|
||||
<register addr="dfff0FF8" rw_flags="R" width="1" name="VICPCELLID2" comment="PrimeCell Identification Register bits 23:16"/>
|
||||
<register addr="dfff0FFC" rw_flags="R" width="1" name="VICPCELLID3" comment="PrimeCell Identification Register bits 31:24"/>
|
||||
</block>
|
||||
</memory>
|
||||
</processor>
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!--
|
||||
(c) SCSC 2015 Maxwell moredump memory definitions
|
||||
From http://wiki/Maxwell140MemoryMap
|
||||
-->
|
||||
|
||||
<memory xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.samsung.com Memory.xsd">
|
||||
<!-- Define the mmap range - DO NOT CHANGE THIS -->
|
||||
<mmap startAddr="80000000" endAddr="803FFFFF"/>
|
||||
<R4>
|
||||
<!-- Memory specific to (and will only be read via) R4 -->
|
||||
<region startAddr="00000000" endAddr="00007fff" name="TCMA" comment=""/>
|
||||
<region startAddr="00018000" endAddr="0001ffff" name="TCMB1" comment=""/>
|
||||
</R4>
|
||||
<M4>
|
||||
<!-- Memory specific to (and will only be read via) M4 -->
|
||||
</M4>
|
||||
<!-- Memory that can be read via R4 or M4 (or possibly mmap) -->
|
||||
<region startAddr="07FE0000" endAddr="07FFFFFF" name="RAMCB" comment="128KB" />
|
||||
<region startAddr="08000000" endAddr="08013FFF" name="RAMSB" comment="80KB" />
|
||||
<region startAddr="80000000" endAddr="803FFFFF" name="DRAM" comment="4MB" />
|
||||
<region startAddr="C0000000" endAddr="C0017FFF" name="RAMSW ASIC" comment="96KB" />
|
||||
|
||||
<region startAddr="A0580000" endAddr="A0580003" name="MAILBOX_AP_APM 1" comment="MCU Controller" />
|
||||
<region startAddr="A0580008" endAddr="A058002F" name="MAILBOX_AP_APM 2" comment="Interrupt registers" />
|
||||
<region startAddr="A058004C" endAddr="A0580053" name="MAILBOX_AP_APM 3" comment="INIT/VERSION" />
|
||||
<region startAddr="A0580080" endAddr="A058009F" name="MAILBOX_AP_APM 4" comment="Shared registers" />
|
||||
</memory>
|
||||
|
|
@ -0,0 +1,586 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!--
|
||||
(c) SCSC 2015-2016 autogenerated by moredump.py as part of 'drun prep'.
|
||||
Changes made to this file may cause incorrect behaviour and will be lost if it is regenerated.
|
||||
|
||||
XML file defining registers for chip subsystem moredump
|
||||
Chip hash: 8423
|
||||
|
||||
|
||||
-->
|
||||
|
||||
<subsystem xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.samsung.com Registers.xsd"
|
||||
name="chip">
|
||||
<block name="alwayson_rf" comment="">
|
||||
<register addr="00000000" rw_flags="R" width="2" name="CHIP_VERSION" comment="Chip Version and ID (EVT0=0x00B0, EVT1=0x10B0, EVT1.1=0x11B0, EVT2=0x20B0)"/>
|
||||
<register addr="00000004" rw_flags="RW" width="2" name="RFIC_CONFIG" comment="Main BT/WL configuration register for RFIC."/>
|
||||
<register addr="00000008" rw_flags="R" width="1" name="RFIC_CORE_PWR_STATUS" comment="Set when the BT/WL core power domain has powered up"/>
|
||||
<register addr="0000000c" rw_flags="R" width="1" name="RFIC_PLL_UNLOCK_STATUS" comment="Set on falling edge of Aux PLL lock indicator when RFIC_CONFIG_PLL_UNLOCK_EN=1."/>
|
||||
<register addr="00000010" rw_flags="RW" width="2" name="RFIC_CLKGEN_ENABLES" comment="Clock enables"/>
|
||||
<register addr="00000014" rw_flags="RW" width="1" name="RFIC_CLKGEN_INVERT_CTRL" comment="Clock enables"/>
|
||||
<register addr="00000018" rw_flags="RW" width="1" name="RFIC_CLKGEN_SYSTEM_TIME_DIV_RATIO" comment="Divide ratio for system timer (from 80MHz clock)"/>
|
||||
<register addr="0000001c" rw_flags="RW" width="1" name="RFIC_CLKGEN_SYSTEM_TIME_EN" comment="Enable System Timer"/>
|
||||
<register addr="00000020" rw_flags="RW" width="4" name="RFIC_CLKGEN_SYSTEM_TIME_INIT_VAL" comment="Set initial value for System Timer"/>
|
||||
<register addr="00000024" rw_flags="R" width="4" name="RFIC_CLKGEN_SYSTEM_TIME" comment="Current value of System Timer"/>
|
||||
<register addr="00000028" rw_flags="R" width="1" name="AUX_ANA_STATUS0" comment=""/>
|
||||
<register addr="0000002c" rw_flags="RW" width="4" name="AUX_ANA_ENABLES" comment=""/>
|
||||
<register addr="00000030" rw_flags="RW" width="4" name="AUX_ANA_SH_CFG0" comment=""/>
|
||||
<register addr="00000034" rw_flags="RW" width="4" name="AUX_ANA_SH_CFG1" comment=""/>
|
||||
<register addr="00000038" rw_flags="RW" width="2" name="AUX_ANA_SH_CFG2" comment=""/>
|
||||
<register addr="0000003c" rw_flags="RW" width="4" name="AUX_ANA_CFG0" comment=""/>
|
||||
<register addr="00000040" rw_flags="RW" width="4" name="RFIC_PAD_MUX_CTRL" comment="PIO mux controls for PIO0 to PIO3"/>
|
||||
<register addr="00000044" rw_flags="RW" width="1" name="RFIC_SCAN_MODE_ENABLES" comment="DFT Scan mode configuration register. *FIRMWARE DO NOT TOUCH THIS*"/>
|
||||
<register addr="00000048" rw_flags="RW" width="4" name="RFIC_SCAN_CONFIG" comment="DFT Scan mode configuration register. *FIRMWARE DO NOT TOUCH THIS*"/>
|
||||
<register addr="0000004c" rw_flags="RW" width="1" name="RFIC_SCAN_RESERVE_REGS" comment="DFT Scan mode reserve registers. *FIRMWARE DO NOT TOUCH THIS*"/>
|
||||
<register addr="00000050" rw_flags="R" width="2" name="RFIC_SCAN_OBSERVE_REGS" comment="DFT Scan mode observable regsiters. *FIRMWARE DO NOT TOUCH THIS*"/>
|
||||
<register addr="00000054" rw_flags="R" width="4" name="RFIC_SCSC0" comment="Chris Hunter/Damien Smith"/>
|
||||
<register addr="00000058" rw_flags="R" width="4" name="RFIC_SCSC1" comment="Michael Cowell/Andy Barnish"/>
|
||||
<register addr="0000005c" rw_flags="R" width="4" name="RFIC_SCSC2" comment="Roger Wood/Colin Tapp"/>
|
||||
<register addr="00000060" rw_flags="R" width="4" name="RFIC_SCSC3" comment="Stelios Staveris/Hayley Bird"/>
|
||||
<register addr="00000064" rw_flags="R" width="4" name="RFIC_SCSC4" comment="Dave Price/Riccardo Micci"/>
|
||||
</block>
|
||||
<block name="bt_rf" comment="">
|
||||
<register addr="00003000" rw_flags="RW" width="1" name="BT_RF_CONFIG" comment=""/>
|
||||
<register addr="00003004" rw_flags="RW" width="1" name="BT_RF_DEBUG_SEL" comment=""/>
|
||||
<register addr="00003008" rw_flags="RW" width="1" name="BT_TX_DEBUG_SEL" comment="Bluetooth Transmit debug mux select"/>
|
||||
<register addr="0000300c" rw_flags="RW" width="1" name="BT_TX_INTERFACE_CTRL" comment=""/>
|
||||
<register addr="00003010" rw_flags="RW" width="4" name="BT_TX_MOD_TEST" comment=""/>
|
||||
<register addr="00003014" rw_flags="RW" width="1" name="BT_TX_PATTERN_GEN_CFG" comment=""/>
|
||||
<register addr="00003018" rw_flags="RW" width="1" name="BT_TX_CTRL_DEBUG_SEL" comment="Bluetooth Transmit Control debug mux select."/>
|
||||
<register addr="0000301c" rw_flags="RW" width="4" name="BT_TX_CTRL_CFG" comment="Bluetooth Transmit Control configuration."/>
|
||||
<register addr="00003020" rw_flags="RW" width="2" name="BT_TX_EDR3_ALIGN_CFG" comment="Bluetooth Transmit EDR3 Symbol Alignment workaround logic (to workaround Java EVT0 EDR3 bitstream bug)"/>
|
||||
<register addr="00003024" rw_flags="R" width="1" name="BT_TX_CTRL_STATUS" comment="The current Bluetooth Tx radio mode"/>
|
||||
<register addr="00003028" rw_flags="RW" width="1" name="BT_TX_TIMER_CFG" comment="Bluetooth Transmit Radio Timer configuration."/>
|
||||
<register addr="0000302c" rw_flags="R" width="1" name="BT_TX_TIMER_STATUS" comment="Bluetooth Transmit Radio Timer status."/>
|
||||
<register addr="00003030" rw_flags="RW" width="1" name="BT_TX_TIMER_SW_TRIGGERS" comment="Bluetooth Transmit Radio Timer software triggers."/>
|
||||
<register addr="00003034" rw_flags="RW" width="4" name="BT_TX_TIMER_EVENT_TIME" comment="Set the required Tx event time. Used when timing to an event, not used when timing from an event."/>
|
||||
<register addr="00003038" rw_flags="RW" width="1" name="BT_TX_TIMER_DIG_SW_ORIDE" comment="Bluetooth Transmit Radio Timer digital enable software overrides."/>
|
||||
<register addr="0000303c" rw_flags="RW" width="2" name="BT_TX_TIMER_TRIGGER_PLL_ABORT" comment="Bluetooth Tx Radio Timer - PLL Abort trigger configuration."/>
|
||||
<register addr="00003040" rw_flags="RW" width="2" name="BT_TX_TIMER_TRIGGER_START" comment="Bluetooth Tx Radio Timer - Start trigger configuration."/>
|
||||
<register addr="00003044" rw_flags="RW" width="2" name="BT_TX_TIMER_TRIGGER_SW_ABORT" comment="Bluetooth Tx Radio Timer - Software Abort trigger configuration."/>
|
||||
<register addr="00003048" rw_flags="RW" width="2" name="BT_TX_TIMER_TRIGGER_DONE" comment="Bluetooth Tx Radio Timer - Done trigger configuration."/>
|
||||
<register addr="0000304c" rw_flags="RW" width="2" name="BT_TX_TIMER_TRIGGER_COEX_ABORT" comment="Bluetooth Tx Radio Timer - Coex Abort trigger configuration."/>
|
||||
<register addr="00003050" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT0_ANA_EN" comment="Transmit slot 0 Analogue Enables"/>
|
||||
<register addr="00003054" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT1_ANA_EN" comment="Transmit slot 1 Analogue Enables"/>
|
||||
<register addr="00003058" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT2_ANA_EN" comment="Transmit slot 2 Analogue Enables"/>
|
||||
<register addr="0000305c" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT3_ANA_EN" comment="Transmit slot 3 Analogue Enables"/>
|
||||
<register addr="00003060" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT4_ANA_EN" comment="Transmit slot 4 Analogue Enables"/>
|
||||
<register addr="00003064" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT5_ANA_EN" comment="Transmit slot 5 Analogue Enables"/>
|
||||
<register addr="00003068" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT6_ANA_EN" comment="Transmit slot 6 Analogue Enables"/>
|
||||
<register addr="0000306c" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT7_ANA_EN" comment="Transmit slot 7 Analogue Enables"/>
|
||||
<register addr="00003070" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT8_ANA_EN" comment="Transmit slot 8 Analogue Enables"/>
|
||||
<register addr="00003074" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT9_ANA_EN" comment="Transmit slot 9 Analogue Enables"/>
|
||||
<register addr="00003078" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT10_ANA_EN" comment="Transmit slot 10 Analogue Enables"/>
|
||||
<register addr="0000307c" rw_flags="RW" width="4" name="BT_TX_TIMER_SLOT11_ANA_EN" comment="Transmit slot 11 Analogue Enables"/>
|
||||
<register addr="00003080" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT0_DIG_EN" comment="Transmit slot 0 Digital Enables"/>
|
||||
<register addr="00003084" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT1_DIG_EN" comment="Transmit slot 1 Digital Enables"/>
|
||||
<register addr="00003088" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT2_DIG_EN" comment="Transmit slot 2 Digital Enables"/>
|
||||
<register addr="0000308c" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT3_DIG_EN" comment="Transmit slot 3 Digital Enables"/>
|
||||
<register addr="00003090" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT4_DIG_EN" comment="Transmit slot 4 Digital Enables"/>
|
||||
<register addr="00003094" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT5_DIG_EN" comment="Transmit slot 5 Digital Enables"/>
|
||||
<register addr="00003098" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT6_DIG_EN" comment="Transmit slot 6 Digital Enables"/>
|
||||
<register addr="0000309c" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT7_DIG_EN" comment="Transmit slot 7 Digital Enables"/>
|
||||
<register addr="000030a0" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT8_DIG_EN" comment="Transmit slot 8 Digital Enables"/>
|
||||
<register addr="000030a4" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT9_DIG_EN" comment="Transmit slot 9 Digital Enables"/>
|
||||
<register addr="000030a8" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT10_DIG_EN" comment="Transmit slot 10 Digital Enables"/>
|
||||
<register addr="000030ac" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT11_DIG_EN" comment="Transmit slot 11 Digital Enables"/>
|
||||
<register addr="000030b0" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT0_DELAY" comment="Transmit slot 0 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030b4" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT1_DELAY" comment="Transmit slot 1 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030b8" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT2_DELAY" comment="Transmit slot 2 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030bc" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT3_DELAY" comment="Transmit slot 3 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030c0" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT4_DELAY" comment="Transmit slot 4 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030c4" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT5_DELAY" comment="Transmit slot 5 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030c8" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT6_DELAY" comment="Transmit slot 6 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030cc" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT7_DELAY" comment="Transmit slot 7 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030d0" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT8_DELAY" comment="Transmit slot 8 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030d4" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT9_DELAY" comment="Transmit slot 9 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030d8" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT10_DELAY" comment="Transmit slot 10 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030dc" rw_flags="RW" width="1" name="BT_TX_TIMER_SLOT11_DELAY" comment="Transmit slot 11 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="000030e0" rw_flags="RW" width="2" name="BT_TX_CONFIG1" comment=""/>
|
||||
<register addr="000030e4" rw_flags="RW" width="2" name="BT_TX_CONFIG2" comment=""/>
|
||||
<register addr="000030e8" rw_flags="RW" width="1" name="BT_TX_CONFIG3" comment=""/>
|
||||
<register addr="000030ec" rw_flags="RW" width="1" name="BT_TX_BB_RAMP_CONFIG" comment=""/>
|
||||
<register addr="000030f0" rw_flags="RW" width="2" name="BT_TX_BDR_SCALE_CONFIG" comment=""/>
|
||||
<register addr="000030f4" rw_flags="RW" width="2" name="BT_TX_EDR_SCALE_CONFIG" comment=""/>
|
||||
<register addr="000030f8" rw_flags="RW" width="1" name="BT_TX_MAX_ATT_CONFIG" comment=""/>
|
||||
<register addr="000030fc" rw_flags="RW" width="2" name="BT_TX_GAIN_RAMP" comment=""/>
|
||||
<register addr="00003100" rw_flags="RW" width="1" name="BT_TX_GAIN_RAMP_DELAY" comment=""/>
|
||||
<register addr="00003104" rw_flags="R" width="1" name="BT_TX_GAIN" comment=""/>
|
||||
<register addr="00003108" rw_flags="RW" width="2" name="BT_TX_MR_CONFIG1" comment=""/>
|
||||
<register addr="0000310c" rw_flags="RW" width="2" name="BT_TX_MR_CONFIG2" comment=""/>
|
||||
<register addr="00003110" rw_flags="RW" width="1" name="BT_TX_MR_MOD_DELAY" comment=""/>
|
||||
<register addr="00003114" rw_flags="RW" width="2" name="BT_POLAR_CTRL" comment="General control register"/>
|
||||
<register addr="00003118" rw_flags="RW" width="2" name="BT_POLAR_CTRL2" comment="Second set of general control register"/>
|
||||
<register addr="0000311c" rw_flags="RW" width="2" name="BT_POLAR_MAG_DATA" comment="Magnitude value to be inserted into Polar chain at various points when reg source selected (Only 10 LS bits are used when this is used to drive TX_AM_DAC output)"/>
|
||||
<register addr="00003120" rw_flags="RW" width="2" name="BT_POLAR_PHASE_DATA" comment="Phase value to be inserted into Polar chain at various points when reg source selected"/>
|
||||
<register addr="00003124" rw_flags="RW" width="2" name="BT_POLAR_MUX_1" comment="Mux control register"/>
|
||||
<register addr="00003128" rw_flags="RW" width="2" name="BT_POLAR_MUX_2" comment="Mux control register"/>
|
||||
<register addr="0000312c" rw_flags="RW" width="2" name="BT_POLAR_QUAD_POLAR_I_DATA" comment="Quadrature-Polar converter I data input register"/>
|
||||
<register addr="00003130" rw_flags="RW" width="2" name="BT_POLAR_QUAD_POLAR_Q_DATA" comment="Quadrature-Polar converter Q data input register"/>
|
||||
<register addr="00003134" rw_flags="RW" width="1" name="BT_POLAR_AA_FIR_CONTROL" comment="FIR filter control for AntiAliasing"/>
|
||||
<register addr="00003138" rw_flags="RW" width="1" name="BT_POLAR_AA_FIR_TAP0" comment="AntiAliasing FIR filter, tap 0 of 5"/>
|
||||
<register addr="0000313c" rw_flags="RW" width="1" name="BT_POLAR_AA_FIR_TAP1" comment="AntiAliasing FIR filter, tap 1 of 5"/>
|
||||
<register addr="00003140" rw_flags="RW" width="1" name="BT_POLAR_AA_FIR_TAP2" comment="AntiAliasing FIR filter, tap 2 of 5"/>
|
||||
<register addr="00003144" rw_flags="RW" width="1" name="BT_POLAR_AA_FIR_TAP3" comment="AntiAliasing FIR filter, tap 3 of 5"/>
|
||||
<register addr="00003148" rw_flags="RW" width="1" name="BT_POLAR_AA_FIR_TAP4" comment="AntiAliasing FIR filter, tap 4 of 5"/>
|
||||
<register addr="0000314c" rw_flags="R" width="2" name="BT_POLAR_DEBUG_STATUS" comment="Debug Status bus"/>
|
||||
<register addr="00003150" rw_flags="RW" width="2" name="BT_POLAR_QUAD_POLAR_AMP_CONST" comment="Correction const for Quad-Polar Amp output (const/4096 scales output and includes Cordic magnitude correction)"/>
|
||||
<register addr="00003154" rw_flags="RW" width="2" name="BT_POLAR_QUAD_POLAR_PHASE_CONST" comment="Correction const for Quad-Polar Phase output (const/4096 scales +-180 to +-2047)"/>
|
||||
<register addr="00003158" rw_flags="RW" width="2" name="BT_POLAR_COMPENSATION_DATA_WRITE" comment="Compensation Y LUT write register"/>
|
||||
<register addr="0000315c" rw_flags="R" width="2" name="BT_POLAR_COMPENSATION_DATA_READ" comment="Compensation Y LUT read register"/>
|
||||
<register addr="00003160" rw_flags="RW" width="1" name="BT_POLAR_COMPENSATION_ADDR" comment="Compensation Y LUT address register"/>
|
||||
<register addr="00003164" rw_flags="RW" width="4" name="BT_POLAR_TEST_STIM_LSW" comment="Polar Test stimulus"/>
|
||||
<register addr="00003168" rw_flags="RW" width="1" name="BT_POLAR_TEST_STIM_MSB" comment="Polar Test stimulus"/>
|
||||
<register addr="0000316c" rw_flags="R" width="4" name="BT_POLAR_TEST_CAP_LSW" comment="Polar Test capture"/>
|
||||
<register addr="00003170" rw_flags="R" width="4" name="BT_POLAR_TEST_CAP_MSW" comment="Polar Test capture"/>
|
||||
<register addr="00003174" rw_flags="RW" width="4" name="BT_POLAR_IIR_COEFF1_LSW" comment="TX POLAR IIR filter coefficients (Biquad 1)"/>
|
||||
<register addr="00003178" rw_flags="RW" width="1" name="BT_POLAR_IIR_COEFF1_MSB" comment="TX POLAR IIR filter coefficients (Biquad 1)"/>
|
||||
<register addr="0000317c" rw_flags="RW" width="4" name="BT_POLAR_IIR_COEFF2_LSW" comment="TX POLAR IIR filter coefficients (Biquad 2)"/>
|
||||
<register addr="00003180" rw_flags="RW" width="1" name="BT_POLAR_IIR_COEFF2_MSB" comment="TX POLAR IIR filter coefficients (Biquad 2)"/>
|
||||
<register addr="00003184" rw_flags="RW" width="2" name="BT_POLAR_IIR_FILTER_CFG" comment="TX POLAR IIR filter configuration"/>
|
||||
<register addr="00003188" rw_flags="RW" width="2" name="BT_POLAR_POLAR_QUAD_PHASE_CORR" comment="Signed: Phase correction adjustments for Polar to IQ conversion (shifted left by 2)"/>
|
||||
<register addr="0000318c" rw_flags="RW" width="1" name="BT_POLAR_POLAR_QUAD_AMP_CORR" comment="Signed: Amplitude correction adjustments for Polar to IQ conversion"/>
|
||||
<register addr="00003190" rw_flags="RW" width="2" name="BT_POLAR_POLAR_QUAD_OFFSET" comment="I and Q offset adjustments for Polar to IQ conversion"/>
|
||||
<register addr="00003194" rw_flags="RW" width="2" name="BT_POLAR_POLAR_QUAD_AMP_CONST" comment="Correction const for Polar-Quad Amp output (4096/const unscales output)"/>
|
||||
<register addr="00003198" rw_flags="RW" width="2" name="BT_POLAR_POLAR_QUAD_PHASE_CONST" comment="Correction const for Polar-Quad Phase output - reset default gives x1"/>
|
||||
<register addr="0000319c" rw_flags="RW" width="2" name="BT_POLAR_SIGGEN_CTRL" comment="Cal Siggen sine wave Ctrl"/>
|
||||
<register addr="000031a0" rw_flags="RW" width="2" name="BT_POLAR_SIGGEN_FREQ" comment="Cal Siggen sine wave - frequency to generate"/>
|
||||
<register addr="000031a4" rw_flags="RW" width="1" name="BT_POLAR_INVERT_CTRL" comment="Fallback IQ Inversion control"/>
|
||||
<register addr="000031a8" rw_flags="RW" width="1" name="BT_RF_RX_CFG" comment="Bluetooth Rx configuration."/>
|
||||
<register addr="000031ac" rw_flags="RW" width="1" name="BT_RX_INTERFACE_CTRL" comment="Bluetooth Rx Interface control."/>
|
||||
<register addr="000031b0" rw_flags="RW" width="1" name="BT_RX_DEBUG_SEL" comment="Bluetooth Rx debug mux select."/>
|
||||
<register addr="000031b4" rw_flags="RW" width="2" name="BT_RX_SUPP_CFG" comment="Bluetooth Rx Supplemental Sampler configuration register (for Direction Finding)."/>
|
||||
<register addr="000031b8" rw_flags="RW" width="1" name="BT_RX_CTRL_DEBUG_SEL" comment="Bluetooth Rx Control debug mux select."/>
|
||||
<register addr="000031bc" rw_flags="R" width="4" name="BT_RX_BDR_SYNC_TIME" comment="The time we found BDR Sync (in relation to RFIC System Time)"/>
|
||||
<register addr="000031c0" rw_flags="RW" width="4" name="BT_RX_BDR_SYNC_TIMEOUT_OFFSET" comment="The number of microseconds before the BDR sync timeout is asserted from the point the Rx Digital enable is set (in reference to the RFIC system time)"/>
|
||||
<register addr="000031c4" rw_flags="RW" width="4" name="BT_RX_LR_SYNC_TIMEOUT_OFFSET" comment="The number of microseconds before the LR sync timeout is asserted from the point the Rx Digital enable is set (in reference to the RFIC system time)"/>
|
||||
<register addr="000031c8" rw_flags="RW" width="2" name="BT_RX_CTRL_CFG" comment="Bluetooth Rx Control configuration."/>
|
||||
<register addr="000031cc" rw_flags="RW" width="1" name="BT_RX_EDR3_ALIGN_CFG" comment="Set to enable EDR3 symbol alignment workaround logic for Java EVT0."/>
|
||||
<register addr="000031d0" rw_flags="RW" width="4" name="BT_RX_MLE_ESCO_OFFSET" comment="Set to enable EDR3 symbol alignment workaround logic for Java EVT0."/>
|
||||
<register addr="000031d4" rw_flags="RW" width="4" name="BT_RX_MLE_ACL_OFFSET" comment="Set to enable EDR3 symbol alignment workaround logic for Java EVT0."/>
|
||||
<register addr="000031d8" rw_flags="RW" width="4" name="BT_RX_MR_SYNC_TIMING" comment="BT DPSK synchronization timing configuration"/>
|
||||
<register addr="000031dc" rw_flags="RW" width="1" name="BT_RX_TIMER_CFG" comment="Bluetooth Rx Radio Timer configuration."/>
|
||||
<register addr="000031e0" rw_flags="R" width="1" name="BT_RX_TIMER_STATUS" comment="Bluetooth Rx Radio Timer status."/>
|
||||
<register addr="000031e4" rw_flags="RW" width="1" name="BT_RX_TIMER_SW_TRIGGERS" comment="Bluetooth Rx Radio Timer software triggers."/>
|
||||
<register addr="000031e8" rw_flags="RW" width="4" name="BT_RX_TIMER_EVENT_TIME" comment="Set the required Tx event time. Used when timing to an event, not used when timing from an event."/>
|
||||
<register addr="000031ec" rw_flags="RW" width="1" name="BT_RX_TIMER_DIG_SW_ORIDE" comment="Override timer digital outputs, when masked."/>
|
||||
<register addr="000031f0" rw_flags="RW" width="2" name="BT_RX_TIMER_TRIGGER_PLL_ABORT" comment="Bluetooth Rx Radio Timer - PLL Abort trigger configuration."/>
|
||||
<register addr="000031f4" rw_flags="RW" width="2" name="BT_RX_TIMER_TRIGGER_START" comment="Bluetooth Rx Radio Timer - Start trigger configuration."/>
|
||||
<register addr="000031f8" rw_flags="RW" width="2" name="BT_RX_TIMER_TRIGGER_SW_ABORT" comment="Bluetooth Rx Radio Timer - Softwre Abort trigger configuration."/>
|
||||
<register addr="000031fc" rw_flags="RW" width="2" name="BT_RX_TIMER_TRIGGER_DONE" comment="Bluetooth Rx Radio Timer - Done trigger configuration."/>
|
||||
<register addr="00003200" rw_flags="RW" width="2" name="BT_RX_TIMER_TRIGGER_SYNC_TIMEOUT" comment="Bluetooth Rx Radio Timer - BDR Sync Timeout trigger configuration."/>
|
||||
<register addr="00003204" rw_flags="RW" width="2" name="BT_RX_TIMER_TRIGGER_COEX_ABORT" comment="Bluetooth Rx Radio Timer - Coex Abort trigger configuration."/>
|
||||
<register addr="00003208" rw_flags="RW" width="2" name="BT_RX_TIMER_TRIGGER_MLSE_EARLY" comment="Bluetooth Rx Radio Timer - MLSE Early trigger configuration."/>
|
||||
<register addr="0000320c" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT0_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003210" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT1_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003214" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT2_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003218" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT3_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="0000321c" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT4_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003220" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT5_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003224" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT6_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003228" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT7_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="0000322c" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT8_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003230" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT9_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003234" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT10_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="00003238" rw_flags="RW" width="4" name="BT_RX_TIMER_SLOT11_ANA_EN" comment="Receive slot 0 Analogue Enables"/>
|
||||
<register addr="0000323c" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT0_DIG_EN" comment="Receive slot 0 Digital Enables"/>
|
||||
<register addr="00003240" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT1_DIG_EN" comment="Receive slot 1 Digital Enables"/>
|
||||
<register addr="00003244" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT2_DIG_EN" comment="Receive slot 2 Digital Enables"/>
|
||||
<register addr="00003248" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT3_DIG_EN" comment="Receive slot 3 Digital Enables"/>
|
||||
<register addr="0000324c" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT4_DIG_EN" comment="Receive slot 4 Digital Enables"/>
|
||||
<register addr="00003250" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT5_DIG_EN" comment="Receive slot 5 Digital Enables"/>
|
||||
<register addr="00003254" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT6_DIG_EN" comment="Receive slot 6 Digital Enables"/>
|
||||
<register addr="00003258" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT7_DIG_EN" comment="Receive slot 7 Digital Enables"/>
|
||||
<register addr="0000325c" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT8_DIG_EN" comment="Receive slot 8 Digital Enables"/>
|
||||
<register addr="00003260" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT9_DIG_EN" comment="Receive slot 9 Digital Enables"/>
|
||||
<register addr="00003264" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT10_DIG_EN" comment="Receive slot 10 Digital Enables"/>
|
||||
<register addr="00003268" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT11_DIG_EN" comment="Receive slot 11 Digital Enables"/>
|
||||
<register addr="0000326c" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT0_DELAY" comment="Receive slot 0 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003270" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT1_DELAY" comment="Receive slot 1 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003274" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT2_DELAY" comment="Receive slot 2 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003278" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT3_DELAY" comment="Receive slot 3 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="0000327c" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT4_DELAY" comment="Receive slot 4 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003280" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT5_DELAY" comment="Receive slot 5 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003284" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT6_DELAY" comment="Receive slot 6 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003288" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT7_DELAY" comment="Receive slot 7 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="0000328c" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT8_DELAY" comment="Receive slot 8 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003290" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT9_DELAY" comment="Receive slot 9 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003294" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT10_DELAY" comment="Receive slot 10 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="00003298" rw_flags="RW" width="1" name="BT_RX_TIMER_SLOT11_DELAY" comment="Receive slot 11 - delay from trigger or to trigger depending on trigger type"/>
|
||||
<register addr="0000329c" rw_flags="RW" width="2" name="BT_RX_MR_FREQ_CONFIG" comment="BT DPSK demodulator frequency offset in bits [12:0] - Bit 15 when *** cleared *** enables spectrum inversion (change sign of Q channel *** after *** SDDCRS mixer)"/>
|
||||
<register addr="000032a0" rw_flags="RW" width="2" name="BT_RX_MR_FREQ_OFFSET" comment="BT DPSK demodulator frequency offset value"/>
|
||||
<register addr="000032a4" rw_flags="RW" width="2" name="BT_CAL_ANALYSER_CFG" comment="This register configures the signal analyser"/>
|
||||
<register addr="000032a8" rw_flags="RW" width="2" name="BT_CAL_ANALYSER_FREQ" comment="This sets the frequency of the tone used by the signal analyser. f = reg_value * (16_000_000)/2^16.This sets the frequency of the tone used by the signal analyser."/>
|
||||
<register addr="000032ac" rw_flags="R" width="4" name="BT_CAL_ANALYSER_RESULT" comment="This register contains the values generated by the signal analyser, Real = [7:0], Imag = [15:8]"/>
|
||||
<register addr="000032b0" rw_flags="RW" width="4" name="BT_RX_DEMOD_CONFIG" comment="BT GFSK demodulator configuration"/>
|
||||
<register addr="000032b4" rw_flags="RW" width="2" name="BT_BDR_FREQ_DISC_CONFIG" comment="Configures GFSK frequency discriminator"/>
|
||||
<register addr="000032b8" rw_flags="RW" width="4" name="BT_BDR_FREQ2_CONFIG" comment="Configures GFSK frequency discriminator"/>
|
||||
<register addr="000032bc" rw_flags="RW" width="2" name="BT_RX_DEMOD_BDR_DECISION_EQ_CONFIG" comment="Configures the decision-directed BDR equaliser"/>
|
||||
<register addr="000032c0" rw_flags="RW" width="1" name="BT_PHASESQUELCH_CONFIG" comment="'Squelch' functionality for frequency discriminator"/>
|
||||
<register addr="000032c4" rw_flags="RW" width="4" name="BT_RX_DEMOD_MLSE_CONFIG" comment="Config for and enable for the new RX BDR enhancements provided by MLSE block"/>
|
||||
<register addr="000032c8" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLSE_LR_CONFIG" comment="Config for MLSE LR"/>
|
||||
<register addr="000032cc" rw_flags="RW" width="4" name="BT_RX_DEMOD_MLSE_LR_EXP_FREQ_CONFIG" comment="Config for MLSE LR, expected FREQ"/>
|
||||
<register addr="000032d0" rw_flags="RW" width="4" name="BT_RX_DEMOD_MLSE_SYNC_CONFIG" comment="MLSE config for the FFT sync block"/>
|
||||
<register addr="000032d4" rw_flags="RW" width="1" name="BT_RX_DEMOD_MLSE_DEBUG" comment="Debug Sel"/>
|
||||
<register addr="000032d8" rw_flags="RW" width="2" name="BT_RX_SYNC_CONFIG" comment="Additional Synchroniser config"/>
|
||||
<register addr="000032dc" rw_flags="RW" width="4" name="BT_RF_ACCESS_CODE_LAP" comment="Lower address part of BT address to generate access code"/>
|
||||
<register addr="000032e0" rw_flags="RW" width="4" name="BT_RX_WBREE_ACCESS_ADDR" comment="Wibree Access Address. Sync word to seacrhg for in received packets"/>
|
||||
<register addr="000032e4" rw_flags="RW" width="2" name="BT_RX_ANT_NET_ADDR" comment="ANT Network Address for Rx Synchroniser"/>
|
||||
<register addr="000032e8" rw_flags="RW" width="2" name="BT_RX_LLR_CONFIG" comment="LLR Configuration"/>
|
||||
<register addr="000032ec" rw_flags="RW" width="4" name="BT_RF_LLR_TRIGGER_LSW" comment="LLR Access Code to transmit or receive LSW"/>
|
||||
<register addr="000032f0" rw_flags="RW" width="4" name="BT_RF_LLR_TRIGGER_MSW" comment="LLR Access Code to transmit or receive MSW"/>
|
||||
<register addr="000032f4" rw_flags="R" width="2" name="BT_RX_SYNC_NUM_ERRORS" comment="Number of bit errors in access code"/>
|
||||
<register addr="000032f8" rw_flags="R" width="2" name="BT_RX_FREQ_DISCRIM" comment="BT GFSK frequency discriminator output"/>
|
||||
<register addr="000032fc" rw_flags="R" width="2" name="BT_RX_FREQ_ERROR" comment="BT GFSK actual frequency offset output"/>
|
||||
<register addr="00003300" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_CONFIG" comment="Config for and enable for the new RX EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003304" rw_flags="RW" width="4" name="BT_RX_MR_SYNC_MLE_CONFIG" comment=""/>
|
||||
<register addr="00003308" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM00" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="0000330c" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM02" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003310" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM04" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003314" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM06" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003318" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM08" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="0000331c" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM10" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003320" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM12" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003324" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_THCOM14" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003328" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_HBASE00" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="0000332c" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_HBASE02" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003330" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_HBASE04" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003334" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_HBASE06" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003338" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_HBASE08" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="0000333c" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_HBASE10" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003340" rw_flags="RW" width="2" name="BT_RX_DEMOD_MLE_HBASE12" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003344" rw_flags="RW" width="1" name="BT_RX_DEMOD_MLE_HBASE14" comment="Config for EDR enhancements provided by MLE block"/>
|
||||
<register addr="00003348" rw_flags="RW" width="2" name="BT_RX_MR_SYNC_CONFIG" comment="BT DPSK demodulator synchronization configuration"/>
|
||||
<register addr="0000334c" rw_flags="RW" width="2" name="BT_RX_MR_SAMP_CONFIG" comment="BT DPSK demodulator slicer configuration"/>
|
||||
<register addr="00003350" rw_flags="RW" width="4" name="BT_RX_MR_EQ_TAPS_LSW" comment="BT DPSK RRC-filter coefficients LSW"/>
|
||||
<register addr="00003354" rw_flags="RW" width="4" name="BT_RX_MR_EQ_TAPS_MSW" comment="BT DPSK RRC-filter coefficients MSW"/>
|
||||
<register addr="00003358" rw_flags="R" width="1" name="BT_RX_MR_FREQ_ERROR" comment="BT DPSK actual frequency offset output"/>
|
||||
<register addr="0000335c" rw_flags="R" width="1" name="BT_RX_MR_SYNC_SCORE" comment="BT DPSK synchronizer score output"/>
|
||||
<register addr="00003360" rw_flags="R" width="1" name="BT_DCRS_ADC_MON_STATUS" comment="ADC power detect output register: Note: BT_DCRS_ADC_MON_SINGLE_SHOT_EN should be set if this register is being used for scanning purposes."/>
|
||||
<register addr="00003364" rw_flags="RW" width="1" name="BT_DCRS_ADC_MON_CS_ENABLE" comment="Conditional scan enable (turns on just sincfir and adcproc)"/>
|
||||
<register addr="00003368" rw_flags="RW" width="1" name="BT_DCRS_CIC_CFG" comment="BT CIC decimator configuration"/>
|
||||
<register addr="0000336c" rw_flags="RW" width="1" name="BT_DCRS_ADC_MON_ENABLE" comment="Enables optional ADC domain processing"/>
|
||||
<register addr="00003370" rw_flags="RW" width="2" name="BT_DCRS_ADC_MON_CONFIG" comment="Optional ADC domain processing configuration"/>
|
||||
<register addr="00003374" rw_flags="RW" width="1" name="BT_DCRS_ADC_MON_CONFIG2" comment="Optional ADC domain processing configuration 2"/>
|
||||
<register addr="00003378" rw_flags="RW" width="1" name="BT_DCRS_ADC_MON_CS_RESET" comment="Rising edge on this signal resets ADC RMS accumulator"/>
|
||||
<register addr="0000337c" rw_flags="R" width="2" name="BT_DCRS_AGCGAIN_MON_AT_SYNC" comment="AGC gain parameters readback to determine gain settings at time of RxSync. Additional fields contain 4 bits recording whether saturation occurred after RxSync."/>
|
||||
<register addr="00003380" rw_flags="RW" width="1" name="BT_DCRS_AGC_CFG" comment="BT AGC configuration"/>
|
||||
<register addr="00003384" rw_flags="R" width="1" name="BT_DCRS_AGC_STATUS" comment="Capture some raw Ana sigs"/>
|
||||
<register addr="00003388" rw_flags="RW" width="1" name="BT_DCRS_AGC_EN_SRC" comment="Configures AGC enable criteria"/>
|
||||
<register addr="0000338c" rw_flags="RW" width="1" name="BT_DCRS_AGC_SW_LNA_GAIN" comment="Startup/SW override for LNA gain value (valid values are 0 to 6)"/>
|
||||
<register addr="00003390" rw_flags="RW" width="1" name="BT_DCRS_AGC_SW_MIX_GAIN" comment="Startup/SW override for MIX gain value (valid values are 0 to 4)"/>
|
||||
<register addr="00003394" rw_flags="RW" width="1" name="BT_DCRS_AGC_SW_BUF_GAIN" comment="Startup/SW override for BUF gain value (valid values are 0 to 3)"/>
|
||||
<register addr="00003398" rw_flags="RW" width="1" name="BT_DCRS_AGC_SW_DIG_GAIN" comment="Startup/SW override for DIG gain value - Signed 2's complement: -8 to +15 selects digital gain of -48dB to +21dB in 3dB steps"/>
|
||||
<register addr="0000339c" rw_flags="RW" width="2" name="BT_DCRS_AGC_SW_CTRL" comment="SW override enables"/>
|
||||
<register addr="000033a0" rw_flags="RW" width="4" name="BT_DCRS_AGC_GAIN_STEPS" comment="AGC LNA step values for each saturation indicator"/>
|
||||
<register addr="000033a4" rw_flags="RW" width="4" name="BT_DCRS_AGC_SATRST" comment="Configurable AGC Saturation Indicator resets"/>
|
||||
<register addr="000033a8" rw_flags="RW" width="2" name="BT_DCRS_AGC_CONF1" comment="AGC configuration register 1"/>
|
||||
<register addr="000033ac" rw_flags="RW" width="2" name="BT_DCRS_AGC_CONF2" comment="AGC configuration register 2"/>
|
||||
<register addr="000033b0" rw_flags="RW" width="2" name="BT_DCRS_AGC_CONF3" comment="AGC configuration register 3"/>
|
||||
<register addr="000033b4" rw_flags="RW" width="2" name="BT_DCRS_AGC_CONF4" comment="AGC configuration register 4"/>
|
||||
<register addr="000033b8" rw_flags="RW" width="1" name="BT_DCRS_AGC_CONF5" comment="AGC configuration register 5"/>
|
||||
<register addr="000033bc" rw_flags="RW" width="2" name="BT_DCRS_AGC_EQ_PWR_THR" comment="(Post digital gain) power threshold register for digital gain control"/>
|
||||
<register addr="000033c0" rw_flags="RW" width="2" name="BT_DCRS_AGC_BB_PWR_HI_THR" comment="(Pre digital gain) power threshold register for analog gain control"/>
|
||||
<register addr="000033c4" rw_flags="RW" width="2" name="BT_DCRS_AGC_BB_PWR_DET_THR" comment="(Post digital gain) power threshold register for power detection"/>
|
||||
<register addr="000033c8" rw_flags="RW" width="1" name="BT_DCRS_AGC_FAST_DIG_CTRL_CFG" comment="(Pre digital gain) power threshold register for fast digital control of the analogue gains"/>
|
||||
<register addr="000033cc" rw_flags="R" width="2" name="BT_DCRS_AGCGAIN_MON" comment="AGC gain parameters readback"/>
|
||||
<register addr="000033d0" rw_flags="R" width="2" name="BT_DCRS_SAT_MON" comment="Monitor raw saturation detectorors"/>
|
||||
<register addr="000033d4" rw_flags="RW" width="4" name="BT_DCRS_BB_EQ_CFG0" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033d8" rw_flags="RW" width="4" name="BT_DCRS_BB_EQ_CFG1" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033dc" rw_flags="RW" width="4" name="BT_DCRS_BB_EQ_CFG2" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033e0" rw_flags="RW" width="4" name="BT_DCRS_BB_EQ_CFG3" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033e4" rw_flags="RW" width="4" name="BT_DCRS_BB_EQ_CFG4" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033e8" rw_flags="RW" width="4" name="BT_DCRS_BB_EQ_CFG5" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033ec" rw_flags="RW" width="4" name="BT_DCRS_BB_EQ_CFG6" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033f0" rw_flags="RW" width="2" name="BT_DCRS_BB_EQ_CFG7" comment="BT baseband equalizer filter coefficients"/>
|
||||
<register addr="000033f4" rw_flags="RW" width="1" name="BT_DCRS_EQ_CONFIG" comment="BT baseband equalizer configuration"/>
|
||||
<register addr="000033f8" rw_flags="RW" width="1" name="BT_DCRS_DBG_CFG" comment="BT debug mux configuration"/>
|
||||
<register addr="000033fc" rw_flags="RW" width="1" name="BT_DCRS_DBG_SEL" comment=""/>
|
||||
<register addr="00003400" rw_flags="RW" width="2" name="BT_DCRS_IF_EQ_CFG" comment="BT IF equalizer filter coefficients"/>
|
||||
<register addr="00003404" rw_flags="RW" width="1" name="BT_DCRS_IIR_CONFIG" comment="IIR decimation configuration"/>
|
||||
<register addr="00003408" rw_flags="RW" width="2" name="BT_DCRS_NBIIR_FILTER_CFG" comment="SDDCRS NarrowBand IIR filter configuration"/>
|
||||
<register addr="0000340c" rw_flags="RW" width="4" name="BT_DCRS_NBIIR_COEFF1_LSW" comment="SDDCRS NarrowBand IIR filter coefficients (Biquad 1) LSW"/>
|
||||
<register addr="00003410" rw_flags="RW" width="1" name="BT_DCRS_NBIIR_COEFF1_MSB" comment="SDDCRS NarrowBand IIR filter coefficients (Biquad 1) MSB"/>
|
||||
<register addr="00003414" rw_flags="RW" width="4" name="BT_DCRS_NBIIR_COEFF2_LSW" comment="SDDCRS NarrowBand IIR filter coefficients (Biquad 2) LSW"/>
|
||||
<register addr="00003418" rw_flags="RW" width="1" name="BT_DCRS_NBIIR_COEFF2_MSB" comment="SDDCRS NarrowBand IIR filter coefficients (Biquad 2) MSB"/>
|
||||
<register addr="0000341c" rw_flags="RW" width="4" name="BT_DCRS_TINC_CFG" comment="BT resampling ratio configuration - Must be calculated as round((1 - 16*(BT_DCRS_CIC_DEC+1)/fAdc_MHz) * 2^26) - Use floor instead of round if BT_DCRS_PHASE_LOCK is set"/>
|
||||
<register addr="00003420" rw_flags="RW" width="1" name="BT_DCRS_LINT_CFG" comment="BT linear interpolator configuration"/>
|
||||
<register addr="00003424" rw_flags="RW" width="4" name="BT_DCRS_PHASECOMP_SHIFTS_LNA0" comment=""/>
|
||||
<register addr="00003428" rw_flags="RW" width="2" name="BT_DCRS_PHASECOMP_SHIFTS_LNA1" comment=""/>
|
||||
<register addr="0000342c" rw_flags="RW" width="4" name="BT_DCRS_PHASECOMP_SHIFTS_BUF" comment=""/>
|
||||
<register addr="00003430" rw_flags="RW" width="4" name="BT_DCRS_PHASECOMP_SHIFTS_MIX0" comment=""/>
|
||||
<register addr="00003434" rw_flags="RW" width="1" name="BT_DCRS_PHASECOMP_SHIFTS_MIX1" comment=""/>
|
||||
<register addr="00003438" rw_flags="RW" width="4" name="BT_DCRS_PHASECOMP_DELAYS" comment="Phase compensator delay values"/>
|
||||
<register addr="0000343c" rw_flags="RW" width="2" name="BT_DCRS_NOM_IF_BT_CFG" comment="BT nominal IF"/>
|
||||
<register addr="00003440" rw_flags="R" width="2" name="BT_DCRS_FREQ_OFFSET_STATUS" comment=""/>
|
||||
<register addr="00003444" rw_flags="R" width="4" name="BT_DCRS_BB_PWR_STATUS" comment="Measured baseband power (pre-digital gain)"/>
|
||||
<register addr="00003448" rw_flags="R" width="2" name="BT_DCRS_EQ_PWR_STATUS_AT_SYNC" comment="This is not exactly EqPwr registered at Sync. It is the post-digital gain signal power averaged over the longer period of time used for BbPwr. In order to measure this, we use BbPwr and compensate for the digital gain at Sync. This results in a stabilised RSSI value after digital gain. It also produces a 16-bit result which the XAP can more easily manage than the raw BBPwrAtSync (32 bit)Measured baseband power (post-digital gain) obtained at RxSync, averaged over the longer period of time used for pre-digital gain measurements."/>
|
||||
<register addr="0000344c" rw_flags="R" width="2" name="BT_DCRS_EQ_PWR_STATUS" comment="Raw EqPwr"/>
|
||||
<register addr="00003450" rw_flags="RW" width="2" name="BT_DCRS_AGC_PWR_MEAS" comment="AGC power measure configuration"/>
|
||||
<register addr="00003454" rw_flags="RW" width="2" name="BT_DCRS_SYNCPHASE_CONFIG" comment="Configures phase of clock synchronization buffer"/>
|
||||
<register addr="00003458" rw_flags="R" width="1" name="BT_DCRS_STATUS" comment="Contains the status from the Dcrs block "/>
|
||||
<register addr="0000345c" rw_flags="R" width="2" name="BT_ANA_STATUS" comment="Miscellaneous readable analogue bits"/>
|
||||
<register addr="00003460" rw_flags="R" width="4" name="BT_ANA_LO_DPLL_TEST_STATUS" comment="This register contains test outputs from the LO"/>
|
||||
<register addr="00003464" rw_flags="RW" width="4" name="BT_ANA_MISC" comment=""/>
|
||||
<register addr="00003468" rw_flags="RW" width="4" name="BT_ANA_STATIC_SPARE" comment="Static spare bits for analogue. Descriptions will be updated based on analogue usage."/>
|
||||
<register addr="0000346c" rw_flags="RW" width="4" name="BT_ANA_RXRF" comment=""/>
|
||||
<register addr="00003470" rw_flags="RW" width="4" name="BT_ANA_RXADC" comment=""/>
|
||||
<register addr="00003474" rw_flags="RW" width="4" name="BT_ANA_TXBB_0" comment=""/>
|
||||
<register addr="00003478" rw_flags="RW" width="2" name="BT_ANA_TXBB_1" comment=""/>
|
||||
<register addr="0000347c" rw_flags="RW" width="4" name="BT_ANA_TXRF_0" comment=""/>
|
||||
<register addr="00003480" rw_flags="RW" width="4" name="BT_ANA_TXRF_1" comment=""/>
|
||||
<register addr="00003484" rw_flags="RW" width="2" name="BT_ANA_TXRF_2" comment=""/>
|
||||
<register addr="00003488" rw_flags="RW" width="4" name="BT_ANA_LO_CLKREF_ADC" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="0000348c" rw_flags="RW" width="4" name="BT_ANA_LO_DCO_CONF1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="00003490" rw_flags="RW" width="4" name="BT_ANA_LO_DCO_CONF2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="00003494" rw_flags="RW" width="4" name="BT_ANA_LO_DCO_OPEN1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="00003498" rw_flags="RW" width="4" name="BT_ANA_LO_DCO_OPEN2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="0000349c" rw_flags="RW" width="4" name="BT_ANA_LO_DCO_TEST" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034a0" rw_flags="RW" width="4" name="BT_ANA_LO_DPLL_CONF1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034a4" rw_flags="RW" width="4" name="BT_ANA_LO_DPLL_CONF2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034a8" rw_flags="RW" width="4" name="BT_ANA_LO_DPLL_TEST" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034ac" rw_flags="RW" width="4" name="BT_ANA_LO_D_FREQ1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034b0" rw_flags="RW" width="4" name="BT_ANA_LO_D_FREQ2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034b4" rw_flags="RW" width="4" name="BT_ANA_LO_TEST" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034b8" rw_flags="RW" width="4" name="BT_ANA_LO_PLL_RESV" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034bc" rw_flags="RW" width="4" name="BT_ANA_LO_PU_DCO_CONF" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034c0" rw_flags="RW" width="4" name="BT_ANA_LO_PU_TDC_CONF" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034c4" rw_flags="RW" width="4" name="BT_ANA_LO_AREG_CONF" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034c8" rw_flags="RW" width="4" name="BT_ANA_LO_TDC_NLMEM" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034cc" rw_flags="RW" width="4" name="BT_ANA_LO_TOP" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034d0" rw_flags="RW" width="1" name="BT_ANA_DEBUG_SEL" comment=""/>
|
||||
<register addr="000034d4" rw_flags="RW" width="2" name="BT_ANAIF_CFG" comment="ADC Digital saturation filter control"/>
|
||||
<register addr="000034d8" rw_flags="RW" width="1" name="BT_ANA_LO_SW_STOP" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000034dc" rw_flags="RW" width="4" name="BT_ANA_SW_ENABLES" comment="Override value for timer outputs when not controlled by timer"/>
|
||||
<register addr="000034e0" rw_flags="RW" width="4" name="BT_ANA_SW_ENABLES_MASK" comment="Selects whether timer outputs or override bits are used for analogue"/>
|
||||
<register addr="000034e4" rw_flags="R" width="4" name="BT_ANA_ENABLES_STATUS" comment="Shows values being driven to analogue interface after timer and masking function is resolved"/>
|
||||
<register addr="000034e8" rw_flags="RW" width="4" name="BT_ANA_LNA_ZIN_TRIM_LUT" comment="First 4 locations of LUT used to generate the 2G5 LNA ZinTrim value."/>
|
||||
</block>
|
||||
<block name="btwl_common" comment="">
|
||||
<register addr="00002000" rw_flags="RW" width="1" name="COEX_RF_DEBUG_SEL" comment="Coexistence RFIC debug mux select."/>
|
||||
<register addr="00002004" rw_flags="RW" width="1" name="COEX_RF_CFG" comment="Coexistence RFIC configuration."/>
|
||||
<register addr="00002008" rw_flags="RW" width="1" name="COEX_RF_SW_RESET" comment="Software reset of Coexistence RFIC digital."/>
|
||||
<register addr="0000200c" rw_flags="RW" width="4" name="COEX_RF_ARB_CFG" comment=""/>
|
||||
<register addr="00002010" rw_flags="RW" width="4" name="COEX_RF_TRAN_CTRL_CFG" comment="Coexistence Transition Control configuration."/>
|
||||
<register addr="00002014" rw_flags="RW" width="4" name="COEX_RF_SH_STATIC_CTRL0" comment=""/>
|
||||
<register addr="00002018" rw_flags="RW" width="4" name="COEX_RF_SH_STATIC_CTRL1" comment=""/>
|
||||
<register addr="0000201c" rw_flags="RW" width="4" name="COEX_RF_LO_LDOREG_CFG1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="00002020" rw_flags="RW" width="2" name="COEX_RF_SHRX_CFG" comment=""/>
|
||||
<register addr="00002024" rw_flags="RW" width="1" name="COEX_RF_SHTX_CFG" comment="Coexistence Shared Tx Mux configuration."/>
|
||||
<register addr="00002028" rw_flags="RW" width="1" name="COEX_RF_FEC_IDLE_2G_CFG" comment="RF Switch configuration to use when both WLAN/BT radios are idle at 2G."/>
|
||||
<register addr="0000202c" rw_flags="RW" width="1" name="COEX_RF_FEC_SH_2G_RX_CFG" comment="RF Switch configuration to use when WLAN/BT are simultaneously receiving at 2G."/>
|
||||
<register addr="00002030" rw_flags="RW" width="1" name="COEX_RF_FEC_WL_2G_TX_CFG" comment="RF Switch configuration to use when WLAN is transmitting at 2G."/>
|
||||
<register addr="00002034" rw_flags="RW" width="1" name="COEX_RF_FEC_BT_TX_CFG" comment="RF Switch configuration to use when BT is transmitting."/>
|
||||
<register addr="00002038" rw_flags="RW" width="1" name="COEX_RF_FEC_WL_2G_DCOC_CFG" comment="RF Switch configuration to use during WLAN 2G DCOC."/>
|
||||
<register addr="0000203c" rw_flags="RW" width="1" name="COEX_RF_FEC_WL_2G_DPD_CFG" comment="RF Switch configuration to use during WLAN 2G DPD training."/>
|
||||
<register addr="00002040" rw_flags="RW" width="1" name="COEX_RF_FEC_IDLE_5G_CFG" comment="RF Switch configuration to use when WLAN is idle at 5G (or operating in 2G band)."/>
|
||||
<register addr="00002044" rw_flags="RW" width="1" name="COEX_RF_FEC_WL_5G_TX_CFG" comment="RF Switch configuration to use when WLAN is transmitting at 5G."/>
|
||||
<register addr="00002048" rw_flags="RW" width="1" name="COEX_RF_FEC_WL_5G_RX_CFG" comment="RF Switch configuration to use when WLAN is receiving at 5G."/>
|
||||
<register addr="0000204c" rw_flags="RW" width="1" name="COEX_RF_FEC_WL_5G_DCOC_CFG" comment="RF Switch configuration to use during WLAN 5G DCOC."/>
|
||||
<register addr="00002050" rw_flags="RW" width="1" name="COEX_RF_FEC_WL_5G_DPD_CFG" comment="RF Switch configuration to use during WLAN 5G DPD training."/>
|
||||
<register addr="00002054" rw_flags="RW" width="4" name="COEX_RF_PROT_CHANGE_MODE" comment="Set this to 0xDEADBEEF in order to change the analogue protection. Should clear back to 0 after changing mode."/>
|
||||
<register addr="00002058" rw_flags="RW" width="1" name="COEX_RF_PROT_CFG" comment="Analogue protection configuration register."/>
|
||||
<register addr="0000205c" rw_flags="RW" width="2" name="AUX_BIST_ADC_CTRL" comment="Control register for auxiliary ADC"/>
|
||||
<register addr="00002060" rw_flags="RW" width="2" name="AUX_BIST_ADC_LEVEL" comment="DAC value driven to auxiliary ADC"/>
|
||||
<register addr="00002064" rw_flags="R" width="2" name="AUX_BIST_ADC_STATUS" comment="Returns the data from auxiliary ADC"/>
|
||||
<register addr="00002068" rw_flags="RW" width="2" name="BTWL_BIST_ADC_CTRL" comment="Control register for auxiliary ADC"/>
|
||||
<register addr="0000206c" rw_flags="RW" width="2" name="BTWL_BIST_ADC_LEVEL" comment="DAC value driven to auxiliary ADC"/>
|
||||
<register addr="00002070" rw_flags="R" width="2" name="BTWL_BIST_ADC_STATUS" comment="Returns the data from auxiliary ADC"/>
|
||||
<register addr="00002074" rw_flags="RW" width="4" name="RFIC_DEBUG_CFG" comment="BTWL Debug Config"/>
|
||||
<register addr="00002078" rw_flags="RW" width="4" name="RFIC_DEBUG_CFG2" comment="BTWL Debug Config register 2"/>
|
||||
<register addr="0000207c" rw_flags="RW" width="4" name="RFIC_DEBUG_CFG3" comment="BTWL Debug Config register 3"/>
|
||||
<register addr="00002080" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_DBG0" comment="Debug Mux for pin"/>
|
||||
<register addr="00002084" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_DBG1" comment="Debug Mux for pin"/>
|
||||
<register addr="00002088" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_DBG2" comment="Debug Mux for pin"/>
|
||||
<register addr="0000208c" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_DBG3" comment="Debug Mux for pin"/>
|
||||
<register addr="00002090" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_WL_SPDY_M" comment="Debug Mux for pin"/>
|
||||
<register addr="00002094" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_WL_SPDY_S" comment="Debug Mux for pin"/>
|
||||
<register addr="00002098" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_BT_SPDY_M" comment="Debug Mux for pin"/>
|
||||
<register addr="0000209c" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_BT_SPDY_S" comment="Debug Mux for pin"/>
|
||||
<register addr="000020a0" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_FM_SPDY_S" comment="Debug Mux for pin"/>
|
||||
<register addr="000020a4" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_FEM0" comment="Debug Mux for pin"/>
|
||||
<register addr="000020a8" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_FEM1" comment="Debug Mux for pin"/>
|
||||
<register addr="000020ac" rw_flags="RW" width="4" name="RFIC_DEBUG_MUX_SERIAL_BT" comment="Serialiser control for BT Debug bus"/>
|
||||
<register addr="000020b0" rw_flags="RW" width="4" name="RFIC_DEBUG_MUX_SERIAL_WL" comment="Serialiser control for WLan Debug bus"/>
|
||||
<register addr="000020b4" rw_flags="RW" width="4" name="RFIC_DEBUG_MUX_SERIAL_COEX" comment="Serialiser control for Coex Debug bus"/>
|
||||
<register addr="000020b8" rw_flags="RW" width="4" name="RFIC_DEBUG_MUX_SERIAL_MISC" comment="Serialiser control for Misc Debug bus"/>
|
||||
<register addr="000020bc" rw_flags="RW" width="2" name="RFIC_DEBUG_MUX_SERIAL_DATA" comment="Not used"/>
|
||||
<register addr="000020c0" rw_flags="R" width="2" name="RFIC_DEBUG_PAD_SDR_STATUS" comment="Debug Pad Inputs"/>
|
||||
<register addr="000020c4" rw_flags="R" width="2" name="RFIC_DEBUG_PAD_DDR_STATUS" comment="Debug Pad DDR Inputs"/>
|
||||
<register addr="000020c8" rw_flags="RW" width="1" name="RFIC_DEBUG_ACC_ADDR" comment="Debug Acc Addr"/>
|
||||
<register addr="000020cc" rw_flags="RW" width="4" name="RFIC_DEBUG_ACC_WDATA" comment="Debug Acc Write Data"/>
|
||||
<register addr="000020d0" rw_flags="R" width="4" name="RFIC_DEBUG_ACC_RDATA" comment="Debug Acc Read Data"/>
|
||||
<register addr="000020d4" rw_flags="R" width="2" name="RFIC_DEBUG_STATUS" comment="Main Debug Status register"/>
|
||||
<register addr="000020d8" rw_flags="RW" width="2" name="RFIC_DEBUG_WL_SPEEDY_S_MON_CTRL" comment="WL Speedy Slave Monitor Ctrl"/>
|
||||
<register addr="000020dc" rw_flags="RW" width="4" name="RFIC_DEBUG_WL_SPEEDY_M_MON_CTRL" comment="WL Speedy Master Monitor Ctrl"/>
|
||||
<register addr="000020e0" rw_flags="R" width="4" name="RFIC_DEBUG_WL_SPEEDY_MON_STATUS" comment="WL Speedy Monitor Status"/>
|
||||
<register addr="000020e4" rw_flags="RW" width="2" name="RFIC_DEBUG_BT_SPEEDY_S_MON_CTRL" comment="BT Speedy Slave Monitor Ctrl"/>
|
||||
<register addr="000020e8" rw_flags="RW" width="4" name="RFIC_DEBUG_BT_SPEEDY_M_MON_CTRL" comment="BT Speedy Master Monitor Ctrl"/>
|
||||
<register addr="000020ec" rw_flags="R" width="4" name="RFIC_DEBUG_BT_SPEEDY_MON_STATUS" comment="BT Speedy Monitor Status"/>
|
||||
<register addr="000020f0" rw_flags="RW" width="2" name="RFIC_DEBUG_ACC_TIMER" comment="Timer"/>
|
||||
<register addr="000020f4" rw_flags="R" width="4" name="RFIC_DEBUG_ACC_STATUS" comment="Status information for Debug Acc"/>
|
||||
<register addr="000020f8" rw_flags="RW" width="4" name="RFIC_MON_BT_DA_INV0" comment="Optional invert for each BT DA dynamic signal, excluding Dynamic Enables from timers"/>
|
||||
<register addr="000020fc" rw_flags="RW" width="4" name="RFIC_MON_WL_DA_INV0" comment="Optional invert for each WL DA dynamic signal, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002100" rw_flags="RW" width="4" name="RFIC_MON_WL_DA_INV1" comment="Optional invert for each WL DA dynamic signal, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002104" rw_flags="RW" width="4" name="RFIC_MON_WL_DA_INV2" comment="Optional invert for each WL DA dynamic signal, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002108" rw_flags="RW" width="4" name="RFIC_MON_COEX_DA_INV0" comment="Optional invert for each SH DA dynamic signal, excluding Dynamic Enables from timers"/>
|
||||
<register addr="0000210c" rw_flags="RW" width="4" name="RFIC_MON_COEX_DA_INV1" comment="Optional invert for each SH DA dynamic signal, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002110" rw_flags="RW" width="4" name="RFIC_MON_BT_DA_OFF0" comment="Set to turn off drive of each BT DA dynamic signal from core, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002114" rw_flags="RW" width="4" name="RFIC_MON_WL_DA_OFF0" comment="Set to turn off drive of each WL DA dynamic signal from core, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002118" rw_flags="RW" width="4" name="RFIC_MON_WL_DA_OFF1" comment="Set to turn off drive of each WL DA dynamic signal from core, excluding Dynamic Enables from timers"/>
|
||||
<register addr="0000211c" rw_flags="RW" width="4" name="RFIC_MON_WL_DA_OFF2" comment="Set to turn off drive of each WL DA dynamic signal from core, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002120" rw_flags="RW" width="4" name="RFIC_MON_COEX_DA_OFF0" comment="Set to turn off drive of each SH DA dynamic signal from core, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002124" rw_flags="RW" width="4" name="RFIC_MON_COEX_DA_OFF1" comment="Set to turn off drive of each SH DA dynamic signal from core, excluding Dynamic Enables from timers"/>
|
||||
<register addr="00002128" rw_flags="R" width="4" name="RFIC_MON_BT_AD0" comment="Monitor BT AD signals right at the AD interface"/>
|
||||
<register addr="0000212c" rw_flags="R" width="4" name="RFIC_MON_WL_AD0" comment="Monitor WL AD signals right at the AD interface"/>
|
||||
<register addr="00002130" rw_flags="R" width="4" name="RFIC_MON_WL_AD1" comment="Monitor WL AD signals right at the AD interface"/>
|
||||
<register addr="00002134" rw_flags="R" width="4" name="RFIC_MON_WL_AD2" comment="Monitor WL AD signals right at the AD interface"/>
|
||||
<register addr="00002138" rw_flags="R" width="4" name="RFIC_MON_COEX_AD0" comment="Monitor SH AD signals right at the AD interface"/>
|
||||
<register addr="0000213c" rw_flags="R" width="4" name="RFIC_MON_RS_ACC_BUF" comment="Rs Accumulation Buffer register"/>
|
||||
<register addr="00002140" rw_flags="R" width="2" name="RFIC_MON_RS_ACC_BUF2" comment="Rs Accumulation Buffer register2"/>
|
||||
</block>
|
||||
<block name="rfic_pad_control" comment="">
|
||||
<register addr="00001000" rw_flags="RW" width="1" name="PAD_CONTROL_FEM_CTRL0" comment="Control register for pad FEM_CTRL0"/>
|
||||
<register addr="00001004" rw_flags="RW" width="1" name="PAD_CONTROL_FEM_CTRL1" comment="Control register for pad FEM_CTRL1"/>
|
||||
<register addr="00001008" rw_flags="RW" width="1" name="PAD_CONTROL_FM_SPDY_S" comment="Control register for pad FM_SPDY_S"/>
|
||||
<register addr="0000100c" rw_flags="RW" width="1" name="PAD_CONTROL_BT_SPDY_M" comment="Control register for pad BT_SPDY_M"/>
|
||||
<register addr="00001010" rw_flags="RW" width="1" name="PAD_CONTROL_WL_SPDY_S" comment="Control register for pad WL_SPDY_S"/>
|
||||
<register addr="00001014" rw_flags="RW" width="1" name="PAD_CONTROL_BT_SPDY_S" comment="Control register for pad BT_SPDY_S"/>
|
||||
<register addr="00001018" rw_flags="RW" width="1" name="PAD_CONTROL_WL_SPDY_M" comment="Control register for pad WL_SPDY_M"/>
|
||||
</block>
|
||||
<block name="wlrf_radio" comment="">
|
||||
<register addr="00004000" rw_flags="RW" width="1" name="WLRF_RADIO_LNA_RSSI_THRESH_EXT_LOUD" comment="This register specifies the threshold value for the LNA RSSI module, turning off external LNA indication"/>
|
||||
<register addr="00004004" rw_flags="RW" width="1" name="WLRF_RADIO_LNA_RSSI_THRESH_LOUD" comment="This register specifies the threshold value for the LNA RSSI module, too loud indication (- 6dB gain change request)"/>
|
||||
<register addr="00004008" rw_flags="RW" width="1" name="WLRF_RADIO_LNA_RSSI_THRESH_V_LOUD" comment="This register specifies the threshold value for the LNA RSSI module, extra loud indication (-12dB gain change request)"/>
|
||||
<register addr="0000400c" rw_flags="RW" width="2" name="WLRF_RADIO_MIX_RSSI_THRESH_WEAK" comment="This register specifies the threshold value for the Mixer RSSI module, too weak indication (+ 6dB gain change request)"/>
|
||||
<register addr="00004010" rw_flags="RW" width="2" name="WLRF_RADIO_MIX_RSSI_THRESH_LOUD" comment="This register specifies the threshold value for the Mixer RSSI module, too loud indication (- 6dB gain change request)"/>
|
||||
<register addr="00004014" rw_flags="RW" width="2" name="WLRF_RADIO_MIX_RSSI_THRESH_V_LOUD" comment="This register specifies the threshold value for the Mixer RSSI module, extra loud indication (-12dB gain change request)"/>
|
||||
<register addr="00004018" rw_flags="RW" width="2" name="WLRF_RADIO_ABB_RSSI_THRESH_WEAK" comment="This register specifies the threshold value for the ABB RSSI module, too weak indication (+ 1.5dB gain change request)"/>
|
||||
<register addr="0000401c" rw_flags="RW" width="2" name="WLRF_RADIO_ABB_RSSI_THRESH_LOUD" comment="This register specifies the threshold value for the ABB RSSI module, too loud indication (- 6dB gain change request)"/>
|
||||
<register addr="00004020" rw_flags="RW" width="2" name="WLRF_RADIO_ABB_RSSI_THRESH_V_LOUD" comment="This register specifies the threshold value for the ABB RSSI module, extra loud indication (-12dB gain change request)"/>
|
||||
<register addr="00004024" rw_flags="R" width="2" name="WLRF_RADIO_RX_RSSI" comment="This register contains the RSSI of the receive chain. The lower byte is the 8 bit digital RSSI (fixed to 0 since this is a radio-only chip) and the upper byte is the final analogue gain in 3dB steps."/>
|
||||
<register addr="00004028" rw_flags="R" width="1" name="WLRF_RSSI_FILTERED_STATUS" comment="This register contains the analogue RSSI values for the receive chain, after initial processing in the rssi blocks block."/>
|
||||
<register addr="0000402c" rw_flags="RW" width="4" name="WLRF_WB_RSSI_LUT0" comment="First 6 locations of LUT used to generate RSSI values for WB RSSI. Note that fields are 5 bits but only LS 4 bits are used"/>
|
||||
<register addr="00004030" rw_flags="RW" width="4" name="WLRF_WB_RSSI_LUT1" comment="Last 6 locations of LUT used to generate RSSI values for WB RSSI. Note that fields are 5 bits but only LS 4 bits are used"/>
|
||||
<register addr="00004034" rw_flags="RW" width="4" name="WLRF_IB_RSSI_LUT0" comment="First 6 locations of LUT used to generate RSSI values for IB RSSI"/>
|
||||
<register addr="00004038" rw_flags="RW" width="4" name="WLRF_IB_RSSI_LUT1" comment="Last 6 locations of LUT used to generate RSSI values for IB RSSI"/>
|
||||
<register addr="0000403c" rw_flags="RW" width="4" name="WLRF_ABB_RSSI_LUT0" comment="First 6 locations of LUT used to generate RSSI values for ABB RSSI"/>
|
||||
<register addr="00004040" rw_flags="RW" width="4" name="WLRF_ABB_RSSI_LUT1" comment="Last 6 locations of LUT used to generate RSSI values for ABB RSSI"/>
|
||||
<register addr="00004044" rw_flags="RW" width="4" name="WLRF_RADIO_AGC_CONFIG1" comment="Miscellaneous config bits for the AGC as follows:"/>
|
||||
<register addr="00004048" rw_flags="RW" width="4" name="WLRF_RADIO_AGC_CONFIG2" comment="Configuration bits for the AGC: gains ranges definition. valid when AGC is active, and gain not forced."/>
|
||||
<register addr="0000404c" rw_flags="RW" width="2" name="WLRF_RADIO_RX_LEVEL" comment="This register contains the value to be sent to the analogue gain stages if the AGC is disabled."/>
|
||||
<register addr="00004050" rw_flags="R" width="2" name="WLRF_RADIO_GAIN_STATUS" comment="This register contains the current gain settings to all blocks in the analogue front end"/>
|
||||
<register addr="00004054" rw_flags="RW" width="4" name="WLRF_ANA_LNA_TRIM_LUT" comment="This register defines the LUT used to generate ZIN_TRIM values for 2G5 LNAs"/>
|
||||
<register addr="00004058" rw_flags="RW" width="1" name="WLRF_DEBUG_SELECT" comment="Selects which debug appears on the output of the WLAN block"/>
|
||||
<register addr="0000405c" rw_flags="R" width="2" name="WLRF_DEBUG_STATUS" comment="Returns the current value on the debug bus"/>
|
||||
<register addr="00004060" rw_flags="RW" width="1" name="WLRF_RADIO_CONFIG" comment="Miscellaneous config bits"/>
|
||||
<register addr="00004064" rw_flags="RW" width="4" name="WLRF_RADIO_TEMP_CTRL_CONFIG" comment="Control register for block interfacing to analogue temperature sensor"/>
|
||||
<register addr="00004068" rw_flags="RW" width="2" name="WLRF_ANA_INT_CFG" comment="Configure source for WL status interrupts"/>
|
||||
<register addr="0000406c" rw_flags="R" width="1" name="WLRF_ANA_INT_STATUS" comment="WL Status Interrupt status"/>
|
||||
<register addr="00004070" rw_flags="R" width="4" name="WLRF_ANA_RAW_INT_STATUS" comment="Raw status from the analogue module - intended for hardware debug"/>
|
||||
<register addr="00004074" rw_flags="R" width="2" name="WLRF_RADIO_TEMP" comment="Radio temperature, as measured by analogue sensors near PA"/>
|
||||
<register addr="00004078" rw_flags="R" width="4" name="WLRF_ANA_STATUS" comment="Returns the value on the ANA_STATUS bus"/>
|
||||
<register addr="0000407c" rw_flags="R" width="4" name="WLRF_ANA_RSSI_STATUS" comment="This register contains the raw analogue RSSI values for the receive chain"/>
|
||||
<register addr="00004080" rw_flags="R" width="4" name="WLRF_ANA_ENABLES_STATUS" comment="This register contains the current values of the Analogue Enables, after all masking and multiplexing."/>
|
||||
<register addr="00004084" rw_flags="RW" width="4" name="WLRF_ANA_ENABLES" comment="Default values for analogue enables signals should the mask register select this rather than the timer outputs"/>
|
||||
<register addr="00004088" rw_flags="RW" width="4" name="WLRF_ANA_ENABLES_MASK" comment="Selects use of ANA_ENABLES or timer outputs. A 1 in a given bit selects the timer output."/>
|
||||
<register addr="0000408c" rw_flags="RW" width="4" name="WLRF_ANA_TRAINING_ENABLES_MASK" comment="This masks the output of the Tx timer when it is not a DPD training frame. The idea is to be able to remove the extra Rx enables that are required for making DPD training work to improve power consumption on frames that don't need them. It should typically have all the Tx bits set and none of the Rx bits."/>
|
||||
<register addr="00004090" rw_flags="R" width="1" name="WLRF_ANA_TIMER_TX_SLOT" comment="This register contains the current slot selected by the Tx timer"/>
|
||||
<register addr="00004094" rw_flags="R" width="1" name="WLRF_ANA_TIMER_RX_SLOT" comment="This register contains the current slot selected by the Rx timer"/>
|
||||
<register addr="00004098" rw_flags="RW" width="4" name="WLRF_ANA_TRIM_TX" comment="This register sets the modulation dependent analogue trims in low power mode and when Ana Tx Test Mode is selected (in WLRF_RADIO_CONFIG register)"/>
|
||||
<register addr="0000409c" rw_flags="RW" width="4" name="WLRF_ANA_TX_CCK_TRIM_CONF" comment="CCK modulation dependent analogue trims"/>
|
||||
<register addr="000040a0" rw_flags="RW" width="4" name="WLRF_ANA_TX_OFDM0_TRIM_CONF" comment="OFDM modulation dependent analogue trims when corresponding bit in WL_RADIO_TX_CTRL_ANA_OFDM_SEL is set to 0"/>
|
||||
<register addr="000040a4" rw_flags="RW" width="4" name="WLRF_ANA_TX_OFDM1_TRIM_CONF" comment="OFDM modulation dependent analogue trims when corresponding bit in WL_RADIO_TX_CTRL_ANA_OFDM_SEL is set to 1"/>
|
||||
<register addr="000040a8" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT0_ENABLES" comment="This register sets the radio enables for transmit timer slot 0."/>
|
||||
<register addr="000040ac" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT1_ENABLES" comment="This register sets the radio enables for transmit timer slot 1."/>
|
||||
<register addr="000040b0" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT2_ENABLES" comment="This register sets the radio enables for transmit timer slot 2."/>
|
||||
<register addr="000040b4" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT3_ENABLES" comment="This register sets the radio enables for transmit timer slot 3."/>
|
||||
<register addr="000040b8" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT4_ENABLES" comment="This register sets the radio enables for transmit timer slot 4."/>
|
||||
<register addr="000040bc" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT5_ENABLES" comment="This register sets the radio enables for transmit timer slot 5."/>
|
||||
<register addr="000040c0" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT6_ENABLES" comment="This register sets the radio enables for transmit timer slot 6."/>
|
||||
<register addr="000040c4" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_TX_SLOT7_ENABLES" comment="This register sets the radio enables for transmit timer slot 7."/>
|
||||
<register addr="000040c8" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT0_DELAY" comment="This register sets the delay from Tx timer enable to slot 0 becoming active in 50ns units"/>
|
||||
<register addr="000040cc" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT1_DELAY" comment="This register sets the delay from Tx timer enable to slot 1 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="000040d0" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT2_DELAY" comment="This register sets the delay from Tx timer enable to slot 2 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="000040d4" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT3_DELAY" comment="This register sets the delay from Tx timer enable to slot 3 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="000040d8" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT4_DELAY" comment="This register sets the delay from Tx timer enable to slot 4 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="000040dc" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT5_DELAY" comment="This register sets the delay from Tx timer enable to slot 5 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="000040e0" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT6_DELAY" comment="This register sets the delay from Tx timer enable to slot 6 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="000040e4" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_TX_SLOT7_DELAY" comment="This register sets the delay from Tx timer enable to slot 7 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="000040e8" rw_flags="RW" width="2" name="WLRF_ANA_TIMER_TX_SLOT_ON_OFF_LAST" comment="This register sets the start and end of Tx turn on and off ramps, and the slot jumped to in the case of a Tx abort"/>
|
||||
<register addr="000040ec" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT0_ENABLES" comment="This register sets the radio enables for receive timer slot 0."/>
|
||||
<register addr="000040f0" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT1_ENABLES" comment="This register sets the radio enables for receive timer slot 1."/>
|
||||
<register addr="000040f4" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT2_ENABLES" comment="This register sets the radio enables for receive timer slot 2."/>
|
||||
<register addr="000040f8" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT3_ENABLES" comment="This register sets the radio enables for receive timer slot 3."/>
|
||||
<register addr="000040fc" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT4_ENABLES" comment="This register sets the radio enables for receive timer slot 4."/>
|
||||
<register addr="00004100" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT5_ENABLES" comment="This register sets the radio enables for receive timer slot 5."/>
|
||||
<register addr="00004104" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT6_ENABLES" comment="This register sets the radio enables for receive timer slot 6."/>
|
||||
<register addr="00004108" rw_flags="RW" width="4" name="WLRF_ANA_TIMER_RX_SLOT7_ENABLES" comment="This register sets the radio enables for receive timer slot 7."/>
|
||||
<register addr="0000410c" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT0_DELAY" comment="This register sets the delay from Rx timer enable to slot 0 becoming active in 50ns units"/>
|
||||
<register addr="00004110" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT1_DELAY" comment="This register sets the delay from Rx timer enable to slot 1 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="00004114" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT2_DELAY" comment="This register sets the delay from Rx timer enable to slot 2 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="00004118" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT3_DELAY" comment="This register sets the delay from Rx timer enable to slot 3 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="0000411c" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT4_DELAY" comment="This register sets the delay from Rx timer enable to slot 4 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="00004120" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT5_DELAY" comment="This register sets the delay from Rx timer enable to slot 5 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="00004124" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT6_DELAY" comment="This register sets the delay from Rx timer enable to slot 6 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="00004128" rw_flags="RW" width="1" name="WLRF_ANA_TIMER_RX_SLOT7_DELAY" comment="This register sets the delay from Rx timer enable to slot 7 becoming active in 50ns units. NOTE that if the delay is less than the previous slot, the timer will wrap, allowing delays up to 12.8us to be selected."/>
|
||||
<register addr="0000412c" rw_flags="RW" width="2" name="WLRF_ANA_TIMER_RX_SLOT_ON_OFF_LAST" comment="This register sets the start and end of Rx turn on and off ramps, and the slot jumped to in the case of an Rx abort"/>
|
||||
<register addr="00004130" rw_flags="RW" width="2" name="WLRF_5G_TRIM_LUT0" comment="Values for LNA 5G trim buses when LNA gain is 0"/>
|
||||
<register addr="00004134" rw_flags="RW" width="2" name="WLRF_5G_TRIM_LUT1" comment="Values for LNA 5G trim buses when LNA gain is 1"/>
|
||||
<register addr="00004138" rw_flags="RW" width="2" name="WLRF_5G_TRIM_LUT2" comment="Values for LNA 5G trim buses when LNA gain is 2"/>
|
||||
<register addr="0000413c" rw_flags="RW" width="2" name="WLRF_5G_TRIM_LUT3" comment="Values for LNA 5G trim buses when LNA gain is 3"/>
|
||||
<register addr="00004140" rw_flags="RW" width="2" name="WLRF_5G_TRIM_LUT4" comment="Values for LNA 5G trim buses when LNA gain is 4"/>
|
||||
<register addr="00004144" rw_flags="RW" width="1" name="WLRF_INT_CLEAR" comment="Writing this register clears any interrupts whose corresponding bits are set in the write data. Bit allocations are as for WL_RF_INT_MASK"/>
|
||||
<register addr="00004148" rw_flags="RW" width="1" name="WLRF_INT_MASK" comment="This register masks events from causing interrupts. Only those interrupts whose mask bit is set will be delivered to the processors"/>
|
||||
<register addr="0000414c" rw_flags="R" width="2" name="WLRF_INT_STATUS" comment="This register has bits set in it for any interrupt that is currently active. In addition 'raw' bits are set for any active interrupt, whether it is masked or not"/>
|
||||
<register addr="00004150" rw_flags="RW" width="1" name="WL_ANA_BIAS_EN" comment="This register controls enabling of bias blocks within WLAN analogue"/>
|
||||
<register addr="00004154" rw_flags="RW" width="4" name="WL_ANA_TEST_EN" comment="This register controls enabling of test facilities"/>
|
||||
<register addr="00004158" rw_flags="RW" width="4" name="WL_ANA_DCOC_CTRL" comment="This register controls the DC offset compensation block"/>
|
||||
<register addr="0000415c" rw_flags="RW" width="4" name="WL_ANA_DCOC_CAL_GAINS" comment="This register contains the gains used during the calibration process by the DC offset compensation block"/>
|
||||
<register addr="00004160" rw_flags="RW" width="4" name="WL_ANA_DCOC_OVERRIDE" comment="This register controls the DC offset compensation block"/>
|
||||
<register addr="00004164" rw_flags="RW" width="4" name="WL_ANA_DCOC_OFFSET" comment="This register controls the DC offset compensation block fixed offsets"/>
|
||||
<register addr="00004168" rw_flags="RW" width="2" name="WL_ANA_ABB_DCOC_I_LUT" comment="This register is used to write the LUT that contains the DC offset values for the I receive channel. The location accessed is set by the current LNA and mixer gain"/>
|
||||
<register addr="0000416c" rw_flags="RW" width="2" name="WL_ANA_ABB_DCOC_Q_LUT" comment="This register is used to write the LUT that contains the DC offset values for the Q receive channel. The location accessed is set by the current LNA and mixer gain"/>
|
||||
<register addr="00004170" rw_flags="R" width="4" name="WL_ANA_ABB_DCOC_LUT_STATUS" comment="This register returns the value of the DC offset for the LUT entry corresponding to the current gain"/>
|
||||
<register addr="00004174" rw_flags="RW" width="4" name="WL_ANA_ABB_RX_CONFIG1" comment="This register controls Rx baseband"/>
|
||||
<register addr="00004178" rw_flags="RW" width="4" name="WL_ANA_ABB_RX_CONFIG2" comment="This register controls Rx baseband"/>
|
||||
<register addr="0000417c" rw_flags="RW" width="4" name="WL_ANA_ABB_RX_CONFIG3" comment="This register controls Rx baseband"/>
|
||||
<register addr="00004180" rw_flags="RW" width="2" name="WL_ANA_ABB_RX_CONFIG4" comment="This register controls Rx baseband"/>
|
||||
<register addr="00004184" rw_flags="RW" width="4" name="WL_ANA_ABB_RX_RSSI_CONFIG" comment="This register controls Rx RSSI blocks"/>
|
||||
<register addr="00004188" rw_flags="RW" width="4" name="WL_ANA_ABB_TX_CONFIG" comment="This register controls Rx baseband"/>
|
||||
<register addr="0000418c" rw_flags="RW" width="4" name="WL_ANA_ABB_PERIPH_CONFIG" comment="This register controls the peripheral block"/>
|
||||
<register addr="00004190" rw_flags="RW" width="4" name="WL_ANA_2G_RX_RF_CONFIG" comment="This register controls the 2G Rx RF block"/>
|
||||
<register addr="00004194" rw_flags="RW" width="2" name="WL_ANA_5G_RX_LNA_CONFIG" comment="This register controls the 5G Rx LNA block"/>
|
||||
<register addr="00004198" rw_flags="RW" width="4" name="WL_ANA_5G_RX_MIX_CONFIG" comment="This register controls the 5G Rx mixer block"/>
|
||||
<register addr="0000419c" rw_flags="RW" width="2" name="WL_ANA_RX_RF_MISC_CONFIG" comment="This register controls miscellaneous Rx RF features"/>
|
||||
<register addr="000041a0" rw_flags="RW" width="4" name="WL_ANA_TX_2G_MISC_CONFIG" comment="This register controls miscellaneous Tx RF features"/>
|
||||
<register addr="000041a4" rw_flags="RW" width="4" name="WL_ANA_TX_5G_MISC_CONFIG" comment="This register controls miscellaneous Tx RF features"/>
|
||||
<register addr="000041a8" rw_flags="RW" width="4" name="WL_ANA_TX_2G_MIX_DRV_CONFIG" comment="This register controls the Tx RF mixer and driver blocks"/>
|
||||
<register addr="000041ac" rw_flags="RW" width="4" name="WL_ANA_TX_5G_MIX_DRV_CONFIG" comment="This register controls the Tx RF mixer and driver blocks"/>
|
||||
<register addr="000041b0" rw_flags="RW" width="2" name="WL_ANA_TX_RF_PA_PROT_CONFIG" comment="This register controls the Tx RF PA and protection blocks"/>
|
||||
<register addr="000041b4" rw_flags="RW" width="4" name="WL_ANA_LO_TOP" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041b8" rw_flags="RW" width="4" name="WL_ANA_LO_CLKREF_ADC" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041bc" rw_flags="RW" width="4" name="WL_ANA_LO_D_FREQ1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041c0" rw_flags="RW" width="4" name="WL_ANA_LO_D_FREQ2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041c4" rw_flags="RW" width="1" name="WL_ANA_LO_PLL_STOP" comment="This register written to stop the PLL from running"/>
|
||||
<register addr="000041c8" rw_flags="RW" width="4" name="WL_ANA_LO_DPLL_CONF1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041cc" rw_flags="RW" width="4" name="WL_ANA_LO_PU_TDC_CONF" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041d0" rw_flags="RW" width="4" name="WL_ANA_LO_DCO_CONF1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041d4" rw_flags="RW" width="4" name="WL_ANA_LO_DCO_CONF2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041d8" rw_flags="RW" width="4" name="WL_ANA_LO_DPLL_CONF2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041dc" rw_flags="RW" width="4" name="WL_ANA_LO_TDC_NLMEM" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041e0" rw_flags="RW" width="4" name="WL_ANA_LO_PU_DCO_CONF" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041e4" rw_flags="RW" width="4" name="WL_ANA_LO_DCO_OPEN1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041e8" rw_flags="RW" width="4" name="WL_ANA_LO_DCO_OPEN2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041ec" rw_flags="RW" width="4" name="WL_ANA_LO_AREG_CONF" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041f0" rw_flags="RW" width="4" name="WL_ANA_LO_DCO_TEST" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041f4" rw_flags="RW" width="4" name="WL_ANA_LO_LOGEN1" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041f8" rw_flags="RW" width="4" name="WL_ANA_LO_LOGEN2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="000041fc" rw_flags="RW" width="4" name="WL_ANA_LO_LDOREG_CFG2" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="00004200" rw_flags="RW" width="4" name="WL_ANA_LO_DPLL_TEST" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="00004204" rw_flags="RW" width="4" name="WL_ANA_LO_TEST" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="00004208" rw_flags="RW" width="4" name="WL_ANA_LO_PLL_RESV" comment="This register is one of the LO configuration registers"/>
|
||||
<register addr="0000420c" rw_flags="R" width="4" name="WL_ANA_LO_DPLL_TEST_STATUS" comment="This register contains test outputs from the LO"/>
|
||||
</block>
|
||||
</subsystem>
|
||||
1275
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/hardware/moredump/wlan_sys_registers.xml
vendored
Normal file
1275
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/hardware/moredump/wlan_sys_registers.xml
vendored
Normal file
File diff suppressed because it is too large
Load diff
6475
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/hip_signals.xml
vendored
Normal file
6475
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/hip_signals.xml
vendored
Normal file
File diff suppressed because it is too large
Load diff
1
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/id.txt
vendored
Normal file
1
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/id.txt
vendored
Normal file
|
|
@ -0,0 +1 @@
|
|||
2018-07-18 09:41 javadXXdXX_wlanlite_hardmac_ram_gcc_integrated on5 498039157 adm-swbld@camsbugrd009@a3a6dcc086@HEAD (no branch)
|
||||
5175
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/mib_out.xml
vendored
Normal file
5175
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/mib_out.xml
vendored
Normal file
File diff suppressed because it is too large
Load diff
5633
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/symbols.dbg
vendored
Normal file
5633
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/symbols.dbg
vendored
Normal file
File diff suppressed because it is too large
Load diff
2022
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/unicli.dbg
vendored
Normal file
2022
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/unicli.dbg
vendored
Normal file
File diff suppressed because it is too large
Load diff
372
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/unitab.dbg
vendored
Normal file
372
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/unitab.dbg
vendored
Normal file
|
|
@ -0,0 +1,372 @@
|
|||
2 dot11RSNAStatsSTAAddress
|
||||
2 dot11RSNAStatsTKIPICVErrors
|
||||
2 dot11RSNAStatsTKIPLocalMICFailures
|
||||
2 dot11RSNAStatsTKIPRemoteMICFailures
|
||||
2 dot11RSNAStatsCCMPReplays
|
||||
2 dot11RSNAStatsCCMPDecryptErrors
|
||||
2 dot11RSNAStatsTKIPReplays
|
||||
2 dot11RSNAStatsRobustMgmtCCMPReplays
|
||||
0 dot11TDLSPeerUAPSDIndicationWindow
|
||||
0 dot11AssociationSAQueryMaximumTimeout
|
||||
0 dot11AssociationSAQueryRetryTimeout
|
||||
0 dot11PowerCapabilityMaxImplemented
|
||||
0 dot11PowerCapabilityMinImplemented
|
||||
0 dot11RTSThreshold
|
||||
0 dot11ShortRetryLimit
|
||||
0 dot11LongRetryLimit
|
||||
0 dot11FragmentationThreshold
|
||||
0 dot11RTSSuccessCount
|
||||
0 dot11ACKFailureCount
|
||||
0 dot11MulticastReceivedFrameCount
|
||||
0 dot11FCSErrorCount
|
||||
0 dot11WEPUndecryptableCount
|
||||
0 dot11manufacturerProductVersion
|
||||
0 unifiMLMEConnectionTimeOut
|
||||
0 unifiMLMEScanChannelMaxScanTime
|
||||
0 unifiMLMEScanChannelProbeInterval
|
||||
0 unifiMLMEDataReferenceTimeout
|
||||
0 unifiMLMEScanProbeInterval
|
||||
0 unifiMLMEScanHighRSSIThreshold
|
||||
0 unifiMLMEScanDeltaRSSIThreshold
|
||||
0 unifiMLMEScanMaximumAge
|
||||
0 unifiMLMEScanMaximumResults
|
||||
0 unifiMLMEAutonomousScanNoisy
|
||||
0 unifiFirmwareBuildID
|
||||
0 unifiChipVersion
|
||||
0 unifiFirmwarePatchBuildID
|
||||
0 unifiBasicCapabilities
|
||||
0 unifiExtendedCapabilities
|
||||
0 unifiHtCapabilities
|
||||
0 unifiRsnCapabilities
|
||||
0 unifi24G40MHZChannels
|
||||
0 unifiExtendedCapabilitiesDisabled
|
||||
0 unifiTestSetChannelBW
|
||||
0 unifiPLM689WorkaroundEnable
|
||||
0 unifiPLM689WorkaroundTriggerDHCPDiscoverCount
|
||||
0 unifiPLM689WorkaroundTriggerDHCPDiscoverTimeout
|
||||
0 unifiSupportedDataRates
|
||||
0 unifiPLM689WorkaroundAddresses
|
||||
0 unifiRadioMeasurementActivated
|
||||
0 unifiRadioMeasurementCapabilities
|
||||
0 unifiVhtActivated
|
||||
0 unifiHtActivated
|
||||
0 unifiPLM689WorkaroundTriggerStaticIPTimeout
|
||||
0 unifiPLM689WorkaroundTriggerARPCount
|
||||
0 unifiRoamingEnabled
|
||||
0 unifiRssiRoamScanTrigger
|
||||
0 unifiRoamDeltaTrigger
|
||||
0 unifiRoamCachedChannelScanPeriod
|
||||
0 unifiFullRoamScanPeriod
|
||||
0 unifiRoamScanBand
|
||||
0 unifiRoamScanMaxActiveChannelTime
|
||||
0 unifiRoamFullChannelScanFrequency
|
||||
0 unifiRoamMode
|
||||
0 unifiRssiRoamScanNoCandidateDeltaTrigger
|
||||
0 unifiRoamEAPTimeout
|
||||
0 unifiRoamScanControl
|
||||
0 unifiRoamDfsScanMode
|
||||
0 unifiRoamScanHomeTime
|
||||
0 unifiRoamScanHomeAwayTime
|
||||
0 unifiRoamScanNProbe
|
||||
0 unifiApOlbcDuration
|
||||
0 unifiApOlbcInterval
|
||||
0 unifiFrameResponseTimeOut
|
||||
0 unifiConnectionFailureTimeout
|
||||
0 unifiConnectingProbeTimeout
|
||||
0 unifiDisconnectTimeout
|
||||
0 unifiFrameResponseCfmTxLifetimeTimeOut
|
||||
0 unifiFrameResponseCfmFailureTimeOut
|
||||
0 unifiForceActiveDuration
|
||||
0 unifiMLMEScanMaxNumberOfProbeSets
|
||||
0 unifiMLMEScanStopIfLessThanXFrames
|
||||
0 unifiMLMEStationInactivityTimeOut
|
||||
0 unifiMLMECliInactivityTimeOut
|
||||
0 unifiMLMEStationInitialKickTimeOut
|
||||
0 unifiUartConfigure
|
||||
0 unifiUartPios
|
||||
0 unifiClockFrequency
|
||||
0 unifiCrystalFrequencyTrim
|
||||
0 unifiEnableDorm
|
||||
0 unifiDisableDormWhenBtOn
|
||||
0 unifiExternalClockDetect
|
||||
0 unifiExternalFastClockRequest
|
||||
0 unifiWatchdogTimeout
|
||||
0 unifiExternalFastClockRequestPIO
|
||||
0 unifiRSSI
|
||||
0 unifiLastBssRSSI
|
||||
0 unifiSNR
|
||||
0 unifiLastBssSNR
|
||||
0 unifiSwTxTimeout
|
||||
0 unifiHwTxTimeout
|
||||
0 unifiTxDataRate
|
||||
0 unifiSNRExtraOffsetCCK
|
||||
0 unifiRSSIMaxAveragingPeriod
|
||||
0 unifiRSSIMinReceivedFrames
|
||||
0 unifiLastBssTxDataRate
|
||||
0 unifiDiscardedFrameCount
|
||||
0 unifiMacrameDebugStats
|
||||
0 unifiCurrentTSFTime
|
||||
0 unifiBaTxEnableTid
|
||||
0 unifiBaConfig
|
||||
0 unifiMoveBKtoBE
|
||||
0 unifiBeaconReceived
|
||||
0 unifiRadioOnTime
|
||||
0 unifiRadioTxTime
|
||||
0 unifiRadioRxTime
|
||||
0 unifiRadioScanTime
|
||||
0 unifiPSLeakyAP
|
||||
0 unifiTqamActivated
|
||||
0 unifiNoAckActivationCount
|
||||
0 unifiRxFcsErrorCount
|
||||
0 unifiBeaconsReceivedPercentage
|
||||
0 unifiQueueStatsEnable
|
||||
0 unifiDpdMasterSwitch
|
||||
0 unifiGoogleMaxNumberOfPeriodicScans
|
||||
0 unifiGoogleMaxRSSISampleSize
|
||||
0 unifiGoogleMaxHotlistAPs
|
||||
0 unifiGoogleMaxSignificantWifiChangeAPs
|
||||
0 unifiGoogleMaxBssidHistoryEntries
|
||||
0 unifiMacBeaconTimeout
|
||||
0 UnifiRoamTrackingScanPeriod
|
||||
0 unifiRoamCuLocal
|
||||
0 unifiCuRoamScanNoCandidateDeltaTrigger
|
||||
0 unifiRoamAPSelectDeltaFactor
|
||||
0 unifiCURoamweight
|
||||
0 unifiRSSIRoamweight
|
||||
0 unifiRoamBSSLoadMonitoringFrequency
|
||||
0 unifiCUMeasurementInterval
|
||||
0 unifiCurrentBssNss
|
||||
0 unifiAPMimoUsed
|
||||
0 unifiRoamOffloaded4wshkTimeout
|
||||
0 unifiRoamingCount
|
||||
0 unifiRoamingAKM
|
||||
0 unifiCurrentBssBandwidth
|
||||
0 unifiCurrentBssChannelFrequency
|
||||
0 unifiLoggerEnabled
|
||||
0 unifiMaPacketFateEnabled
|
||||
0 unifiCSROnlyEIFSDuration
|
||||
0 unifiOverrideDefaultBETXOPForHT
|
||||
0 unifiOverrideDefaultBETXOP
|
||||
0 unifiRXABBTrimSettings
|
||||
0 unifiRadioTrimsEnable
|
||||
0 unifiHardwarePlatform
|
||||
0 unifiForceChannelBW
|
||||
0 unifiDPDTrainingDuration
|
||||
0 unifiCoexDebugOverrideBt
|
||||
0 unifiFastPowerSaveTimeout
|
||||
0 unifiFastPowerSaveTimeOutSmall
|
||||
0 unifiMLMESTAKeepAliveTimeout
|
||||
0 unifiMLMEAPKeepAliveTimeout
|
||||
0 unifiMLMEGOKeepAliveTimeout
|
||||
0 unifiSTARouterAdvertisementMinimumIntervalToForward
|
||||
0 unifiRoamConnectionQualityCheckWaitAfterConnect
|
||||
0 unifiApBeaconMaxDrift
|
||||
0 unifiBSSMaxIdlePeriodEnabled
|
||||
0 unifiVifIdleMonitorTime
|
||||
0 unifiDisableLegacyPowerSave
|
||||
0 unifiDebugForceActive
|
||||
0 unifiStationActivityIdleTime
|
||||
0 unifiPowerManagementDelayTimeout
|
||||
0 unifiAPSDServicePeriodTimeout
|
||||
0 unifiConcurrentPowerManagementDelayTimeout
|
||||
0 unifiStationQosInfo
|
||||
0 unifiListenIntervalSkippingDTIM
|
||||
0 unifiListenInterval
|
||||
0 unifiLegacyPsPollTimeout
|
||||
0 unifiTogglePowerDomain
|
||||
0 unifiP2PListenIntervalSkippingDTIM
|
||||
0 unifiFragmentationDuration
|
||||
0 unifiIdleModeLiteEnabled
|
||||
0 unifiIdleModeEnabled
|
||||
0 unifiDTIMWaitTimeout
|
||||
0 unifiListenIntervalMaxTime
|
||||
0 unifiScanMaxProbeTransmitLifetime
|
||||
0 unifiPowerSaveTransitionPacketThreshold
|
||||
0 unifiProbeResponseLifetime
|
||||
0 unifiProbeResponseMaxRetry
|
||||
0 unifiExitPowerSavePeriod
|
||||
0 unifiAggressivePowerSaveTransitionPeriod
|
||||
0 unifiActiveTimeAfterMoreBit
|
||||
0 unifiForcedScheduleDuration
|
||||
0 unifiVhtCapabilities
|
||||
0 unifiMAXVifScheduleDuration
|
||||
0 unifiVifLongIntervalTime
|
||||
0 unifiDisallowSchedRelinquish
|
||||
0 unifiRameDplaneOperationTimeout
|
||||
0 unifiDebugKeepRadioOn
|
||||
0 unifiScanAbsenceDuration
|
||||
0 unifiScanAbsencePeriod
|
||||
0 unifiMaxClient
|
||||
0 unifiTdlsInP2pActivated
|
||||
0 unifiTdlsActivated
|
||||
0 unifiTdlsTPThresholdPktSecs
|
||||
0 unifiTdlsRssiThreshold
|
||||
0 unifiTdlsMaximumRetry
|
||||
0 unifiTdlsTPMonitorSecs
|
||||
0 unifiTdlsBasicHtMcsSet
|
||||
0 unifiTdlsBasicVhtMcsSet
|
||||
0 dot11TDLSDiscoveryRequestWindow
|
||||
0 dot11TDLSResponseTimeout
|
||||
0 dot11TDLSChannelSwitchActivated
|
||||
0 unifiTdlsDesignForTestMode
|
||||
0 unifiTdlsKeyLifeTimeInterval
|
||||
0 unifiTdlsTeardownFrameTxTimeout
|
||||
0 unifiWifiSharingEnabled
|
||||
0 unifiWiFiSharing5GHzChannel
|
||||
0 unifiWifiSharingChannelSwitchCount
|
||||
0 unifiChannelAnnouncementCount
|
||||
0 unifiRATestStoredSA
|
||||
0 unifiRATestStoreFrame
|
||||
0 dot11TDLSPeerUAPSDBufferSTAActivated
|
||||
0 unifiCSROnlyMIBShield
|
||||
0 unifiPrivateBbbTxFilterConfig
|
||||
0 unifiPrivateSWAGCFrontEndGain
|
||||
0 unifiPrivateSWAGCFrontEndLoss
|
||||
0 unifiPrivateSWAGCExtThresh
|
||||
0 unifiCSROnlyPowerCalDelay
|
||||
0 unifiRxAgcControl
|
||||
0 unifiWapiQosMask
|
||||
0 unifiRaaMaxSpecTimerMultiplier
|
||||
0 unifiWMMStallEnable
|
||||
0 unifiRaaSpeculationInterval
|
||||
0 unifiRaaSpeculationPeriod
|
||||
0 unifiRaaNumbSpeculationFrames
|
||||
0 unifiRaaTxHostRate
|
||||
0 unifiFallbackShortFrameRetryDistribution
|
||||
0 unifiPreEBRTWindow
|
||||
0 unifiPostEBRTWindow
|
||||
0 unifiPsPollThreshold
|
||||
0 unifiTxUsingLdpcEnabled
|
||||
0 unifiTxSGI20Enabled
|
||||
0 unifiTxSGI40Enabled
|
||||
0 unifiTxSGI80Enabled
|
||||
0 unifiTxSGI160Enabled
|
||||
0 unifiMacAddressRandomisation
|
||||
0 unifiSuBeamformerEnabled
|
||||
0 unifiMuBeamformerEnabled
|
||||
0 unifiTxOfdmSelect
|
||||
0 unifiTxDigGain
|
||||
0 unifiChipTemperature
|
||||
0 UnifiBatteryVoltage
|
||||
0 unifiForceShortSlotTime
|
||||
0 unifiDebugDisableRadioNannyActions
|
||||
0 unifiRxCckModemSensitivity
|
||||
0 unifiDpdPerBandwidth
|
||||
0 unifiBBVersion
|
||||
0 unifiRFVersion
|
||||
0 unifiClearRadioTrimCache
|
||||
0 unifiRxRadioCsMode
|
||||
0 unifiRxPriEnergyDetThreshold
|
||||
0 unifiRxSecEnergyDetThreshold
|
||||
0 unifiCCAMasterSwitch
|
||||
0 unifiRxSyncCCACfg
|
||||
0 unifiMacSecChanClearTime
|
||||
0 unifiLnaControlEnabled
|
||||
0 unifiLnaControlRssiThresholdLower
|
||||
0 unifiLnaControlRssiThresholdUpper
|
||||
0 unifiLowPowerRxConfig
|
||||
0 unifiTPCEnabled
|
||||
0 unifiCurrentTxpowerLevel
|
||||
0 unifiUserSetTxpowerLevel
|
||||
0 unifiTPCMaxPowerRSSIThreshold
|
||||
0 unifiTPCMinPowerRSSIThreshold
|
||||
0 unifiTPCMinPower2G
|
||||
0 unifiTPCMinPower5G
|
||||
0 unifiRadioLpRxRssiThresholdLower
|
||||
0 unifiRadioLpRxRssiThresholdUpper
|
||||
0 unifiPMFAssociationComebackTimeDelta
|
||||
0 unifiTestTspecHack
|
||||
0 unifiTestTspecHackValue
|
||||
0 unifiDebugInstantDelivery
|
||||
0 unifiDebugEnable
|
||||
0 unifiDPlaneDebug
|
||||
0 unifiNANEnabled
|
||||
0 unifiNANBeaconCapabilities
|
||||
0 hutsReadWriteDataElementInt32
|
||||
0 hutsReadWriteDataElementBoolean
|
||||
0 hutsReadWriteDataElementOctetString
|
||||
0 hutsReadWriteRemoteProcedureCallInt32
|
||||
0 hutsReadWriteInternalAPIInt16
|
||||
0 hutsReadWriteInternalAPIUint16
|
||||
0 hutsReadWriteInternalAPIUint32
|
||||
0 hutsReadWriteInternalAPIInt64
|
||||
0 hutsReadWriteInternalAPIBoolean
|
||||
0 hutsReadWriteInternalAPIOctetString
|
||||
0 unifiTestScanNoMedium
|
||||
0 unifiDualBandConcurrency
|
||||
0 unifiSupportedChannels
|
||||
0 unifiCountryList
|
||||
0 unifiNoCellIncludedChannels
|
||||
2 hutsReadWriteInternalAPIFixSizeTableKeyRow
|
||||
1 hutsReadWriteInternalAPIFixSizeTableKey1Row
|
||||
1 hutsReadWriteInternalAPIFixSizeTableKey2Row
|
||||
1 hutsReadWriteInternalAPIFixVarSizeTableKey1Row
|
||||
1 hutsReadWriteInternalAPIFixVarSizeTableKey2Row
|
||||
1 hutsReadWriteInternalAPIFixedSizeTableRow
|
||||
1 hutsReadWriteInternalAPIVarSizeTableRow
|
||||
2 hutsReadWriteInternalAPIVarSizeTableKeyRow
|
||||
2 hutsReadWriteRemoteProcedureCallOctetString
|
||||
1 hutsReadWriteTableInt16Row
|
||||
1 hutsReadWriteTableOctetStringRow
|
||||
1 unifiACRetries
|
||||
1 unifiTxDataConfirm
|
||||
1 unifiCCACSThresh
|
||||
1 unifiCURoamScanTrigger
|
||||
1 unifiCURoamfactor
|
||||
1 unifiDPDTrainPacketConfig
|
||||
1 unifiDebugModuleControl
|
||||
1 unifiDefaultCountry
|
||||
1 unifiDpdPredistortGains
|
||||
2 unifiLoadDpdLut
|
||||
2 unifiOverrideDpdLut
|
||||
2 unifiMacCCABusyTime
|
||||
2 unifiModemSgiOffset
|
||||
1 unifiNoCellMaxPower
|
||||
1 unifiOperatingClassParamters
|
||||
1 unifiPeerBandwidth
|
||||
1 unifiCurrentPeerNss
|
||||
1 unifiPeerTxDataRate
|
||||
1 unifiPeerRSSI
|
||||
1 unifiSwToHwQueueStats
|
||||
1 unifiHostToSwQueueStats
|
||||
1 unifiRSSICURoamScanTrigger
|
||||
1 unifiRSSIRoamfactor
|
||||
2 unifiRadioCCADebug
|
||||
1 unifiRadioCCAThresholds
|
||||
2 unifiRadioRXSettingsRead
|
||||
2 unifiRadioTXSettingsRead
|
||||
1 unifiRadioTxPowerOverride
|
||||
1 unifiRateStatsRxSuccessCount
|
||||
1 unifiRateStatsTxSuccessCount
|
||||
1 unifiRateStatsRate
|
||||
1 unifiRaaTxSuccessesCount
|
||||
1 unifiRaaTxFailuresCount
|
||||
1 unifiRaaTxPer
|
||||
1 unifiRaaResetStats
|
||||
1 unifiRaaTxMTPer
|
||||
2 unifiReadHardwareCounter
|
||||
1 unifiReadReg
|
||||
1 unifiRegulatoryParameters
|
||||
1 unifiRoamRSSIBoost
|
||||
1 unifiRxExternalGainFrequency
|
||||
1 unifiRxExternalGain
|
||||
1 unifiSarBackoff
|
||||
1 unifiScanParameters
|
||||
1 unifiThroughputDebug
|
||||
1 unifiTxAntennaConnectionLossFrequency
|
||||
1 unifiTxAntennaConnectionLoss
|
||||
1 unifiTxAntennaMaxGainFrequency
|
||||
1 unifiTxAntennaMaxGain
|
||||
1 unifiTxDetectorFrequencyCompensation
|
||||
1 unifiTxDetectorTemperatureCompensation
|
||||
1 unifiTxFtrimSettings
|
||||
1 unifiTxGainSettings
|
||||
1 unifiTxGainStepSettings
|
||||
1 unifiTxOOBConstraints
|
||||
1 unifiTxOpenLoopFrequencyCompensation
|
||||
1 unifiTxOpenLoopTemperatureCompensation
|
||||
1 unifiTxPaGainDpdFrequencyCompensation
|
||||
1 unifiTxPaGainDpdTemperatureCompensation
|
||||
1 unifiTxPowerDetectorResponse
|
||||
1 unifiTxPowerTrimConfig
|
||||
1 unifiTxSettings
|
||||
372
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/univif.dbg
vendored
Normal file
372
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/univif.dbg
vendored
Normal file
|
|
@ -0,0 +1,372 @@
|
|||
z dot11RSNAStatsSTAAddress
|
||||
z dot11RSNAStatsTKIPICVErrors
|
||||
z dot11RSNAStatsTKIPLocalMICFailures
|
||||
z dot11RSNAStatsTKIPRemoteMICFailures
|
||||
z dot11RSNAStatsCCMPReplays
|
||||
z dot11RSNAStatsCCMPDecryptErrors
|
||||
z dot11RSNAStatsTKIPReplays
|
||||
z dot11RSNAStatsRobustMgmtCCMPReplays
|
||||
z dot11TDLSPeerUAPSDIndicationWindow
|
||||
z dot11AssociationSAQueryMaximumTimeout
|
||||
z dot11AssociationSAQueryRetryTimeout
|
||||
z dot11PowerCapabilityMaxImplemented
|
||||
z dot11PowerCapabilityMinImplemented
|
||||
p dot11RTSThreshold
|
||||
p dot11ShortRetryLimit
|
||||
p dot11LongRetryLimit
|
||||
p dot11FragmentationThreshold
|
||||
p dot11RTSSuccessCount
|
||||
p dot11ACKFailureCount
|
||||
p dot11MulticastReceivedFrameCount
|
||||
p dot11FCSErrorCount
|
||||
p dot11WEPUndecryptableCount
|
||||
z dot11manufacturerProductVersion
|
||||
z unifiMLMEConnectionTimeOut
|
||||
z unifiMLMEScanChannelMaxScanTime
|
||||
z unifiMLMEScanChannelProbeInterval
|
||||
z unifiMLMEDataReferenceTimeout
|
||||
z unifiMLMEScanProbeInterval
|
||||
z unifiMLMEScanHighRSSIThreshold
|
||||
z unifiMLMEScanDeltaRSSIThreshold
|
||||
z unifiMLMEScanMaximumAge
|
||||
z unifiMLMEScanMaximumResults
|
||||
z unifiMLMEAutonomousScanNoisy
|
||||
z unifiFirmwareBuildID
|
||||
z unifiChipVersion
|
||||
z unifiFirmwarePatchBuildID
|
||||
z unifiBasicCapabilities
|
||||
z unifiExtendedCapabilities
|
||||
z unifiHtCapabilities
|
||||
z unifiRsnCapabilities
|
||||
z unifi24G40MHZChannels
|
||||
z unifiExtendedCapabilitiesDisabled
|
||||
p unifiTestSetChannelBW
|
||||
z unifiPLM689WorkaroundEnable
|
||||
z unifiPLM689WorkaroundTriggerDHCPDiscoverCount
|
||||
z unifiPLM689WorkaroundTriggerDHCPDiscoverTimeout
|
||||
z unifiSupportedDataRates
|
||||
z unifiPLM689WorkaroundAddresses
|
||||
z unifiRadioMeasurementActivated
|
||||
z unifiRadioMeasurementCapabilities
|
||||
z unifiVhtActivated
|
||||
z unifiHtActivated
|
||||
z unifiPLM689WorkaroundTriggerStaticIPTimeout
|
||||
z unifiPLM689WorkaroundTriggerARPCount
|
||||
z unifiRoamingEnabled
|
||||
z unifiRssiRoamScanTrigger
|
||||
z unifiRoamDeltaTrigger
|
||||
z unifiRoamCachedChannelScanPeriod
|
||||
z unifiFullRoamScanPeriod
|
||||
z unifiRoamScanBand
|
||||
z unifiRoamScanMaxActiveChannelTime
|
||||
z unifiRoamFullChannelScanFrequency
|
||||
z unifiRoamMode
|
||||
z unifiRssiRoamScanNoCandidateDeltaTrigger
|
||||
z unifiRoamEAPTimeout
|
||||
z unifiRoamScanControl
|
||||
z unifiRoamDfsScanMode
|
||||
z unifiRoamScanHomeTime
|
||||
z unifiRoamScanHomeAwayTime
|
||||
z unifiRoamScanNProbe
|
||||
z unifiApOlbcDuration
|
||||
z unifiApOlbcInterval
|
||||
z unifiFrameResponseTimeOut
|
||||
z unifiConnectionFailureTimeout
|
||||
z unifiConnectingProbeTimeout
|
||||
z unifiDisconnectTimeout
|
||||
z unifiFrameResponseCfmTxLifetimeTimeOut
|
||||
z unifiFrameResponseCfmFailureTimeOut
|
||||
z unifiForceActiveDuration
|
||||
z unifiMLMEScanMaxNumberOfProbeSets
|
||||
z unifiMLMEScanStopIfLessThanXFrames
|
||||
z unifiMLMEStationInactivityTimeOut
|
||||
z unifiMLMECliInactivityTimeOut
|
||||
z unifiMLMEStationInitialKickTimeOut
|
||||
z unifiUartConfigure
|
||||
z unifiUartPios
|
||||
z unifiClockFrequency
|
||||
z unifiCrystalFrequencyTrim
|
||||
z unifiEnableDorm
|
||||
z unifiDisableDormWhenBtOn
|
||||
z unifiExternalClockDetect
|
||||
z unifiExternalFastClockRequest
|
||||
z unifiWatchdogTimeout
|
||||
z unifiExternalFastClockRequestPIO
|
||||
p unifiRSSI
|
||||
z unifiLastBssRSSI
|
||||
p unifiSNR
|
||||
z unifiLastBssSNR
|
||||
z unifiSwTxTimeout
|
||||
z unifiHwTxTimeout
|
||||
p unifiTxDataRate
|
||||
z unifiSNRExtraOffsetCCK
|
||||
z unifiRSSIMaxAveragingPeriod
|
||||
z unifiRSSIMinReceivedFrames
|
||||
z unifiLastBssTxDataRate
|
||||
p unifiDiscardedFrameCount
|
||||
z unifiMacrameDebugStats
|
||||
p unifiCurrentTSFTime
|
||||
z unifiBaTxEnableTid
|
||||
z unifiBaConfig
|
||||
z unifiMoveBKtoBE
|
||||
p unifiBeaconReceived
|
||||
z unifiRadioOnTime
|
||||
z unifiRadioTxTime
|
||||
z unifiRadioRxTime
|
||||
z unifiRadioScanTime
|
||||
p unifiPSLeakyAP
|
||||
z unifiTqamActivated
|
||||
z unifiNoAckActivationCount
|
||||
z unifiRxFcsErrorCount
|
||||
p unifiBeaconsReceivedPercentage
|
||||
p unifiQueueStatsEnable
|
||||
z unifiDpdMasterSwitch
|
||||
z unifiGoogleMaxNumberOfPeriodicScans
|
||||
z unifiGoogleMaxRSSISampleSize
|
||||
z unifiGoogleMaxHotlistAPs
|
||||
z unifiGoogleMaxSignificantWifiChangeAPs
|
||||
z unifiGoogleMaxBssidHistoryEntries
|
||||
z unifiMacBeaconTimeout
|
||||
z UnifiRoamTrackingScanPeriod
|
||||
z unifiRoamCuLocal
|
||||
z unifiCuRoamScanNoCandidateDeltaTrigger
|
||||
z unifiRoamAPSelectDeltaFactor
|
||||
z unifiCURoamweight
|
||||
z unifiRSSIRoamweight
|
||||
z unifiRoamBSSLoadMonitoringFrequency
|
||||
z unifiCUMeasurementInterval
|
||||
z unifiCurrentBssNss
|
||||
z unifiAPMimoUsed
|
||||
z unifiRoamOffloaded4wshkTimeout
|
||||
z unifiRoamingCount
|
||||
z unifiRoamingAKM
|
||||
z unifiCurrentBssBandwidth
|
||||
z unifiCurrentBssChannelFrequency
|
||||
z unifiLoggerEnabled
|
||||
z unifiMaPacketFateEnabled
|
||||
z unifiCSROnlyEIFSDuration
|
||||
z unifiOverrideDefaultBETXOPForHT
|
||||
z unifiOverrideDefaultBETXOP
|
||||
z unifiRXABBTrimSettings
|
||||
z unifiRadioTrimsEnable
|
||||
z unifiHardwarePlatform
|
||||
z unifiForceChannelBW
|
||||
z unifiDPDTrainingDuration
|
||||
z unifiCoexDebugOverrideBt
|
||||
z unifiFastPowerSaveTimeout
|
||||
z unifiFastPowerSaveTimeOutSmall
|
||||
z unifiMLMESTAKeepAliveTimeout
|
||||
z unifiMLMEAPKeepAliveTimeout
|
||||
z unifiMLMEGOKeepAliveTimeout
|
||||
z unifiSTARouterAdvertisementMinimumIntervalToForward
|
||||
z unifiRoamConnectionQualityCheckWaitAfterConnect
|
||||
z unifiApBeaconMaxDrift
|
||||
z unifiBSSMaxIdlePeriodEnabled
|
||||
z unifiVifIdleMonitorTime
|
||||
z unifiDisableLegacyPowerSave
|
||||
z unifiDebugForceActive
|
||||
z unifiStationActivityIdleTime
|
||||
z unifiPowerManagementDelayTimeout
|
||||
p unifiAPSDServicePeriodTimeout
|
||||
z unifiConcurrentPowerManagementDelayTimeout
|
||||
z unifiStationQosInfo
|
||||
z unifiListenIntervalSkippingDTIM
|
||||
z unifiListenInterval
|
||||
p unifiLegacyPsPollTimeout
|
||||
z unifiTogglePowerDomain
|
||||
z unifiP2PListenIntervalSkippingDTIM
|
||||
p unifiFragmentationDuration
|
||||
z unifiIdleModeLiteEnabled
|
||||
z unifiIdleModeEnabled
|
||||
z unifiDTIMWaitTimeout
|
||||
z unifiListenIntervalMaxTime
|
||||
z unifiScanMaxProbeTransmitLifetime
|
||||
z unifiPowerSaveTransitionPacketThreshold
|
||||
z unifiProbeResponseLifetime
|
||||
z unifiProbeResponseMaxRetry
|
||||
z unifiExitPowerSavePeriod
|
||||
z unifiAggressivePowerSaveTransitionPeriod
|
||||
z unifiActiveTimeAfterMoreBit
|
||||
p unifiForcedScheduleDuration
|
||||
z unifiVhtCapabilities
|
||||
z unifiMAXVifScheduleDuration
|
||||
z unifiVifLongIntervalTime
|
||||
z unifiDisallowSchedRelinquish
|
||||
z unifiRameDplaneOperationTimeout
|
||||
z unifiDebugKeepRadioOn
|
||||
z unifiScanAbsenceDuration
|
||||
z unifiScanAbsencePeriod
|
||||
z unifiMaxClient
|
||||
z unifiTdlsInP2pActivated
|
||||
z unifiTdlsActivated
|
||||
z unifiTdlsTPThresholdPktSecs
|
||||
z unifiTdlsRssiThreshold
|
||||
z unifiTdlsMaximumRetry
|
||||
z unifiTdlsTPMonitorSecs
|
||||
z unifiTdlsBasicHtMcsSet
|
||||
z unifiTdlsBasicVhtMcsSet
|
||||
z dot11TDLSDiscoveryRequestWindow
|
||||
z dot11TDLSResponseTimeout
|
||||
z dot11TDLSChannelSwitchActivated
|
||||
z unifiTdlsDesignForTestMode
|
||||
z unifiTdlsKeyLifeTimeInterval
|
||||
z unifiTdlsTeardownFrameTxTimeout
|
||||
z unifiWifiSharingEnabled
|
||||
z unifiWiFiSharing5GHzChannel
|
||||
z unifiWifiSharingChannelSwitchCount
|
||||
z unifiChannelAnnouncementCount
|
||||
z unifiRATestStoredSA
|
||||
z unifiRATestStoreFrame
|
||||
z dot11TDLSPeerUAPSDBufferSTAActivated
|
||||
z unifiCSROnlyMIBShield
|
||||
z unifiPrivateBbbTxFilterConfig
|
||||
z unifiPrivateSWAGCFrontEndGain
|
||||
z unifiPrivateSWAGCFrontEndLoss
|
||||
z unifiPrivateSWAGCExtThresh
|
||||
z unifiCSROnlyPowerCalDelay
|
||||
z unifiRxAgcControl
|
||||
z unifiWapiQosMask
|
||||
z unifiRaaMaxSpecTimerMultiplier
|
||||
z unifiWMMStallEnable
|
||||
z unifiRaaSpeculationInterval
|
||||
z unifiRaaSpeculationPeriod
|
||||
z unifiRaaNumbSpeculationFrames
|
||||
z unifiRaaTxHostRate
|
||||
z unifiFallbackShortFrameRetryDistribution
|
||||
p unifiPreEBRTWindow
|
||||
p unifiPostEBRTWindow
|
||||
p unifiPsPollThreshold
|
||||
z unifiTxUsingLdpcEnabled
|
||||
z unifiTxSGI20Enabled
|
||||
z unifiTxSGI40Enabled
|
||||
z unifiTxSGI80Enabled
|
||||
z unifiTxSGI160Enabled
|
||||
z unifiMacAddressRandomisation
|
||||
z unifiSuBeamformerEnabled
|
||||
z unifiMuBeamformerEnabled
|
||||
z unifiTxOfdmSelect
|
||||
z unifiTxDigGain
|
||||
z unifiChipTemperature
|
||||
z UnifiBatteryVoltage
|
||||
z unifiForceShortSlotTime
|
||||
z unifiDebugDisableRadioNannyActions
|
||||
z unifiRxCckModemSensitivity
|
||||
z unifiDpdPerBandwidth
|
||||
z unifiBBVersion
|
||||
z unifiRFVersion
|
||||
z unifiClearRadioTrimCache
|
||||
z unifiRxRadioCsMode
|
||||
z unifiRxPriEnergyDetThreshold
|
||||
z unifiRxSecEnergyDetThreshold
|
||||
z unifiCCAMasterSwitch
|
||||
z unifiRxSyncCCACfg
|
||||
z unifiMacSecChanClearTime
|
||||
z unifiLnaControlEnabled
|
||||
z unifiLnaControlRssiThresholdLower
|
||||
z unifiLnaControlRssiThresholdUpper
|
||||
z unifiLowPowerRxConfig
|
||||
z unifiTPCEnabled
|
||||
p unifiCurrentTxpowerLevel
|
||||
z unifiUserSetTxpowerLevel
|
||||
z unifiTPCMaxPowerRSSIThreshold
|
||||
z unifiTPCMinPowerRSSIThreshold
|
||||
z unifiTPCMinPower2G
|
||||
z unifiTPCMinPower5G
|
||||
z unifiRadioLpRxRssiThresholdLower
|
||||
z unifiRadioLpRxRssiThresholdUpper
|
||||
z unifiPMFAssociationComebackTimeDelta
|
||||
z unifiTestTspecHack
|
||||
z unifiTestTspecHackValue
|
||||
z unifiDebugInstantDelivery
|
||||
z unifiDebugEnable
|
||||
z unifiDPlaneDebug
|
||||
z unifiNANEnabled
|
||||
z unifiNANBeaconCapabilities
|
||||
z hutsReadWriteDataElementInt32
|
||||
z hutsReadWriteDataElementBoolean
|
||||
z hutsReadWriteDataElementOctetString
|
||||
p hutsReadWriteRemoteProcedureCallInt32
|
||||
z hutsReadWriteInternalAPIInt16
|
||||
z hutsReadWriteInternalAPIUint16
|
||||
z hutsReadWriteInternalAPIUint32
|
||||
p hutsReadWriteInternalAPIInt64
|
||||
z hutsReadWriteInternalAPIBoolean
|
||||
z hutsReadWriteInternalAPIOctetString
|
||||
z unifiTestScanNoMedium
|
||||
z unifiDualBandConcurrency
|
||||
z unifiSupportedChannels
|
||||
z unifiCountryList
|
||||
z unifiNoCellIncludedChannels
|
||||
z hutsReadWriteInternalAPIFixSizeTableKeyRow
|
||||
p hutsReadWriteInternalAPIFixSizeTableKey1Row
|
||||
p hutsReadWriteInternalAPIFixSizeTableKey2Row
|
||||
z hutsReadWriteInternalAPIFixVarSizeTableKey1Row
|
||||
z hutsReadWriteInternalAPIFixVarSizeTableKey2Row
|
||||
z hutsReadWriteInternalAPIFixedSizeTableRow
|
||||
z hutsReadWriteInternalAPIVarSizeTableRow
|
||||
z hutsReadWriteInternalAPIVarSizeTableKeyRow
|
||||
z hutsReadWriteRemoteProcedureCallOctetString
|
||||
p hutsReadWriteTableInt16Row
|
||||
z hutsReadWriteTableOctetStringRow
|
||||
p unifiACRetries
|
||||
z unifiTxDataConfirm
|
||||
z unifiCCACSThresh
|
||||
z unifiCURoamScanTrigger
|
||||
z unifiCURoamfactor
|
||||
z unifiDPDTrainPacketConfig
|
||||
z unifiDebugModuleControl
|
||||
z unifiDefaultCountry
|
||||
z unifiDpdPredistortGains
|
||||
z unifiLoadDpdLut
|
||||
z unifiOverrideDpdLut
|
||||
z unifiMacCCABusyTime
|
||||
z unifiModemSgiOffset
|
||||
z unifiNoCellMaxPower
|
||||
z unifiOperatingClassParamters
|
||||
z unifiPeerBandwidth
|
||||
z unifiCurrentPeerNss
|
||||
z unifiPeerTxDataRate
|
||||
z unifiPeerRSSI
|
||||
p unifiSwToHwQueueStats
|
||||
p unifiHostToSwQueueStats
|
||||
z unifiRSSICURoamScanTrigger
|
||||
z unifiRSSIRoamfactor
|
||||
z unifiRadioCCADebug
|
||||
z unifiRadioCCAThresholds
|
||||
z unifiRadioRXSettingsRead
|
||||
z unifiRadioTXSettingsRead
|
||||
z unifiRadioTxPowerOverride
|
||||
p unifiRateStatsRxSuccessCount
|
||||
p unifiRateStatsTxSuccessCount
|
||||
z unifiRateStatsRate
|
||||
p unifiRaaTxSuccessesCount
|
||||
p unifiRaaTxFailuresCount
|
||||
p unifiRaaTxPer
|
||||
p unifiRaaResetStats
|
||||
p unifiRaaTxMTPer
|
||||
z unifiReadHardwareCounter
|
||||
z unifiReadReg
|
||||
z unifiRegulatoryParameters
|
||||
z unifiRoamRSSIBoost
|
||||
z unifiRxExternalGainFrequency
|
||||
z unifiRxExternalGain
|
||||
z unifiSarBackoff
|
||||
z unifiScanParameters
|
||||
p unifiThroughputDebug
|
||||
z unifiTxAntennaConnectionLossFrequency
|
||||
z unifiTxAntennaConnectionLoss
|
||||
z unifiTxAntennaMaxGainFrequency
|
||||
z unifiTxAntennaMaxGain
|
||||
z unifiTxDetectorFrequencyCompensation
|
||||
z unifiTxDetectorTemperatureCompensation
|
||||
z unifiTxFtrimSettings
|
||||
z unifiTxGainSettings
|
||||
z unifiTxGainStepSettings
|
||||
z unifiTxOOBConstraints
|
||||
z unifiTxOpenLoopFrequencyCompensation
|
||||
z unifiTxOpenLoopTemperatureCompensation
|
||||
z unifiTxPaGainDpdFrequencyCompensation
|
||||
z unifiTxPaGainDpdTemperatureCompensation
|
||||
z unifiTxPowerDetectorResponse
|
||||
z unifiTxPowerTrimConfig
|
||||
z unifiTxSettings
|
||||
372
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/xide_mib.dbg
vendored
Normal file
372
universal7570-common/proprietary/vendor/etc/wifi/mx140_t/debug/wlan/xide_mib.dbg
vendored
Normal file
File diff suppressed because one or more lines are too long
15
universal7570-common/proprietary/vendor/etc/wifi/p2p_supplicant_overlay.conf
vendored
Normal file
15
universal7570-common/proprietary/vendor/etc/wifi/p2p_supplicant_overlay.conf
vendored
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
disable_scan_offload=1
|
||||
p2p_listen_reg_class=81
|
||||
p2p_listen_channel=1
|
||||
p2p_oper_reg_class=124
|
||||
p2p_oper_channel=149
|
||||
manufacturer=SAMSUNG_ELECTRONICS
|
||||
model_name=SAMSUNG_MOBILE
|
||||
model_number=2014
|
||||
serial_number=19691101
|
||||
update_config=1
|
||||
p2p_add_cli_chan=1
|
||||
ip_addr_go=192.168.49.1
|
||||
ip_addr_mask=255.255.255.0
|
||||
ip_addr_start=192.168.49.200
|
||||
ip_addr_end=192.168.49.254
|
||||
5
universal7570-common/proprietary/vendor/etc/wifi/wpa_supplicant.conf
vendored
Normal file
5
universal7570-common/proprietary/vendor/etc/wifi/wpa_supplicant.conf
vendored
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
update_config=1
|
||||
eapol_version=1
|
||||
ap_scan=1
|
||||
fast_reauth=1
|
||||
p2p_add_cli_chan=1
|
||||
3
universal7570-common/proprietary/vendor/etc/wifi/wpa_supplicant_overlay.conf
vendored
Normal file
3
universal7570-common/proprietary/vendor/etc/wifi/wpa_supplicant_overlay.conf
vendored
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
disable_scan_offload=1
|
||||
p2p_disabled=1
|
||||
update_config=1
|
||||
Loading…
Add table
Add a link
Reference in a new issue