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https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
drc: lots of new debug code
This commit is contained in:
notaz
parent
d3524932fa
commit
00faec9cdb
10 changed files with 399 additions and 153 deletions
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@ -41,7 +41,6 @@
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#define LINK_BRANCHES 1
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// limits (per block)
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#define BLOCK_CYCLE_LIMIT 100
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#define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6)
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// max literal offset from the block end
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@ -49,7 +48,20 @@
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#define MAX_LITERALS (BLOCK_CYCLE_LIMIT / 4)
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#define MAX_LOCAL_BRANCHES 32
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// debug stuff {
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///
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#define FETCH_OP(pc) \
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dr_pc_base[(pc) / 2]
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#define FETCH32(a) \
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((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
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#ifdef DRC_SH2
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// debug stuff
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// 1 - ?
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// 2 - ?
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// 4 - log asm
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// {
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#ifndef DRC_DEBUG
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#define DRC_DEBUG 0
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#endif
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@ -237,41 +249,7 @@ static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
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static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d);
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static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
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extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode);
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// address space stuff
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static void *dr_get_pc_base(u32 pc, int is_slave)
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{
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void *ret = NULL;
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u32 mask = 0;
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if ((pc & ~0x7ff) == 0) {
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// BIOS
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ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
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mask = 0x7ff;
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}
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else if ((pc & 0xfffff000) == 0xc0000000) {
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// data array
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ret = Pico32xMem->data_array[is_slave];
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mask = 0xfff;
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}
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else if ((pc & 0xc6000000) == 0x06000000) {
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// SDRAM
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ret = Pico32xMem->sdram;
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mask = 0x03ffff;
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}
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else if ((pc & 0xc6000000) == 0x02000000) {
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// ROM
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ret = Pico.rom;
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mask = 0x3fffff;
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}
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if (ret == NULL)
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return (void *)-1; // NULL is valid value
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return (char *)ret - (pc & ~mask);
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}
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static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
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{
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int poffs = -1;
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@ -1186,12 +1164,6 @@ static void emit_block_entry(void)
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goto default_; \
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}
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#define FETCH_OP(pc) \
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dr_pc_base[(pc) / 2]
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#define FETCH32(a) \
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((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
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#define GET_Fx() \
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((op >> 4) & 0x0f)
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@ -1204,9 +1176,7 @@ static void emit_block_entry(void)
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if (GET_Fx() >= n) \
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goto default_
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// op_flags: data from 1st pass
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#define OP_FLAGS(pc) op_flags[((pc) - base_pc) / 2]
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#define OF_DELAY_OP (1 << 0)
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static void *dr_get_pc_base(u32 pc, int is_slave);
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static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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{
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@ -1222,7 +1192,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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int literal_addr_count = 0;
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int pending_branch_cond = -1;
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int pending_branch_pc = 0;
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u8 op_flags[BLOCK_CYCLE_LIMIT + 1];
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u8 op_flags[BLOCK_CYCLE_LIMIT];
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struct {
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u32 delayed_op:2;
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u32 test_irq:1;
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@ -1270,56 +1240,19 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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dr_link_blocks(tcache_ptr, base_pc, tcache_id);
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// 1st pass: scan forward for local branches
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memset(op_flags, 0, sizeof(op_flags));
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for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT; cycles++, pc += 2) {
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op = FETCH_OP(pc);
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if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR
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signed int offs = ((signed int)(op << 20) >> 19);
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pc += 2;
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OP_FLAGS(pc) |= OF_DELAY_OP;
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ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 2,);
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break;
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}
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if ((op & 0xf000) == 0) {
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op &= 0xff;
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if (op == 0x1b) // SLEEP
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break;
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if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) { // BRAF, BSRF, RTS, RTE
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pc += 2;
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OP_FLAGS(pc) |= OF_DELAY_OP;
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break;
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}
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scan_block(base_pc, sh2->is_slave, op_flags, &end_pc);
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// collect branch_targets that don't land on delay slots
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for (pc = base_pc; pc <= end_pc; pc += 2) {
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if (!(OP_FLAGS(pc) & OF_TARGET))
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continue;
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if (OP_FLAGS(pc) & OF_DELAY_OP) {
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OP_FLAGS(pc) &= ~OF_TARGET;
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continue;
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}
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if ((op & 0xf0df) == 0x400b) { // JMP, JSR
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pc += 2;
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OP_FLAGS(pc) |= OF_DELAY_OP;
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break;
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}
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if ((op & 0xf900) == 0x8900) { // BT(S), BF(S)
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signed int offs = ((signed int)(op << 24) >> 23);
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if (op & 0x0400)
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OP_FLAGS(pc + 2) |= OF_DELAY_OP;
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ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 4, break);
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}
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if ((op & 0xff00) == 0xc300) // TRAPA
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break;
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ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break);
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}
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end_pc = pc;
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// clean branch_targets that are not really local,
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// and that land on delay slots
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for (i = 0, tmp = 0; i < branch_target_count; i++) {
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pc = branch_target_pc[i];
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if (base_pc <= pc && pc <= end_pc && !(OP_FLAGS(pc) & OF_DELAY_OP))
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branch_target_pc[tmp++] = branch_target_pc[i];
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if (i == branch_target_count - 1) // workaround gcc 4.5.2 bug?
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break;
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}
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branch_target_count = tmp;
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if (branch_target_count > 0) {
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memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
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memset(branch_target_blkid, 0, sizeof(branch_target_blkid[0]) * branch_target_count);
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@ -1338,9 +1271,9 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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op = FETCH_OP(pc);
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i = find_in_array(branch_target_pc, branch_target_count, pc);
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if (i >= 0 || pc == base_pc)
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if ((OP_FLAGS(pc) & OF_TARGET) || pc == base_pc)
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{
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i = find_in_array(branch_target_pc, branch_target_count, pc);
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if (pc != base_pc)
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{
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/* make "subblock" - just a mid-block entry */
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@ -1382,10 +1315,25 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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#if (DRC_DEBUG & 2)
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insns_compiled++;
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#endif
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#if (DRC_DEBUG & 4)
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DasmSH2(sh2dasm_buff, pc, op);
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printf("%08x %04x %s\n", pc, op, sh2dasm_buff);
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#endif
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#ifdef DRC_CMP
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//if (out_pc != 0 && out_pc != (u32)-1)
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// emit_move_r_imm32(SHR_PC, out_pc);
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//else
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if (!drcf.delayed_op) {
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emit_move_r_imm32(SHR_PC, pc);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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FLUSH_CYCLES(sr);
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// rcache_clean(); // FIXME
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rcache_flush();
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emit_do_static_regs(1, 0);
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emith_pass_arg_r(0, CONTEXT_REG);
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emith_call(do_sh2_cmp);
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}
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#endif
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pc += 2;
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@ -1889,6 +1837,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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if (drcf.delayed_op)
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DELAY_SAVE_T(sr);
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#ifndef DRC_CMP
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if (FETCH_OP(pc) == 0x8bfd) { // BF #-2
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if (gconst_get(GET_Rn(), &tmp)) {
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// XXX: limit burned cycles
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@ -1901,6 +1850,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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emith_sh2_dtbf_loop();
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goto end_op;
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}
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#endif
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tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
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emith_bic_r_imm(sr, T);
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emith_subf_r_imm(tmp, 1);
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@ -2502,13 +2452,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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default_:
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elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
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sh2->is_slave ? 's' : 'm', op, pc - 2);
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#ifdef DRC_DEBUG_INTERP
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emit_move_r_imm32(SHR_PC, pc - 2);
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rcache_flush();
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emith_pass_arg_r(0, CONTEXT_REG);
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emith_pass_arg_imm(1, op);
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emith_call(sh2_do_op);
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#endif
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break;
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}
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@ -3151,4 +3094,90 @@ void sh2_drc_finish(SH2 *sh2)
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}
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}
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#endif /* DRC_SH2 */
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static void *dr_get_pc_base(u32 pc, int is_slave)
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{
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void *ret = NULL;
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u32 mask = 0;
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if ((pc & ~0x7ff) == 0) {
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// BIOS
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ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
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mask = 0x7ff;
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}
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else if ((pc & 0xfffff000) == 0xc0000000) {
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// data array
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ret = Pico32xMem->data_array[is_slave];
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mask = 0xfff;
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}
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else if ((pc & 0xc6000000) == 0x06000000) {
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// SDRAM
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ret = Pico32xMem->sdram;
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mask = 0x03ffff;
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}
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else if ((pc & 0xc6000000) == 0x02000000) {
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// ROM
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ret = Pico.rom;
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mask = 0x3fffff;
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}
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if (ret == NULL)
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return (void *)-1; // NULL is valid value
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return (char *)ret - (pc & ~mask);
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}
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void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc)
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{
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u16 *dr_pc_base;
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u32 pc, target, op;
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int cycles;
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memset(op_flags, 0, BLOCK_CYCLE_LIMIT);
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dr_pc_base = dr_get_pc_base(base_pc, is_slave);
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for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT-1; cycles++, pc += 2) {
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op = FETCH_OP(pc);
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if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR
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signed int offs = ((signed int)(op << 20) >> 19);
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pc += 2;
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OP_FLAGS(pc) |= OF_DELAY_OP;
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target = pc + offs + 2;
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if (base_pc <= target && target < base_pc + BLOCK_CYCLE_LIMIT * 2)
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OP_FLAGS(target) |= OF_TARGET;
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break;
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}
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if ((op & 0xf000) == 0) {
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op &= 0xff;
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if (op == 0x1b) // SLEEP
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break;
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// BRAF, BSRF, RTS, RTE
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if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) {
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pc += 2;
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OP_FLAGS(pc) |= OF_DELAY_OP;
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break;
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}
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continue;
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}
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if ((op & 0xf0df) == 0x400b) { // JMP, JSR
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pc += 2;
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OP_FLAGS(pc) |= OF_DELAY_OP;
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break;
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}
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if ((op & 0xf900) == 0x8900) { // BT(S), BF(S)
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signed int offs = ((signed int)(op << 24) >> 23);
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if (op & 0x0400)
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OP_FLAGS(pc + 2) |= OF_DELAY_OP;
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target = pc + offs + 4;
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if (base_pc <= target && target < base_pc + BLOCK_CYCLE_LIMIT * 2)
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OP_FLAGS(target) |= OF_TARGET;
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}
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if ((op & 0xff00) == 0xc300) // TRAPA
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break;
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}
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*end_pc = pc;
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}
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// vim:shiftwidth=2:expandtab
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