mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
vdp fifo speed optimization
This commit is contained in:
kub
parent
8d67848ddf
commit
02138162c4
1 changed files with 125 additions and 103 deletions
228
pico/videoport.c
228
pico/videoport.c
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@ -57,125 +57,142 @@ int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned
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*/
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// NB code assumes fifo_* arrays have size 2^n
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// last transferred FIFO data, ...x = index XXX currently only CPU
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static short fifo_data[4], fifo_dx; // XXX must go into save?
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static struct VdpFIFO { // XXX this must go into save file!
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// last transferred FIFO data, ...x = index XXX currently only CPU
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unsigned short fifo_data[4], fifo_dx;
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// queued FIFO transfers, ...x = index, ...l = queue length
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// each entry has 2 values: [n]>>3 = #writes, [n]&7 = flags (FQ_*)
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unsigned int fifo_queue[8], fifo_qx, fifo_ql;
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unsigned int fifo_total; // total# of pending FIFO entries (w/o BGDMA)
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unsigned short fifo_slot; // last executed slot in current scanline
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unsigned short fifo_maxslot;// #slots in scanline
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const unsigned char *fifo_cyc2sl;
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const unsigned short *fifo_sl2cyc;
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} VdpFIFO;
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// queued FIFO transfers, ...x = index, ...l = queue length
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// each entry has 2 values: [n]>>3 = #writes, [n]&7 = flags
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static int fifo_queue[8], fifo_qx, fifo_ql; // XXX must go into save?
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enum { FQ_BYTE = 1, FQ_BGDMA = 2, FQ_FGDMA = 4 }; // queue flags, NB: BYTE = 1!
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static unsigned int fifo_total; // total# of pending FIFO entries (w/o BGDMA)
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static unsigned short fifo_slot; // last executed slot in current scanline
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static unsigned short fifo_maxslot;// #slots in scanline
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static const unsigned char *fifo_cyc2sl;
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static const unsigned short *fifo_sl2cyc;
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// do the FIFO math
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static __inline int AdvanceFIFOEntry(struct PicoVideo *pv, int slots)
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static __inline int AdvanceFIFOEntry(struct VdpFIFO *vf, struct PicoVideo *pv, int slots)
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{
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int l = slots, b = fifo_queue[fifo_qx] & FQ_BYTE;
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int l = slots, b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;
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int cnt = pv->fifo_cnt;
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// advance currently active FIFO entry
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if (l > pv->fifo_cnt)
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l = pv->fifo_cnt;
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if (!(fifo_queue[fifo_qx] & FQ_BGDMA))
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fifo_total -= ((pv->fifo_cnt & b) + l) >> b;
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pv->fifo_cnt -= l;
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if (l > cnt)
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l = cnt;
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if (!(vf->fifo_queue[vf->fifo_qx] & FQ_BGDMA))
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vf->fifo_total -= ((cnt & b) + l) >> b;
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cnt -= l;
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// if entry has been processed...
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if (pv->fifo_cnt == 0) {
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if (cnt == 0) {
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// remove entry from FIFO
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if (fifo_ql)
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fifo_qx ++, fifo_qx &= 7, fifo_ql --;
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if (vf->fifo_ql)
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vf->fifo_qx = (vf->fifo_qx+1) & 7, vf->fifo_ql --;
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// start processing for next entry if there is one
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if (fifo_ql)
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pv->fifo_cnt = (fifo_queue[fifo_qx] >> 3) << (fifo_queue[fifo_qx] & FQ_BYTE);
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else { // FIFO empty
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if (vf->fifo_ql) {
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b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;
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cnt = (vf->fifo_queue[vf->fifo_qx] >> 3) << b;
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} else { // FIFO empty
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pv->status &= ~PVS_FIFORUN;
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fifo_total = 0;
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vf->fifo_total = 0;
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}
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}
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pv->fifo_cnt = cnt;
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return l;
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}
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static __inline void SetFIFOState(struct PicoVideo *pv)
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static __inline void SetFIFOState(struct VdpFIFO *vf, struct PicoVideo *pv)
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{
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unsigned int st = pv->status, cmd = pv->command;
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// release CPU and terminate DMA if FIFO isn't blocking the 68k anymore
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if (fifo_total <= 4) {
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pv->status &= ~PVS_CPUWR;
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if (!(pv->status & (PVS_DMABG|PVS_DMAFILL))) {
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pv->status &= ~SR_DMA;
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pv->command &= ~0x80;
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if (vf->fifo_total <= 4) {
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st &= ~PVS_CPUWR;
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if (!(st & (PVS_DMABG|PVS_DMAFILL))) {
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st &= ~SR_DMA;
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cmd &= ~0x80;
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}
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}
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if (fifo_total == 0) {
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pv->status &= ~PVS_CPURD;
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if (pv->fifo_cnt == 0) {
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st &= ~PVS_CPURD;
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// terminate DMA if applicable
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if (!(pv->status & (PVS_FIFORUN|PVS_DMAFILL))) {
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pv->status &= ~(SR_DMA|PVS_DMABG);
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pv->command &= ~0x80;
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if (!(st & (PVS_FIFORUN|PVS_DMAFILL))) {
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st &= ~(SR_DMA|PVS_DMABG);
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cmd &= ~0x80;
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}
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}
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pv->status = st;
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pv->command = cmd;
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}
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// sync FIFO to cycles
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void PicoVideoFIFOSync(int cycles)
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{
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struct VdpFIFO *vf = &VdpFIFO;
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struct PicoVideo *pv = &Pico.video;
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int slots, done;
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// calculate #slots since last executed slot
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slots = fifo_cyc2sl[cycles>>1] - fifo_slot;
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slots = vf->fifo_cyc2sl[cycles>>1] - vf->fifo_slot;
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// advance FIFO queue by #done slots
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done = slots;
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while (done > 0 && pv->fifo_cnt) {
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int l = AdvanceFIFOEntry(pv, done);
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fifo_slot += l;
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int l = AdvanceFIFOEntry(vf, pv, done);
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vf->fifo_slot += l;
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done -= l;
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}
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if (done != slots)
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SetFIFOState(pv);
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SetFIFOState(vf, pv);
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}
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// drain FIFO, blocking 68k on the way. FIFO must be synced prior to drain.
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int PicoVideoFIFODrain(int level, int cycles, int bgdma)
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static int PicoVideoFIFODrain(int level, int cycles, int bgdma)
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{
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struct VdpFIFO *vf = &VdpFIFO;
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struct PicoVideo *pv = &Pico.video;
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unsigned ocyc = cycles;
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int burn = 0;
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//int osl = fifo_slot;
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// process FIFO entries until low level is reached
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while (fifo_total > level && fifo_slot < fifo_maxslot &&
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(!(fifo_queue[fifo_qx] & FQ_BGDMA) || bgdma)) {
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int b = fifo_queue[fifo_qx] & FQ_BYTE;
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int cnt = ((fifo_total-level) << b) - (pv->fifo_cnt & b);
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int slot = (pv->fifo_cnt<cnt ? pv->fifo_cnt:cnt) + fifo_slot; // target slot
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while (vf->fifo_slot < vf->fifo_maxslot && cycles < 488 &&
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(vf->fifo_total > level || (vf->fifo_queue[vf->fifo_qx] & bgdma))) {
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int b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;
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int cnt = bgdma ? pv->fifo_cnt : ((vf->fifo_total-level)<<b) - (pv->fifo_cnt&b);
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int slot = (pv->fifo_cnt<cnt ? pv->fifo_cnt:cnt) + vf->fifo_slot;
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if (slot > fifo_maxslot) {
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// target in later scanline, advance to eol
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slot = fifo_maxslot;
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if (slot > vf->fifo_maxslot) {
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// target slot in later scanline, advance to eol
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slot = vf->fifo_maxslot;
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cycles = 488;
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} else {
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// advance FIFO to target slot and CPU to cycles at that slot
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cycles = fifo_sl2cyc[slot]<<1;
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cycles = vf->fifo_sl2cyc[slot]<<1;
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}
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if (slot > vf->fifo_slot) {
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AdvanceFIFOEntry(vf, pv, slot - vf->fifo_slot);
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vf->fifo_slot = slot;
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}
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AdvanceFIFOEntry(pv, slot - fifo_slot);
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fifo_slot = slot;
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}
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burn = cycles - ocyc;
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if (cycles > ocyc)
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burn = cycles - ocyc;
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SetFIFOState(pv);
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SetFIFOState(vf, pv);
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return burn;
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}
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// read VDP data port
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int PicoVideoFIFORead(void)
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static int PicoVideoFIFORead(void)
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{
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struct VdpFIFO *vf = &VdpFIFO;
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struct PicoVideo *pv = &Pico.video;
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int lc = SekCyclesDone()-Pico.t.m68c_line_start;
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int burn = 0;
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@ -183,16 +200,16 @@ int PicoVideoFIFORead(void)
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if (pv->fifo_cnt) {
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PicoVideoFIFOSync(lc);
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// advance FIFO and CPU until FIFO is empty
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burn = PicoVideoFIFODrain(0, lc, 1);
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burn = PicoVideoFIFODrain(0, lc, FQ_BGDMA);
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lc += burn;
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}
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if (fifo_total > 0)
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if (pv->fifo_cnt)
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pv->status |= PVS_CPURD; // target slot is in later scanline
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else {
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// use next VDP access slot for reading, block 68k until then
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fifo_slot = fifo_cyc2sl[lc>>1] + 1;
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burn += (fifo_sl2cyc[fifo_slot]<<1) - lc;
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vf->fifo_slot = vf->fifo_cyc2sl[lc>>1] + 1;
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burn += (vf->fifo_sl2cyc[vf->fifo_slot]<<1) - lc;
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}
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return burn;
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@ -201,50 +218,51 @@ int PicoVideoFIFORead(void)
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// write VDP data port
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int PicoVideoFIFOWrite(int count, int flags, unsigned sr_mask,unsigned sr_flags)
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{
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struct VdpFIFO *vf = &VdpFIFO;
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struct PicoVideo *pv = &Pico.video;
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int lc = SekCyclesDone()-Pico.t.m68c_line_start;
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int burn = 0, x, head = 0;
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int burn = 0;
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if (pv->fifo_cnt)
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PicoVideoFIFOSync(lc);
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pv->status = (pv->status & ~sr_mask) | sr_flags;
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if (count && fifo_ql < 8) {
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// update FIFO state if it was empty
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if (fifo_ql == 0) {
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fifo_slot = fifo_cyc2sl[(lc+8)>>1]; // FIFO latency ~3 vdp slots
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pv->fifo_cnt = count << (flags & FQ_BYTE);
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pv->status |= PVS_FIFORUN;
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}
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if (count && vf->fifo_ql < 8) {
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// determine queue position for entry
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x = (fifo_qx + fifo_ql - 1) & 7;
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if (fifo_ql && (fifo_queue[x] & FQ_BGDMA)) {
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int x = (vf->fifo_qx + vf->fifo_ql - 1) & 7;
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if (unlikely(vf->fifo_ql && (vf->fifo_queue[x] & FQ_BGDMA))) {
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// CPU FIFO writes have priority over a background DMA Fill/Copy
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fifo_queue[(x+1) & 7] = fifo_queue[x];
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if (x == fifo_qx) { // overtaking to queue head?
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// XXX if interrupting a DMA fill, fill data changes
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int f = fifo_queue[x] & 7;
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fifo_queue[(x+1) & 7] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;
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pv->fifo_cnt = count << (flags & FQ_BYTE);
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head = 1;
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}
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// XXX if interrupting a DMA fill, fill data changes
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if (x == vf->fifo_qx) { // overtaking to queue head?
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int f = vf->fifo_queue[x] & 7;
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vf->fifo_queue[(x+1) & 7] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;
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pv->status &= ~PVS_FIFORUN;
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} else
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// push background DMA back
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vf->fifo_queue[(x+1) & 7] = vf->fifo_queue[x];
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x = (x-1) & 7;
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}
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// create xfer queue entry
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if (fifo_ql && !head && (fifo_queue[x] & 7) == flags) {
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if ((pv->status & PVS_FIFORUN) && (vf->fifo_queue[x] & 7) == flags) {
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// amalgamate entries if of same type
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fifo_queue[x] += (count << 3);
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if (x == fifo_qx) // modifiying fifo head, adjust count
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vf->fifo_queue[x] += (count << 3);
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if (x == vf->fifo_qx)
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pv->fifo_cnt += count << (flags & FQ_BYTE);
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} else {
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fifo_ql ++;
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// create new xfer queue entry
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vf->fifo_ql ++;
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x = (x+1) & 7;
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fifo_queue[x] = (count << 3) | flags;
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vf->fifo_queue[x] = (count << 3) | flags;
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}
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// update FIFO state if it was empty
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if (!(pv->status & PVS_FIFORUN)) {
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vf->fifo_slot = vf->fifo_cyc2sl[(lc+8)>>1]; // FIFO latency ~3 vdp slots
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pv->status |= PVS_FIFORUN;
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pv->fifo_cnt = count << (flags & FQ_BYTE);
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}
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if (!(flags & FQ_BGDMA))
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fifo_total += count;
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vf->fifo_total += count;
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}
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// if CPU is waiting for the bus, advance CPU and FIFO until bus is free
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@ -257,11 +275,12 @@ int PicoVideoFIFOWrite(int count, int flags, unsigned sr_mask,unsigned sr_flags)
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// at HINT, advance FIFO to new scanline
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int PicoVideoFIFOHint(void)
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{
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struct VdpFIFO *vf = &VdpFIFO;
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struct PicoVideo *pv = &Pico.video;
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int burn = 0;
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// reset slot to start of scanline
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fifo_slot = 0;
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vf->fifo_slot = 0;
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// if CPU is waiting for the bus, advance CPU and FIFO until bus is free
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if (pv->status & PVS_CPURD)
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@ -280,18 +299,19 @@ void PicoVideoFIFOMode(int active, int h40)
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static const unsigned short *vdpsl2cyc[2][2] =
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{ {vdpsl2cyc_32_bl, vdpsl2cyc_40_bl} , {vdpsl2cyc_32, vdpsl2cyc_40} };
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struct VdpFIFO *vf = &VdpFIFO;
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struct PicoVideo *pv = &Pico.video;
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int lc = SekCyclesDone() - Pico.t.m68c_line_start;
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active = active && !(pv->status & PVS_VB2);
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if (fifo_maxslot)
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if (vf->fifo_maxslot)
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PicoVideoFIFOSync(lc);
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fifo_cyc2sl = vdpcyc2sl[active][h40];
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fifo_sl2cyc = vdpsl2cyc[active][h40];
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vf->fifo_cyc2sl = vdpcyc2sl[active][h40];
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vf->fifo_sl2cyc = vdpsl2cyc[active][h40];
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// recalculate FIFO slot for new mode
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fifo_slot = fifo_cyc2sl[lc>>1]-1;
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fifo_maxslot = fifo_cyc2sl[488>>1];
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vf->fifo_slot = vf->fifo_cyc2sl[lc>>1]-1;
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vf->fifo_maxslot = vf->fifo_cyc2sl[488>>1];
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}
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@ -342,7 +362,7 @@ static void VideoWrite(u16 d)
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static unsigned int VideoRead(void)
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{
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unsigned int a, d = fifo_data[(fifo_dx+1)&3];
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unsigned int a, d = VdpFIFO.fifo_data[(VdpFIFO.fifo_dx+1)&3];
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a=Pico.video.addr; a>>=1;
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@ -351,7 +371,6 @@ static unsigned int VideoRead(void)
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{
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case 0: d=PicoMem.vram [a & 0x7fff]; break;
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case 8: d=PicoMem.cram [a & 0x003f] | (d & ~0x0eee); break;
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case 4: if ((a & 0x3f) >= 0x28) a = 0;
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d=PicoMem.vsram [a & 0x003f] | (d & ~0x07ff); break;
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case 12:a=PicoMem.vram [a & 0x7fff]; if (Pico.video.addr&1) a >>= 8;
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@ -618,8 +637,9 @@ static NOINLINE void CommandDma(void)
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PicoVideoFIFOSync(SekCyclesDone()-Pico.t.m68c_line_start);
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if (pvid->status & SR_DMA) {
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elprintf(EL_VDPDMA, "Dma overlap, left=%d @ %06x",
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fifo_total, SekPc);
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pvid->fifo_cnt = fifo_total = fifo_ql = 0;
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VdpFIFO.fifo_total, SekPc);
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pvid->fifo_cnt = VdpFIFO.fifo_total = VdpFIFO.fifo_ql = 0;
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pvid->status &= ~(PVS_FIFORUN|PVS_DMAFILL);
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}
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len = GetDmaLength();
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@ -704,7 +724,7 @@ PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d)
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if (!(PicoIn.opt&POPT_DIS_VDP_FIFO))
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{
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fifo_data[++fifo_dx&3] = d;
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VdpFIFO.fifo_data[++VdpFIFO.fifo_dx&3] = d;
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SekCyclesBurnRun(PicoVideoFIFOWrite(1, pvid->type == 1, 0, PVS_CPUWR));
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elprintf(EL_ASVDP, "VDP data write: [%04x] %04x [%u] {%i} @ %06x",
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@ -714,7 +734,7 @@ PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d)
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// start DMA fill on write. NB VSRAM and CRAM fills use wrong FIFO data.
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if (pvid->status & PVS_DMAFILL)
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DmaFill(fifo_data[(fifo_dx + !!(pvid->type&~0x81))&3]);
|
||||
DmaFill(VdpFIFO.fifo_data[(VdpFIFO.fifo_dx + !!(pvid->type&~0x81))&3]);
|
||||
|
||||
break;
|
||||
|
||||
|
|
@ -860,9 +880,9 @@ static u32 VideoSr(const struct PicoVideo *pv)
|
|||
d |= SR_HB;
|
||||
|
||||
PicoVideoFIFOSync(c);
|
||||
if (fifo_total >= 4)
|
||||
if (VdpFIFO.fifo_total >= 4)
|
||||
d |= SR_FULL;
|
||||
else if (!fifo_total)
|
||||
else if (!VdpFIFO.fifo_total)
|
||||
d |= SR_EMPT;
|
||||
return d;
|
||||
}
|
||||
|
|
@ -974,16 +994,18 @@ unsigned char PicoVideoRead8HV_L(void)
|
|||
|
||||
void PicoVideoSave(void)
|
||||
{
|
||||
struct VdpFIFO *vf = &VdpFIFO;
|
||||
struct PicoVideo *pv = &Pico.video;
|
||||
int l, x;
|
||||
|
||||
// account for all outstanding xfers XXX kludge, entry attr's not saved
|
||||
for (l = fifo_ql, x = fifo_qx + l-1; l > 1; l--, x--)
|
||||
pv->fifo_cnt += (fifo_queue[x&7] >> 3) << (fifo_queue[x&7] & FQ_BYTE);
|
||||
for (l = vf->fifo_ql, x = vf->fifo_qx + l-1; l > 1; l--, x--)
|
||||
pv->fifo_cnt += (vf->fifo_queue[x&7] >> 3) << (vf->fifo_queue[x&7] & FQ_BYTE);
|
||||
}
|
||||
|
||||
void PicoVideoLoad(void)
|
||||
{
|
||||
struct VdpFIFO *vf = &VdpFIFO;
|
||||
struct PicoVideo *pv = &Pico.video;
|
||||
int l;
|
||||
|
||||
|
|
@ -991,7 +1013,7 @@ void PicoVideoLoad(void)
|
|||
if (Pico.m.dma_xfers) {
|
||||
pv->status = SR_DMA|PVS_FIFORUN;
|
||||
pv->fifo_cnt = Pico.m.dma_xfers * (pv->type == 1 ? 2 : 1);
|
||||
fifo_total = Pico.m.dma_xfers;
|
||||
vf->fifo_total = Pico.m.dma_xfers;
|
||||
Pico.m.dma_xfers = 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue