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sh2 drc: optimize T bit handling for A64

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This commit is contained in:
kub 2019-12-21 16:33:52 +01:00
parent a5e51c16e6
commit 0e12269073
4 changed files with 58 additions and 38 deletions
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5
cpu/drc/emit_riscv.c
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@ -87,8 +87,6 @@ enum { F1_B, F1_H, F1_W, F1_D, F1_BU, F1_HU, F1_WU }; // LD/ST
// func7
enum { F2_ALT=0x20, F2_MULDIV=0x01 };
#define __(n) o##n // enum marker for "undefined"
#define R5_NOP R5_I_INSN(OP_IMM, F1_ADD, Z0, Z0, 0) // nop: ADDI r0, r0, #0
// arithmetic/logical
@ -687,9 +685,8 @@ static void emith_pool_check(void)
static void emith_move_imm(int r, uintptr_t imm)
{
u32 lui = imm + _CB(imm,1,11,12);
u32 lui = imm + _CB(imm,1,11,12); // compensate for ADDI sign extension
if (lui >> 12) {
// take out the effect of the sign extension of ADDI
EMIT(R5_MOVT_IMM(r, lui));
if (imm & 0xfff)
EMIT(R5_ADD_IMM(r, r, imm));