mirror of
https://github.com/RaySollium99/picodrive.git
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svp compiler: all ops implemented, EXT regs left
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@376 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
6e39239fb9
commit
0e4d7ba5f4
2 changed files with 241 additions and 66 deletions
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@ -12,7 +12,7 @@ static int nblocks = 0;
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static int iram_context = 0;
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#ifndef ARM
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#define DUMP_BLOCK 0x341e
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#define DUMP_BLOCK 0x08aa
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unsigned int tcache[512*1024];
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void regfile_load(void){}
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void regfile_store(void){}
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@ -590,16 +590,17 @@ static void tr_unhandled(void)
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exit(1);
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}
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/* update P, if needed. Trashes r1 */
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/* update P, if needed. Trashes r0 */
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static void tr_flush_dirty_P(void)
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{
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// TODO: const regs
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if (!(dirty_regb & KRREG_P)) return;
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EOP_MOV_REG_ASR(10, 4, 16); // mov r10, r4, asr #16
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EOP_MOV_REG_LSL( 1, 4, 16); // mov r1, r4, lsl #16
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EOP_MOV_REG_ASR( 1, 1, 15); // mov r1, r1, asr #15
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EOP_MUL(10, 1, 10); // mul r10, r1, r10
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EOP_MOV_REG_LSL( 0, 4, 16); // mov r0, r4, lsl #16
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EOP_MOV_REG_ASR( 0, 0, 15); // mov r0, r0, asr #15
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EOP_MUL(10, 0, 10); // mul r10, r0, r10
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dirty_regb &= ~KRREG_P;
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hostreg_r[0] = -1;
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}
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/* write dirty pr to host reg. Nothing is trashed */
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@ -693,7 +694,7 @@ static void tr_mov16_cond(int cond, int r, int val)
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hostreg_r[r] = -1;
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}
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/* read bank word to r0. Thrashes r1. */
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/* read bank word to r0 (upper bits zero). Thrashes r1. */
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static void tr_bank_read(int addr) /* word addr 0-0x1ff */
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{
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int breg = 7;
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@ -740,9 +741,16 @@ static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
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{
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int reg = (r < 4) ? 8 : 9;
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tr_release_pr(r);
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tr_flush_dirty_ST();
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EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands r1, r6, #0x70
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EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
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if (dirty_regb & KRREG_ST) {
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// avoid flushing ARM flags
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EOP_AND_IMM(1, 6, 0, 0x70);
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EOP_SUB_IMM(1, 1, 0, 0x10);
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EOP_AND_IMM(1, 1, 0, 0x70);
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EOP_ADD_IMM(1, 1, 0, 0x10);
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} else {
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EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands r1, r6, #0x70
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EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
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}
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EOP_MOV_REG_LSR(1, 1, 4); // mov r1, r1, lsr #4
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EOP_RSB_IMM(2, 1, 0, 8); // rsb r1, r1, #8
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EOP_MOV_IMM(3, 8/2, count); // mov r3, #0x01000000
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@ -776,7 +784,7 @@ static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
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/* handle writes r0 to (rX). Trashes r1.
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* fortunately we can ignore modulo increment modes for writes. */
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static void tr_rX_write1(int op)
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static void tr_rX_write(int op)
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{
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if ((op&3) == 3)
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{
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@ -823,12 +831,45 @@ static void tr_rX_read(int r, int mod)
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if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
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else EOP_ADD_REG_LSL(1,7,1,1);
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EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
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hostreg_r[1] = -1;
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hostreg_r[0] = hostreg_r[1] = -1;
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}
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tr_ptrr_mod(r, mod, 1, 1);
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}
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}
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/* read ((rX)) to r0. Trashes r1,r2. */
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static void tr_rX_read2(int op)
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{
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int r = (op&3) | ((op>>6)&4); // src
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if ((r&3) == 3) {
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tr_bank_read((op&0x100) | ((op>>2)&3));
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} else if (known_regb & (1 << (r+8))) {
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tr_bank_read((op&0x100) | known_regs.r[r]);
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} else {
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int reg = (r < 4) ? 8 : 9;
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int ror = ((4 - (r&3))*8) & 0x1f;
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EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
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if (r >= 4)
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EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
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if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
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else EOP_ADD_REG_LSL(1,7,1,1);
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EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
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}
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EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom
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EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1
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EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1
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if ((r&3) == 3) {
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tr_bank_write((op&0x100) | ((op>>2)&3));
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} else if (known_regb & (1 << (r+8))) {
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tr_bank_write((op&0x100) | known_regs.r[r]);
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} else {
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EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
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hostreg_r[1] = -1;
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}
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EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2]
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hostreg_r[0] = hostreg_r[2] = -1;
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}
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/* get ARM cond which would mean that SSP cond is satisfied. No trash. */
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static int tr_cond_check(int op)
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@ -1036,10 +1077,37 @@ static tr_write_func *tr_write_funcs[8] =
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(tr_write_func *)tr_unhandled
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};
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static void tr_mac_load_XY(int op)
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{
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tr_rX_read(op&3, (op>>2)&3); // X
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EOP_MOV_REG_LSL(4, 0, 16);
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tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y
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EOP_ORR_REG_SIMPLE(4, 0);
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dirty_regb |= KRREG_P;
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hostreg_sspreg_changed(SSP_X);
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hostreg_sspreg_changed(SSP_Y);
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known_regb &= ~KRREG_X;
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known_regb &= ~KRREG_Y;
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}
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static int tr_aop_ssp2arm(int op)
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{
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switch (op) {
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case 1: return A_OP_SUB;
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case 3: return A_OP_CMP;
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case 4: return A_OP_ADD;
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case 5: return A_OP_AND;
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case 6: return A_OP_ORR;
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case 7: return A_OP_EOR;
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}
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tr_unhandled();
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return 0;
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}
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static int translate_op(unsigned int op, int *pc, int imm)
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{
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u32 tmpv, tmpv2;
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u32 tmpv, tmpv2, tmpv3;
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int ret = 0;
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known_regs.gr[SSP_PC].h = *pc;
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@ -1081,7 +1149,7 @@ static int translate_op(unsigned int op, int *pc, int imm)
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tmpv = (op >> 4) & 0xf; // src
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if (tmpv >= 8) return -1; // TODO
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tr_read_funcs[tmpv]();
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tr_rX_write1(op);
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tr_rX_write(op);
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ret++; break;
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// ld a, adr
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@ -1129,47 +1197,17 @@ static int translate_op(unsigned int op, int *pc, int imm)
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return -1; /* TODO.. */
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// ld d, ((ri))
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case 0x05: {
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int r;
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r = (op&3) | ((op>>6)&4); // src
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case 0x05:
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tmpv2 = (op >> 4) & 0xf; // dst
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if (tmpv2 >= 8) return -1; // TODO
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if ((r&3) == 3) {
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tr_bank_read((op&0x100) | ((op>>2)&3));
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} else if (known_regb & (1 << (r+8))) {
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tr_bank_read((op&0x100) | known_regs.r[r]);
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} else {
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int reg = (r < 4) ? 8 : 9;
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int ror = ((4 - (r&3))*8) & 0x1f;
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EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
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if (r >= 4)
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EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
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if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
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else EOP_ADD_REG_LSL(1,7,1,1);
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EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
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}
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EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom
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EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1
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EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1
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if ((r&3) == 3) {
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tr_bank_write((op&0x100) | ((op>>2)&3));
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} else if (known_regb & (1 << (r+8))) {
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tr_bank_write((op&0x100) | known_regs.r[r]);
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} else {
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EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
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hostreg_r[1] = -1;
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}
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EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2]
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hostreg_r[0] = hostreg_r[2] = -1;
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tr_rX_read2(op);
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tr_write_funcs[tmpv2](-1);
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ret += 3; break; /* should certainly take > 1 */
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}
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ret += 3; break;
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// ldi (ri), imm
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case 0x06:
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tr_mov16(0, imm);
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tr_rX_write1(op);
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tr_rX_write(op);
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ret += 2; break;
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// ld adr, a
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@ -1307,35 +1345,171 @@ static int translate_op(unsigned int op, int *pc, int imm)
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known_regb &= ~(KRREG_A|KRREG_AL);
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ret += tmpv; break;
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}
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/*
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// mpys?
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case 0x1b:
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read_P(); // update P
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rA32 -= rP.v; // maybe only upper word?
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UPD_ACC_ZN // there checking flags after this
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
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break;
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tr_flush_dirty_P();
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tr_mac_load_XY(op);
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tr_make_dirty_ST();
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EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10
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hostreg_sspreg_changed(SSP_A);
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known_regb &= ~(KRREG_A|KRREG_AL);
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dirty_regb |= KRREG_ST;
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ret++; break;
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// mpya (rj), (ri), b
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case 0x4b:
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read_P(); // update P
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rA32 += rP.v; // confirmed to be 32bit
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UPD_ACC_ZN // ?
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rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
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rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
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break;
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tr_flush_dirty_P();
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tr_mac_load_XY(op);
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tr_make_dirty_ST();
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EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10
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hostreg_sspreg_changed(SSP_A);
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known_regb &= ~(KRREG_A|KRREG_AL);
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dirty_regb |= KRREG_ST;
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ret++; break;
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// mld (rj), (ri), b
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case 0x5b:
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EOP_MOV_IMM(5, 0, 0); // mov r5, #0
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known_regs.r[SSP_A].v = 0;
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EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0
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hostreg_sspreg_changed(SSP_A);
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known_regs.gr[SSP_A].v = 0;
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known_regb |= (KRREG_A|KRREG_AL);
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EOP_BIC_IMM(6, 6, 0, 0x0f); // bic r6, r6, 0xf // flags
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EOP_BIC_IMM(6, 6, 0, 0x04); // bic r6, r6, 4 // set Z
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// TODO
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dirty_regb |= KRREG_ST;
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tr_mac_load_XY(op);
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ret++; break;
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// OP a, s
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case 0x10:
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case 0x30:
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case 0x40:
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case 0x50:
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case 0x60:
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case 0x70:
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tmpv = op & 0xf; // src
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tmpv2 = tr_aop_ssp2arm(op>>13); // op
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tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
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if (tmpv >= 8) return -1; // TODO
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if (tmpv == SSP_P) {
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tr_flush_dirty_P();
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EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10
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} else if (tmpv == SSP_A) {
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EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5
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} else {
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tr_read_funcs[tmpv]();
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EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16
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}
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hostreg_sspreg_changed(SSP_A);
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known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
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dirty_regb |= KRREG_ST;
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ret++; break;
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// OP a, (ri)
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case 0x11:
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case 0x31:
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case 0x41:
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case 0x51:
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case 0x61:
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case 0x71:
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tmpv2 = tr_aop_ssp2arm(op>>13); // op
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tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
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tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3);
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EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
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hostreg_sspreg_changed(SSP_A);
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known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
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dirty_regb |= KRREG_ST;
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ret++; break;
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// OP a, adr
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case 0x13:
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case 0x33:
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case 0x43:
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case 0x53:
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case 0x63:
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case 0x73:
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tmpv2 = tr_aop_ssp2arm(op>>13); // op
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tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
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tr_bank_read(op&0x1ff);
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EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
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hostreg_sspreg_changed(SSP_A);
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known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
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dirty_regb |= KRREG_ST;
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ret++; break;
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// OP a, imm
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case 0x14:
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case 0x34:
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case 0x44:
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case 0x54:
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case 0x64:
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case 0x74:
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tmpv = (op & 0xf0) >> 4;
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tmpv2 = tr_aop_ssp2arm(op>>13); // op
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tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
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tr_mov16(0, imm);
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EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
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hostreg_sspreg_changed(SSP_A);
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known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
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dirty_regb |= KRREG_ST;
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ret += 2; break;
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// OP a, ((ri))
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case 0x15:
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case 0x35:
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case 0x45:
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case 0x55:
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case 0x65:
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case 0x75:
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tmpv2 = tr_aop_ssp2arm(op>>13); // op
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tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
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tr_rX_read2(op);
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EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
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hostreg_sspreg_changed(SSP_A);
|
||||
known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
|
||||
dirty_regb |= KRREG_ST;
|
||||
ret += 3; break;
|
||||
|
||||
// OP a, ri
|
||||
case 0x19:
|
||||
case 0x39:
|
||||
case 0x49:
|
||||
case 0x59:
|
||||
case 0x69:
|
||||
case 0x79: {
|
||||
int r;
|
||||
tmpv2 = tr_aop_ssp2arm(op>>13); // op
|
||||
tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
|
||||
r = (op&3) | ((op>>6)&4); // src
|
||||
if ((r&3) == 3) tr_unhandled();
|
||||
|
||||
if (known_regb & (1 << (r+8))) {
|
||||
EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]); // OPs r5, r5, #val<<16
|
||||
} else {
|
||||
int reg = (r < 4) ? 8 : 9;
|
||||
if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
|
||||
EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
|
||||
EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
|
||||
hostreg_r[0] = -1;
|
||||
}
|
||||
hostreg_sspreg_changed(SSP_A);
|
||||
known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
|
||||
dirty_regb |= KRREG_ST;
|
||||
ret++; break;
|
||||
}
|
||||
|
||||
// OP simm
|
||||
case 0x1c:
|
||||
case 0x3c:
|
||||
case 0x4c:
|
||||
case 0x5c:
|
||||
case 0x6c:
|
||||
case 0x7c:
|
||||
tmpv2 = tr_aop_ssp2arm(op>>13); // op
|
||||
tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
|
||||
EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff); // OPs r5, r5, #val<<16
|
||||
hostreg_sspreg_changed(SSP_A);
|
||||
known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
|
||||
dirty_regb |= KRREG_ST;
|
||||
ret++; break;
|
||||
*/
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue