mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
mcd, fixes and improvements by mcd-verificator
This commit is contained in:
kub
parent
44a6c67823
commit
178a9b683c
6 changed files with 164 additions and 127 deletions
126
pico/cd/cdc.c
126
pico/cd/cdc.c
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@ -244,65 +244,66 @@ int cdc_context_load_old(uint8 *state)
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#undef old_load
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}
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static void do_dma(enum dma_type type, int words_in)
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static void do_dma(enum dma_type type, int bytes_in)
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{
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int dma_addr = (Pico_mcd->s68k_regs[0x0a] << 8) | Pico_mcd->s68k_regs[0x0b];
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int dma_addr = (Pico_mcd->s68k_regs[0x0a] << 8) | Pico_mcd->s68k_regs[0x0b];
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int src_addr = cdc.dac & 0x3ffe;
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int dst_addr = dma_addr;
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int words = words_in;
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int bytes = bytes_in;
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int words = bytes_in >> 1;
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int dst_limit = 0;
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uint8 *dst;
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int len;
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elprintf(EL_CD, "dma %d %04x->%04x %x",
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type, cdc.dac, dst_addr, words_in);
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type, cdc.dac, dst_addr, bytes_in);
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switch (type)
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{
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case pcm_ram_dma_w:
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dst_addr = (dst_addr << 2) & 0xffc;
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if (dst_addr + words * 2 > 0x1000) {
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if (dst_addr + bytes > 0x1000) {
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elprintf(EL_ANOMALY, "pcm dma oflow: %x %x", dst_addr, words);
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words = (0x1000 - dst_addr) / 2;
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bytes = 0x1000 - dst_addr;
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}
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dst = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank];
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dst = dst + dst_addr;
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while (words > 0)
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while (bytes > 0)
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{
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if (src_addr + words * 2 > 0x4000) {
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if (src_addr + bytes > 0x4000) {
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len = 0x4000 - src_addr;
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memcpy(dst, cdc.ram + src_addr, len);
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dst += len;
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src_addr = 0;
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words -= len / 2;
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bytes -= len;
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continue;
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}
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memcpy(dst, cdc.ram + src_addr, words * 2);
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memcpy(dst, cdc.ram + src_addr, bytes);
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break;
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}
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goto update_dma;
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case prg_ram_dma_w:
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dst_addr <<= 3;
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dst = Pico_mcd->prg_ram + dst_addr;
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dst = Pico_mcd->prg_ram + dst_addr;
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dst_limit = 0x80000;
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break;
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case word_ram_0_dma_w:
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dst_addr = (dst_addr << 3) & 0x1fffe;
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dst = Pico_mcd->word_ram1M[0] + dst_addr;
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dst = Pico_mcd->word_ram1M[0] + dst_addr;
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dst_limit = 0x20000;
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break;
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case word_ram_1_dma_w:
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dst_addr = (dst_addr << 3) & 0x1fffe;
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dst = Pico_mcd->word_ram1M[1] + dst_addr;
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dst = Pico_mcd->word_ram1M[1] + dst_addr;
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dst_limit = 0x20000;
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break;
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case word_ram_2M_dma_w:
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dst_addr = (dst_addr << 3) & 0x3fffe;
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dst = Pico_mcd->word_ram2M + dst_addr;
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dst = Pico_mcd->word_ram2M + dst_addr;
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dst_limit = 0x40000;
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break;
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@ -329,13 +330,15 @@ static void do_dma(enum dma_type type, int words_in)
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break;
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}
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bytes_in &= ~1; // Todo leftover byte?
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update_dma:
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/* update DMA addresses */
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cdc.dac += words_in * 2;
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cdc.dac += bytes_in;
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if (type == pcm_ram_dma_w)
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dma_addr += words_in >> 1;
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dma_addr += bytes_in >> 2;
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else
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dma_addr += words_in >> 2;
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dma_addr += bytes_in >> 3;
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Pico_mcd->s68k_regs[0x0a] = dma_addr >> 8;
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Pico_mcd->s68k_regs[0x0b] = dma_addr;
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@ -348,7 +351,7 @@ void cdc_dma_update(void)
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{
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/* transfer remaining words using 16-bit DMA */
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//cdc.dma_w((cdc.dbc + 1) >> 1);
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do_dma(cdc.dma_w, (cdc.dbc + 1) >> 1);
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do_dma(cdc.dma_w, cdc.dbc + 1);
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/* reset data byte counter (DBCH bits 4-7 should be set to 1) */
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cdc.dbc = 0xf000;
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@ -356,24 +359,26 @@ void cdc_dma_update(void)
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/* clear !DTEN and !DTBSY */
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cdc.ifstat |= (BIT_DTBSY | BIT_DTEN);
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/* pending Data Transfer End interrupt */
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cdc.ifstat &= ~BIT_DTEI;
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/* Data Transfer End interrupt enabled ? */
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if (cdc.ifctrl & BIT_DTEIEN)
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{
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/* level 5 interrupt enabled ? */
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if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
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{
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/* update IRQ level */
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elprintf(EL_INTS, "cdc DTE irq 5");
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pcd_irq_s68k(5, 1);
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}
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}
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/* clear DSR bit & set EDT bit (SCD register $04) */
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Pico_mcd->s68k_regs[0x04+0] = (Pico_mcd->s68k_regs[0x04+0] & 0x07) | 0x80;
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if (cdc.ifstat & BIT_DTEI) {
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/* pending Data Transfer End interrupt */
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cdc.ifstat &= ~BIT_DTEI;
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/* Data Transfer End interrupt enabled ? */
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if (cdc.ifctrl & BIT_DTEIEN)
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{
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/* level 5 interrupt enabled ? */
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if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
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{
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/* update IRQ level */
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elprintf(EL_INTS, "cdc DTE irq 5");
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pcd_irq_s68k(5, 1);
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}
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}
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}
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/* disable DMA transfer */
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cdc.dma_w = 0;
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}
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@ -456,8 +461,11 @@ void cdc_reg_w(unsigned char data)
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#ifdef LOG_CDC
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elprintf(EL_STATUS, "CDC register %X write 0x%04x", Pico_mcd->s68k_regs[0x04+1] & 0x0F, data);
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#endif
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switch (Pico_mcd->s68k_regs[0x04+1] & 0x0F)
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switch (Pico_mcd->s68k_regs[0x04+1] & 0x1F)
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{
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case 0x00:
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break;
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case 0x01: /* IFCTRL */
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{
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/* pending interrupts ? */
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@ -498,7 +506,7 @@ void cdc_reg_w(unsigned char data)
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case 0x03: /* DBCH */
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cdc.dbc &= 0x00ff;
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cdc.dbc |= data << 8;
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cdc.dbc |= (data & 0x0f) << 8;
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Pico_mcd->s68k_regs[0x04+1] = 0x04;
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break;
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@ -638,6 +646,10 @@ void cdc_reg_w(unsigned char data)
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/* set CRCOK bit only if decoding is enabled */
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cdc.stat[0] = data & BIT_DECEN;
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/* reset DECI if decoder turned off */
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if (!cdc.stat[0])
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cdc.ifstat |= BIT_DECI;
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/* update decoding mode */
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if (data & BIT_AUTORQ)
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{
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@ -692,17 +704,22 @@ void cdc_reg_w(unsigned char data)
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case 0x0f: /* RESET */
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cdc_reset();
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Pico_mcd->s68k_regs[0x04+1] = 0x10;
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break;
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default: /* by default, SBOUT is not used */
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Pico_mcd->s68k_regs[0x04+1] = (Pico_mcd->s68k_regs[0x04+1] + 1) & 0x1f;
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break;
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}
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}
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unsigned char cdc_reg_r(void)
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{
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switch (Pico_mcd->s68k_regs[0x04+1] & 0x0F)
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switch (Pico_mcd->s68k_regs[0x04+1] & 0x01F)
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{
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case 0x00:
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return 0xff;
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case 0x01: /* IFSTAT */
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Pico_mcd->s68k_regs[0x04+1] = 0x02;
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return cdc.ifstat;
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@ -778,11 +795,12 @@ unsigned char cdc_reg_r(void)
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}
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#endif
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Pico_mcd->s68k_regs[0x04+1] = 0x00;
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Pico_mcd->s68k_regs[0x04+1] = 0x10;
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return data;
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}
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default: /* by default, COMIN is always empty */
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Pico_mcd->s68k_regs[0x04+1] = (Pico_mcd->s68k_regs[0x04+1] + 1) & 0x1f;
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return 0xff;
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}
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}
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@ -815,23 +833,27 @@ unsigned short cdc_host_r(void)
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/* clear !DTEN and !DTBSY */
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cdc.ifstat |= (BIT_DTBSY | BIT_DTEN);
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/* pending Data Transfer End interrupt */
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cdc.ifstat &= ~BIT_DTEI;
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/* Data Transfer End interrupt enabled ? */
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if (cdc.ifctrl & BIT_DTEIEN)
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{
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/* level 5 interrupt enabled ? */
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if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
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{
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/* update IRQ level */
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elprintf(EL_INTS, "cdc DTE irq 5");
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pcd_irq_s68k(5, 1);
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}
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}
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/* clear DSR bit & set EDT bit (SCD register $04) */
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Pico_mcd->s68k_regs[0x04+0] = (Pico_mcd->s68k_regs[0x04+0] & 0x07) | 0x80;
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} else if ((int16)cdc.dbc <= 2) {
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if (cdc.ifstat & BIT_DTEI) {
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/* pending Data Transfer End interrupt */
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cdc.ifstat &= ~BIT_DTEI;
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/* Data Transfer End interrupt enabled ? */
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if (cdc.ifctrl & BIT_DTEIEN)
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{
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/* level 5 interrupt enabled ? */
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if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
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{
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/* update IRQ level */
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elprintf(EL_INTS, "cdc DTE irq 5");
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pcd_irq_s68k(5, 1);
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}
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}
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}
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/* set DSR and EDT bit (SCD register $04) */
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Pico_mcd->s68k_regs[0x04+0] = (Pico_mcd->s68k_regs[0x04+0] & 0x07) | 0xc0;
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}
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return data;
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