mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-06 07:38:05 -04:00
revised VDP fifo implementation
This commit is contained in:
kub
parent
0f3703fd98
commit
17bd69adc6
5 changed files with 430 additions and 138 deletions
456
pico/videoport.c
456
pico/videoport.c
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@ -14,9 +14,296 @@
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extern const unsigned char hcounts_32[];
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extern const unsigned char hcounts_40[];
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static unsigned hvlatch; // latched hvcounter value
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static int blankline; // display disabled for this line
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int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned int *mask) = NULL;
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/* VDP FIFO implementation
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*
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* fifo_slot: last slot executed in this scanline
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* fifo_cnt: #slots remaining for active FIFO write (#writes<<#bytep)
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* fifo_total: #total FIFO entries pending
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* fifo_data: last values transferred through fifo
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* fifo_queue: fifo transfer queue (#writes, VRAM_byte_p)
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*
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* FIFO states: empty total=0
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* inuse total>0 && total<4
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* full total==4
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* wait total>4
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* Conditions:
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* fifo_slot is always behind slot2cyc[cycles]. Advancing it beyond cycles
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* implies blocking the 68k up to that slot.
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*
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* A FIFO write goes to the end of the fifo queue. There can be more pending
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* writes than FIFO slots, but the 68k will be blocked in most of those cases.
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* This is only about correct timing, data xfer must be handled by the caller.
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* Blocking the CPU means burning cycles via SekCyclesBurn*(), which is to be
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* executed by the caller.
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*
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* FIFOSync "executes" FIFO write slots up to the given cycle in the current
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* scanline. A queue entry completely executed is removed from the queue.
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* FIFOWrite pushes writes to the transfer queue. If it's a blocking write, 68k
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* is blocked if more than 4 FIFO writes are pending.
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* FIFORead executes a 68k read. 68k is blocked until the next transfer slot.
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*/
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// FIFO transfer slots per line: H32 blank, H40 blank, H32 active, H40 active
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static const short vdpslots[] = { 166, 204, 16, 18 };
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// mapping between slot# and 68k cycles in a blanked scanline
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static const int vdpcyc2sl_bl[] = { (166<<16)/488, (204<<16)/488, (16<<16)/488, (18<<16)/488 };
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static const int vdpsl2cyc_bl[] = { (488<<16)/166, (488<<16)/204, (488<<16)/16, (488<<16)/18 };
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// VDP transfer slots in active display 32col mode. 1 slot is 488/171 = 2.8538
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// 68k cycles. Only 16 of the 171 slots in a scanline can be used by CPU/DMA:
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// (HINT=slot 0): 13,27,42,50,58,74,82,90,106,114,122,138,146,154,169,170
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const unsigned char vdpcyc2sl_32[] = { // 68k cycles/4 since HINT to slot #
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// 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
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0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
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3, 3, 3, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7,
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8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9,
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9,10,10,10,10,10,10,11,11,11,11,11,11,11,11,11,
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11,11,12,12,12,12,12,12,13,13,13,13,13,13,14,14,
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14,14,14,14,14,14,14,14,15,16,16,16,16,16,16,16,
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};
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const unsigned char vdpsl2cyc_32[] = { // slot # to 68k cycles/4 since HINT
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0, 9, 19, 30, 35, 41, 52, 58, 64, 75, 81, 87, 98,104,110,120,121,123,123
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};
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// VDP transfer slots in active display 40col mode. 1 slot is 488/210 = 2.3238
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// 68k cycles. Only 18 of the 210 slots in a scanline can be used by CPU/DMA:
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// (HINT=0): 23,49,57,65,81,89,97,113,121,129,145,153,161,177,185,193,208,209
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const unsigned char vdpcyc2sl_40[] = { // 68k cycles/4 since HINT to slot #
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// 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
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2, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5,
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5, 5, 5, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 8, 8, 8, 8, 8, 9, 9, 9, 9,10,10,10,10,10,10,
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10,10,10,10,11,11,11,11,12,12,12,12,12,13,13,13,
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13,13,13,13,13,13,14,14,14,14,14,15,15,15,15,15,
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16,16,16,16,16,16,16,16,17,18,18,18,18,18,18,18,
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};
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const unsigned char vdpsl2cyc_40[] = { // slot # to 68k cycles/4 since HINT
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0, 13, 28, 33, 37, 47, 51, 56, 65, 70, 74, 84, 88, 93,102,107,112,120,121,123,123
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};
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// NB code assumes fifo_* arrays have size 2^n
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// last transferred FIFO data, ...x = index XXX currently only CPU
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static short fifo_data[4], fifo_dx;
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// queued FIFO transfers, ...x = index, ...l = queue length
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// each entry has 2 values: [n]>>1=#writes, [n]&1=is VRAM byte access
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static int fifo_queue[8], fifo_qx, fifo_ql;
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signed int fifo_cnt; // pending slots for current queue entry
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unsigned short fifo_slot; // last executed slot in current scanline
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unsigned int fifo_total; // total# of pending FIFO entries
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// sync FIFO to cycles
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void PicoVideoFIFOSync(int cycles)
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{
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struct PicoVideo *pv = &Pico.video;
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int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);
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int h40 = pv->reg[12] & 1;
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const unsigned char *cs = h40 ? vdpcyc2sl_40 : vdpcyc2sl_32;
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int slots, done;
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// calculate #slots since last executed slot
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if (active) slots = cs[cycles/4];
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else slots = (cycles * vdpcyc2sl_bl[h40] + cycles) >> 16;
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slots -= fifo_slot;
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// advance FIFO queue by #done slots
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done = slots;
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while (done > 0 && fifo_ql) {
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int l = done, b = fifo_queue[fifo_qx&7] & 1;
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if (l > fifo_cnt)
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l = fifo_cnt;
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fifo_total -= ((fifo_cnt & b) + l) >> b;
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fifo_slot += l;
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fifo_cnt -= l;
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done -= l;
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if (fifo_cnt == 0) {
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fifo_qx ++, fifo_ql --;
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fifo_cnt= (fifo_queue[fifo_qx&7] >> 1) << (fifo_queue[fifo_qx&7] & 1);
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}
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}
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// release CPU and terminate DMA if FIFO isn't blocking the 68k anymore
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if (fifo_total <= 4) {
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pv->status &= ~PVS_CPUWR;
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pv->command &= ~0x80;
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if (!(pv->status & PVS_DMAPEND))
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pv->status &= ~(SR_DMA|PVS_DMAFILL);
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}
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if (fifo_total == 0)
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pv->status &= ~PVS_CPURD;
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}
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// drain FIFO, blocking 68k on the way. FIFO must be synced prior to drain.
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int PicoVideoFIFODrain(int level, int cycles)
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{
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struct PicoVideo *pv = &Pico.video;
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int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);
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int h40 = pv->reg[12] & 1;
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const unsigned char *sc = h40 ? vdpsl2cyc_40 : vdpsl2cyc_32;
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int maxsl = vdpslots[h40 + 2*active]; // max xfer slots in this scanline
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int burn = 0;
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while (fifo_total > level && fifo_slot < maxsl) {
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int b = fifo_queue[fifo_qx&7] & 1;
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int cnt = (fifo_total-level) << b;
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int last = fifo_slot;
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int slot = (fifo_cnt<cnt?fifo_cnt:cnt) + last; // target slot
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unsigned ocyc = cycles;
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if (slot > maxsl) {
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// target in later scanline, advance to eol
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slot = maxsl;
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fifo_slot = maxsl;
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cycles = 488;
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} else {
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// advance FIFO to target slot and CPU to cycles at that slot
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fifo_slot = slot;
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if (active) cycles = sc[slot]*4;
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else cycles = ((slot * vdpsl2cyc_bl[h40] + slot) >> 16);
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}
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burn += cycles - ocyc;
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slot -= last;
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fifo_total -= ((fifo_cnt & b) + slot) >> b;
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fifo_cnt -= slot;
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if (fifo_cnt == 0) {
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fifo_qx ++, fifo_ql --;
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fifo_cnt= (fifo_queue[fifo_qx&7] >> 1) << (fifo_queue[fifo_qx&7] & 1);
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}
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}
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// release CPU and terminate DMA if FIFO isn't blocking the bus anymore
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if (fifo_total <= 4) {
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pv->status &= ~PVS_CPUWR;
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pv->command &= ~0x80;
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if (!(pv->status & PVS_DMAPEND))
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pv->status &= ~(SR_DMA|PVS_DMAFILL);
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}
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if (fifo_total == 0)
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pv->status &= ~PVS_CPURD;
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return burn;
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}
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// read VDP data port
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int PicoVideoFIFORead(void)
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{
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struct PicoVideo *pv = &Pico.video;
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int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);
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int h40 = pv->reg[12] & 1;
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const unsigned char *cs = h40 ? vdpcyc2sl_40 : vdpcyc2sl_32;
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const unsigned char *sc = h40 ? vdpsl2cyc_40 : vdpsl2cyc_32;
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int lc = SekCyclesDone()-Pico.t.m68c_line_start+4;
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int burn = 0;
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PicoVideoFIFOSync(lc);
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// advance FIFO and CPU until FIFO is empty
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burn = PicoVideoFIFODrain(0, lc);
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lc += burn;
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if (fifo_total > 0)
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pv->status |= PVS_CPURD; // target slot is in later scanline
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else {
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// use next VDP access slot for reading, block 68k until then
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if (active) {
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fifo_slot = cs[lc/4] + 1;
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burn += sc[fifo_slot]*4;
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} else {
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fifo_slot = ((lc * vdpcyc2sl_bl[h40] + lc) >> 16) + 1;
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burn += ((fifo_slot * vdpsl2cyc_bl[h40] + fifo_slot) >> 16);
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}
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burn -= lc;
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}
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return burn;
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}
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// write VDP data port
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int PicoVideoFIFOWrite(int count, int byte_p, unsigned sr_mask,unsigned sr_flags)
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{
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struct PicoVideo *pv = &Pico.video;
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int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);
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int h40 = pv->reg[12] & 1;
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const unsigned char *cs = h40 ? vdpcyc2sl_40 : vdpcyc2sl_32;
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int lc = SekCyclesDone()-Pico.t.m68c_line_start+4;
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int burn = 0;
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PicoVideoFIFOSync(lc);
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pv->status = (pv->status & ~sr_mask) | sr_flags;
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if (count) {
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// update FIFO state if it was empty
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if (fifo_total == 0 && count) {
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if (active) fifo_slot = cs[lc/4];
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else fifo_slot = (lc * vdpcyc2sl_bl[h40] + lc) >> 16;
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fifo_cnt = count << byte_p;
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}
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// create xfer queue entry
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int x = (fifo_qx + fifo_ql) & 7;
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fifo_queue[x] = (count << 1) | byte_p;
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fifo_ql ++;
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fifo_total += count;
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}
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// if CPU is waiting for the bus, advance CPU and FIFO until bus is free
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if ((pv->status & (PVS_CPUWR|PVS_DMAFILL)) == PVS_CPUWR)
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burn = PicoVideoFIFODrain(4, lc);
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return burn;
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}
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// at HINT, advance FIFO to new scanline
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int PicoVideoFIFOHint(void)
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{
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struct PicoVideo *pv = &Pico.video;
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int burn = 0;
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// reset slot to start of scanline
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fifo_slot = 0;
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// if CPU is waiting for the bus, advance CPU and FIFO until bus is free
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if (pv->status & PVS_CPURD)
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burn = PicoVideoFIFORead();
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if (pv->status & PVS_CPUWR)
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burn = PicoVideoFIFOWrite(0, 0, 0, 0);
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return burn;
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}
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// switch FIFO mode between active/inactive display
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void PicoVideoFIFOMode(int active)
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{
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struct PicoVideo *pv = &Pico.video;
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const unsigned char *cs = pv->reg[12]&1 ? vdpcyc2sl_40 : vdpcyc2sl_32;
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int h40 = pv->reg[12] & 1;
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int lc = SekCyclesDone() - Pico.t.m68c_line_start;
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PicoVideoFIFOSync(lc);
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if (fifo_total) {
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// recalculate FIFO slot for new mode
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if (!(pv->status & SR_VB) && active)
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fifo_slot = cs[lc/4];
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else fifo_slot = ((lc * vdpcyc2sl_bl[h40] + lc) >> 16);
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}
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}
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// VDP memory rd/wr
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static __inline void AutoIncrement(void)
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{
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Pico.video.addr=(unsigned short)(Pico.video.addr+Pico.video.reg[0xf]);
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@ -60,15 +347,19 @@ static void VideoWrite(u16 d)
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static unsigned int VideoRead(void)
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{
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unsigned int a=0,d=0;
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unsigned int a, d = fifo_data[(fifo_dx+1)&3];
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a=Pico.video.addr; a>>=1;
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SekCyclesBurnRun(PicoVideoFIFORead());
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switch (Pico.video.type)
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{
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case 0: d=PicoMem.vram [a & 0x7fff]; break;
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case 8: d=PicoMem.cram [a & 0x003f]; break;
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case 4: d=PicoMem.vsram[a & 0x003f]; break;
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case 8: d=(PicoMem.cram [a & 0x003f] & 0x0eee) | (d & ~0x0eee); break;
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case 4: if ((a & 0x3f) >= 0x28) a = 0;
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d=(PicoMem.vsram [a & 0x003f] & 0x07ff) | (d & ~0x07ff); break;
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case 12:a=PicoMem.vram [a & 0x7fff]; if (Pico.video.addr&1) a >>= 8;
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d=(a & 0x00ff) | (d & ~0x00ff); break;
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default:elprintf(EL_ANOMALY, "VDP read with bad type %i", Pico.video.type); break;
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}
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@ -76,6 +367,8 @@ static unsigned int VideoRead(void)
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return d;
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}
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// VDP DMA
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static int GetDmaLength(void)
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{
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struct PicoVideo *pvid=&Pico.video;
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@ -95,13 +388,11 @@ static void DmaSlow(int len, unsigned int source)
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u32 mask = 0x1ffff;
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elprintf(EL_VDPDMA, "DmaSlow[%i] %06x->%04x len %i inc=%i blank %i [%u] @ %06x",
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Pico.video.type, source, a, len, inc, (Pico.video.status&8)||!(Pico.video.reg[1]&0x40),
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Pico.video.type, source, a, len, inc, (Pico.video.status&SR_VB)||!(Pico.video.reg[1]&0x40),
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SekCyclesDone(), SekPc);
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Pico.m.dma_xfers = len;
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if (Pico.m.dma_xfers < len) // lame 16bit var
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Pico.m.dma_xfers = ~0;
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SekCyclesBurnRun(CheckDMA(488 - (SekCyclesDone()-Pico.t.m68c_line_start)));
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SekCyclesBurnRun(PicoVideoFIFOWrite(len, Pico.video.type == 1, PVS_DMAPEND,
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SR_DMA | PVS_CPUWR) + 8);
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if ((source & 0xe00000) == 0xe00000) { // Ram
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base = (u16 *)PicoMem.ram;
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@ -224,14 +515,12 @@ static void DmaCopy(int len)
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int source;
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elprintf(EL_VDPDMA, "DmaCopy len %i [%u]", len, SekCyclesDone());
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Pico.m.dma_xfers = len;
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if (Pico.m.dma_xfers < len)
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Pico.m.dma_xfers = ~0;
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Pico.video.status |= SR_DMA;
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SekCyclesBurnRun(PicoVideoFIFOWrite(len, 1, PVS_CPUWR|PVS_DMAPEND, SR_DMA));
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source =Pico.video.reg[0x15];
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source|=Pico.video.reg[0x16]<<8;
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// XXX implement VRAM 128k? Is this even working?
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for (; len; len--)
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{
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vr[a] = vr[source++ & 0xffff];
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@ -255,10 +544,7 @@ static NOINLINE void DmaFill(int data)
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len = GetDmaLength();
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elprintf(EL_VDPDMA, "DmaFill len %i inc %i [%u]", len, inc, SekCyclesDone());
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Pico.m.dma_xfers = len;
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if (Pico.m.dma_xfers < len) // lame 16bit var
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Pico.m.dma_xfers = ~0;
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Pico.video.status |= SR_DMA;
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SekCyclesBurnRun(PicoVideoFIFOWrite(len, Pico.video.type == 1, PVS_CPUWR|PVS_DMAPEND, SR_DMA));
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switch (Pico.video.type)
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{
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@ -274,13 +560,24 @@ static NOINLINE void DmaFill(int data)
|
|||
Pico.est.rendstatus |= PDRAW_DIRTY_SPRITES;
|
||||
break;
|
||||
case 3: // cram
|
||||
Pico.m.dirtyPal = 1;
|
||||
for (l = len; l; l--) {
|
||||
PicoMem.cram[(a/2) & 0x3f] = data;
|
||||
|
||||
// Increment address register
|
||||
a += inc;
|
||||
}
|
||||
break;
|
||||
case 5: { // vsram
|
||||
// TODO: needs fifo; anyone using these?
|
||||
static int once;
|
||||
if (!once++)
|
||||
elprintf(EL_STATUS|EL_ANOMALY|EL_VDPDMA, "TODO: cram/vsram fill");
|
||||
for (l = len; l; l--) {
|
||||
PicoMem.vsram[(a/2) & 0x3f] = data;
|
||||
|
||||
// Increment address register
|
||||
a += inc;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case 0x81:
|
||||
case 0x81: // vram 128k
|
||||
for (l = len; l; l--) {
|
||||
VideoWrite128(a, data);
|
||||
|
||||
|
|
@ -307,17 +604,22 @@ static NOINLINE void DmaFill(int data)
|
|||
|
||||
}
|
||||
|
||||
// VDP command handling
|
||||
|
||||
static NOINLINE void CommandDma(void)
|
||||
{
|
||||
struct PicoVideo *pvid=&Pico.video;
|
||||
u32 len, method;
|
||||
u32 source;
|
||||
|
||||
if ((pvid->reg[1]&0x10)==0) return; // DMA not enabled
|
||||
|
||||
if (Pico.m.dma_xfers)
|
||||
pvid->status |= PVS_DMAPEND;
|
||||
PicoVideoFIFOSync(SekCyclesDone()-Pico.t.m68c_line_start);
|
||||
if (pvid->status & SR_DMA) {
|
||||
elprintf(EL_VDPDMA, "Dma overlap, left=%d @ %06x",
|
||||
Pico.m.dma_xfers, SekPc);
|
||||
fifo_total, SekPc);
|
||||
fifo_total = fifo_ql = 0;
|
||||
}
|
||||
pvid->status |= SR_DMA;
|
||||
|
||||
len = GetDmaLength();
|
||||
source =Pico.video.reg[0x15];
|
||||
|
|
@ -329,9 +631,10 @@ static NOINLINE void CommandDma(void)
|
|||
DmaSlow(len, source << 1); // 68000 to VDP
|
||||
else if (method == 3)
|
||||
DmaCopy(len); // VRAM Copy
|
||||
else
|
||||
else {
|
||||
pvid->status |= PVS_DMAFILL;
|
||||
return;
|
||||
|
||||
}
|
||||
source += len;
|
||||
Pico.video.reg[0x13] = Pico.video.reg[0x14] = 0;
|
||||
Pico.video.reg[0x15] = source;
|
||||
|
|
@ -357,13 +660,21 @@ static NOINLINE void CommandChange(void)
|
|||
pvid->addr_u = (u8)((cmd >> 2) & 1);
|
||||
}
|
||||
|
||||
static void DrawSync(int blank_on)
|
||||
// VDP interface
|
||||
|
||||
static void DrawSync(int skip)
|
||||
{
|
||||
int lines = Pico.video.reg[1]&0x08 ? 240 : 224;
|
||||
if (Pico.m.scanline < lines && !(PicoIn.opt & POPT_ALT_RENDERER) &&
|
||||
!PicoIn.skipFrame && Pico.est.DrawScanline <= Pico.m.scanline) {
|
||||
int last = Pico.m.scanline - (skip || blankline == Pico.m.scanline);
|
||||
|
||||
if (last < lines && !(PicoIn.opt & POPT_ALT_RENDERER) &&
|
||||
!PicoIn.skipFrame && Pico.est.DrawScanline <= last) {
|
||||
//elprintf(EL_ANOMALY, "sync");
|
||||
PicoDrawSync(Pico.m.scanline, blank_on);
|
||||
if (blankline >= 0 && blankline < last) {
|
||||
PicoDrawSync(blankline, 1);
|
||||
blankline = -1;
|
||||
}
|
||||
PicoDrawSync(last, 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -390,19 +701,19 @@ PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d)
|
|||
pvid->pending=0;
|
||||
}
|
||||
|
||||
if (!(pvid->status & SR_VB) && (pvid->reg[1]&0x40) && !(PicoIn.opt&POPT_DIS_VDP_FIFO))
|
||||
if (!(PicoIn.opt&POPT_DIS_VDP_FIFO))
|
||||
{
|
||||
int use = pvid->type == 1 ? 2 : 1;
|
||||
pvid->lwrite_cnt -= use;
|
||||
if (pvid->lwrite_cnt < 0)
|
||||
SekCyclesBurnRun(488 - (SekCyclesDone()-Pico.t.m68c_line_start));
|
||||
elprintf(EL_ASVDP, "VDP data write: [%04x] %04x [%u] {%i} #%i @ %06x",
|
||||
Pico.video.addr, d, SekCyclesDone(), Pico.video.type, pvid->lwrite_cnt, SekPc);
|
||||
fifo_data[++fifo_dx&3] = d;
|
||||
SekCyclesBurnRun(PicoVideoFIFOWrite(1, pvid->type == 1, 0, PVS_CPUWR));
|
||||
|
||||
elprintf(EL_ASVDP, "VDP data write: [%04x] %04x [%u] {%i} @ %06x",
|
||||
Pico.video.addr, d, SekCyclesDone(), Pico.video.type, SekPc);
|
||||
}
|
||||
VideoWrite(d);
|
||||
|
||||
if ((pvid->command&0x80) && (pvid->reg[1]&0x10) && (pvid->reg[0x17]>>6)==2)
|
||||
DmaFill(d);
|
||||
// start DMA fill on write. NB VSRAM and CRAM fills use wrong FIFO data.
|
||||
if ((pvid->status & (PVS_DMAPEND|PVS_DMAFILL)) == (PVS_DMAPEND|PVS_DMAFILL))
|
||||
DmaFill(fifo_data[(fifo_dx + !!(pvid->type&~0x81))&3]);
|
||||
|
||||
break;
|
||||
|
||||
|
|
@ -410,6 +721,8 @@ PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d)
|
|||
if (pvid->pending)
|
||||
{
|
||||
// Low word of command:
|
||||
if (!(pvid->reg[1]&0x10))
|
||||
d = (d&~0x80)|(pvid->command&0x80);
|
||||
pvid->command &= 0xffff0000;
|
||||
pvid->command |= d;
|
||||
pvid->pending = 0;
|
||||
|
|
@ -427,16 +740,24 @@ PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d)
|
|||
// Register write:
|
||||
int num=(d>>8)&0x1f;
|
||||
int dold=pvid->reg[num];
|
||||
int blank_on = 0;
|
||||
int skip=0;
|
||||
pvid->type=0; // register writes clear command (else no Sega logo in Golden Axe II)
|
||||
if (num > 0x0a && !(pvid->reg[1]&4)) {
|
||||
elprintf(EL_ANOMALY, "%02x written to reg %02x in SMS mode @ %06x", d, num, SekPc);
|
||||
return;
|
||||
}
|
||||
|
||||
if (num == 1 && !(d&0x40) && SekCyclesDone() - Pico.t.m68c_line_start <= 488-390)
|
||||
blank_on = 1;
|
||||
DrawSync(blank_on);
|
||||
if (num == 0 && !(pvid->reg[0]&2) && (d&2))
|
||||
hvlatch = PicoVideoRead(0x08);
|
||||
if (num == 1 && ((pvid->reg[1]^d)&0x40)) {
|
||||
PicoVideoFIFOMode(d & 0x40);
|
||||
// handle line blanking before line rendering
|
||||
if (SekCyclesDone() - Pico.t.m68c_line_start <= 488-390) {
|
||||
skip = 1;
|
||||
blankline = d&0x40 ? -1 : Pico.m.scanline;
|
||||
}
|
||||
}
|
||||
DrawSync(skip);
|
||||
pvid->reg[num]=(unsigned char)d;
|
||||
switch (num)
|
||||
{
|
||||
|
|
@ -519,15 +840,23 @@ update_irq:
|
|||
}
|
||||
}
|
||||
|
||||
static u32 SrLow(const struct PicoVideo *pv)
|
||||
static u32 VideoSr(const struct PicoVideo *pv)
|
||||
{
|
||||
unsigned int c, d = pv->status;
|
||||
unsigned int hp = pv->reg[12]&1 ? 32:40; // HBLANK start
|
||||
unsigned int hl = pv->reg[12]&1 ? 94:84; // HBLANK length
|
||||
|
||||
c = SekCyclesDone();
|
||||
if (c - Pico.t.m68c_line_start - 39 < 92)
|
||||
if (c - Pico.t.m68c_line_start - hp < hl)
|
||||
d |= SR_HB;
|
||||
if (CYCLES_GT(c, Pico.t.dma_end))
|
||||
d &= ~SR_DMA;
|
||||
|
||||
PicoVideoFIFOSync(c-Pico.t.m68c_line_start);
|
||||
if (pv->status & SR_DMA)
|
||||
d |= SR_EMPT; // unused by DMA, or rather flags not updated?
|
||||
else if (fifo_total >= 4)
|
||||
d |= SR_FULL;
|
||||
else if (!fifo_total)
|
||||
d |= SR_EMPT;
|
||||
return d;
|
||||
}
|
||||
|
||||
|
|
@ -538,8 +867,11 @@ PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a)
|
|||
if (a == 0x04) // control port
|
||||
{
|
||||
struct PicoVideo *pv = &Pico.video;
|
||||
unsigned int d = SrLow(pv);
|
||||
pv->pending = 0;
|
||||
unsigned int d = VideoSr(pv);
|
||||
if (pv->pending) {
|
||||
CommandChange();
|
||||
pv->pending = 0;
|
||||
}
|
||||
elprintf(EL_SR, "SR read: %04x [%u] @ %06x", d, SekCyclesDone(), SekPc);
|
||||
return d;
|
||||
}
|
||||
|
|
@ -564,12 +896,14 @@ PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a)
|
|||
unsigned int d;
|
||||
|
||||
d = (SekCyclesDone() - Pico.t.m68c_line_start) & 0x1ff; // FIXME
|
||||
if (Pico.video.reg[12]&1)
|
||||
d = hcounts_40[d];
|
||||
else d = hcounts_32[d];
|
||||
if (Pico.video.reg[0]&2)
|
||||
d = hvlatch;
|
||||
else if (Pico.video.reg[12]&1)
|
||||
d = hcounts_40[d] | (Pico.video.v_counter << 8);
|
||||
else d = hcounts_32[d] | (Pico.video.v_counter << 8);
|
||||
|
||||
elprintf(EL_HVCNT, "hv: %02x %02x [%u] @ %06x", d, Pico.video.v_counter, SekCyclesDone(), SekPc);
|
||||
return d | (Pico.video.v_counter << 8);
|
||||
return d;
|
||||
}
|
||||
|
||||
if (a==0x00) // data port
|
||||
|
|
@ -592,16 +926,22 @@ unsigned char PicoVideoRead8DataL(void)
|
|||
|
||||
unsigned char PicoVideoRead8CtlH(void)
|
||||
{
|
||||
u8 d = (u8)(Pico.video.status >> 8);
|
||||
Pico.video.pending = 0;
|
||||
u8 d = VideoSr(&Pico.video) >> 8;
|
||||
if (Pico.video.pending) {
|
||||
CommandChange();
|
||||
Pico.video.pending = 0;
|
||||
}
|
||||
elprintf(EL_SR, "SR read (h): %02x @ %06x", d, SekPc);
|
||||
return d;
|
||||
}
|
||||
|
||||
unsigned char PicoVideoRead8CtlL(void)
|
||||
{
|
||||
u8 d = SrLow(&Pico.video);
|
||||
Pico.video.pending = 0;
|
||||
u8 d = VideoSr(&Pico.video);
|
||||
if (Pico.video.pending) {
|
||||
CommandChange();
|
||||
Pico.video.pending = 0;
|
||||
}
|
||||
elprintf(EL_SR, "SR read (l): %02x @ %06x", d, SekPc);
|
||||
return d;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue