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https://github.com/RaySollium99/picodrive.git
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VDP DMA/CPU access timing improvements
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kub
parent
5e04c2f37f
commit
1886ac5f30
4 changed files with 126 additions and 193 deletions
141
pico/videoport.c
141
pico/videoport.c
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@ -2,7 +2,7 @@
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* PicoDrive
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* (c) Copyright Dave, 2004
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* (C) notaz, 2006-2009
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* (C) kub, 2020
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* (C) kub, 2020,2021
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*
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* This work is licensed under the terms of MAME license.
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* See COPYING file in the top-level directory.
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@ -12,11 +12,118 @@
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#define NEED_DMA_SOURCE
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#include "memory.h"
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extern const unsigned char hcounts_32[], hcounts_40[];
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extern const unsigned char vdpcyc2sl_32_bl[], vdpcyc2sl_40_bl[];
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extern const unsigned char vdpcyc2sl_32[], vdpcyc2sl_40[];
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extern const unsigned short vdpsl2cyc_32_bl[], vdpsl2cyc_40_bl[];
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extern const unsigned short vdpsl2cyc_32[], vdpsl2cyc_40[];
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enum { clkdiv = 2 }; // CPU clock granularity: one of 1,2,4,8
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// VDP Slot timing, taken from http://gendev.spritesmind.net/
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// forum/viewtopic.php?f=22&t=851&sid=d5701a71396ee7f700c74fb7cd85cb09
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// Thank you very much for the great work, Nemesis!
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// 1 slot is 488/171 = 2.8538 68k cycles in h32, and 488/210 = 2.3238 in h40.
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// VDP has a slot counter running from 0x00 to 0xff every scanline, but it has
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// a gap depending on the video mode. The slot in which a horizontal interrupt
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// is generated also depends on the video mode.
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enum { hint32 = 0x84, gapstart32 = 0x94, gapend32 = 0xe9 };
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enum { hint40 = 0xa4, gapstart40 = 0xb7, gapend40 = 0xe5 };
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// number of slots in a scanline
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#define slots32 (0x100-(gapend32-gapstart32)) // 171
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#define slots40 (0x100-(gapend40-gapstart40)) // 210
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// In blanked display, all slots but the refresh slots are usable for transfers,
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// in active display only 16(h32) / 18(h40) slots can be used.
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// dma and refresh slots for active display, 16 for H32
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static u8 dmaslots32[] =
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{ 145,243, 2,10,18, 34,42,50, 66,74,82, 98,106,114, 129,130 };
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static u8 refslots32[] =
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{ 250, 26, 58, 90, 122 };
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// dma and refresh slots for active display, 18 for H40
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static u8 dmaslots40[] =
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{ 232, 2,10,18, 34,42,50, 66,74,82, 98,106,114, 130,138,146, 161,162 };
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static u8 refslots40[] =
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{ 250, 26, 58, 90, 122, 154 };
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// table sizes
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enum { cycsz = 488/clkdiv };
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enum { sl32blsz=slots32-sizeof(refslots32)+1, sl32acsz=sizeof(dmaslots32)+1 };
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enum { sl40blsz=slots40-sizeof(refslots40)+1, sl40acsz=sizeof(dmaslots40)+1 };
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// Tables must be considerably larger than one scanline, since 68k emulation
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// isn't stopping in the middle of an operation. If the last op is a 32 bit
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// VDP write 2 slots may need to be taken from the next scanline, which can be
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// more than 100 CPU cycles. For safety just cover 2 scanlines.
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// table for mapping hvcounter reads
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static u8 hcounts_32[2*cycsz], hcounts_40[2*cycsz];
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// tables mapping cycles to slots
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static u16 vdpcyc2sl_32_bl[2*cycsz],vdpcyc2sl_40_bl[2*cycsz];
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static u16 vdpcyc2sl_32_ac[2*cycsz],vdpcyc2sl_40_ac[2*cycsz];
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// tables mapping slots to cycles
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// NB the sl2cyc tables must cover all slots present in the cyc2sl tables.
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static u16 vdpsl2cyc_32_bl[2*sl32blsz],vdpsl2cyc_40_bl[2*sl40blsz];
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static u16 vdpsl2cyc_32_ac[2*sl32acsz],vdpsl2cyc_40_ac[2*sl40acsz];
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// calculate timing tables for one mode (H32 or H40)
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// NB tables aligned to HINT, since the main loop uses HINT as synchronization
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#define INITTABLES(s) { \
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float factor = 488./slots##s; \
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int ax, bx, rx, ac, bc; \
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int i, n; \
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\
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/* calculate internal VDP slot numbers */ \
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for (i = 0; i < cycsz; i++) { \
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n = hint##s + i*clkdiv/factor; \
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if (n >= gapstart##s) n += gapend##s-gapstart##s; \
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hcounts_##s[i] = n % 256; \
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} \
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memcpy(hcounts_##s+cycsz, hcounts_##s, ARRAY_SIZE(hcounts_##s)-cycsz);\
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\
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ax = bx = ac = bc = rx = 0; \
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for (i = 0; i < cycsz; i++) { \
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n = hcounts_##s[i]; \
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if (i == 0 || n != hcounts_##s[i-1]) { \
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/* fill slt <=> cycle tables, active scanline */ \
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if (ax < ARRAY_SIZE(dmaslots##s) && dmaslots##s[ax] == n) { \
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vdpsl2cyc_##s##_ac[++ax]=i; \
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while (ac < i) vdpcyc2sl_##s##_ac[ac++] = ax-1; \
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} \
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/* fill slt <=> cycle tables, scanline off */ \
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if (rx >= ARRAY_SIZE(refslots##s) || refslots##s[rx] != n) { \
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vdpsl2cyc_##s##_bl[++bx]=i; \
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while (bc < i) vdpcyc2sl_##s##_bl[bc++] = bx-1; \
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} else \
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++rx; \
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} \
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} \
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/* fill up cycle to slot mappings for last slot */ \
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while (ac < cycsz) \
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vdpcyc2sl_##s##_ac[ac] = ARRAY_SIZE(dmaslots##s), ac++; \
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while (bc < cycsz) \
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vdpcyc2sl_##s##_bl[bc] = slots##s-ARRAY_SIZE(refslots##s), bc++; \
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/* extend tables for 2nd scanline */ \
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i = ARRAY_SIZE(dmaslots##s); \
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while (ac < ARRAY_SIZE(vdpcyc2sl_##s##_ac)) \
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vdpcyc2sl_##s##_ac[ac] = vdpcyc2sl_##s##_ac[ac-cycsz]+i, ac++; \
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while (ax < ARRAY_SIZE(vdpsl2cyc_##s##_ac)-1) ax++, \
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vdpsl2cyc_##s##_ac[ax] = vdpsl2cyc_##s##_ac[ax-i]+cycsz;\
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i = slots##s - ARRAY_SIZE(refslots##s); \
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while (bc < ARRAY_SIZE(vdpcyc2sl_##s##_bl)) \
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vdpcyc2sl_##s##_bl[bc] = vdpcyc2sl_##s##_bl[bc-cycsz]+i, bc++; \
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while (bx < ARRAY_SIZE(vdpsl2cyc_##s##_bl)-1) bx++, \
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vdpsl2cyc_##s##_bl[bx] = vdpsl2cyc_##s##_bl[bx-i]+cycsz; \
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}
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// initialize VDP timing tables
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void PicoVideoInit(void)
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{
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INITTABLES(32);
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INITTABLES(40);
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}
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static int blankline; // display disabled for this line
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@ -69,16 +176,17 @@ static struct VdpFIFO { // XXX this must go into save file!
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unsigned short fifo_slot; // last executed slot in current scanline
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unsigned short fifo_maxslot;// #slots in scanline
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const unsigned char *fifo_cyc2sl;
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const unsigned short *fifo_cyc2sl;
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const unsigned short *fifo_sl2cyc;
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} VdpFIFO;
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enum { FQ_BYTE = 1, FQ_BGDMA = 2, FQ_FGDMA = 4 }; // queue flags, NB: BYTE = 1!
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// NB must limit cyc2sl to table size in case 68k overdraws its aim. That can
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// happen if the last insn is a blocking acess to VDP, or for exceptions (e.g.irq)
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#define Cyc2Sl(vf,lc) ((lc) < 256*2 ? vf->fifo_cyc2sl[(lc)>>1] : vf->fifo_cyc2sl[255])
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#define Sl2Cyc(vf,sl) (vf->fifo_sl2cyc[sl]*2)
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// NB should limit cyc2sl to table size in case 68k overdraws its aim. That can
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// happen if the last op is a blocking acess to VDP, or for exceptions (e.g.irq)
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#define Cyc2Sl(vf,lc) (vf->fifo_cyc2sl[(lc)/clkdiv])
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#define Sl2Cyc(vf,sl) (vf->fifo_sl2cyc[sl]*clkdiv)
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// do the FIFO math
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static __inline int AdvanceFIFOEntry(struct VdpFIFO *vf, struct PicoVideo *pv, int slots)
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@ -263,7 +371,7 @@ int PicoVideoFIFOWrite(int count, int flags, unsigned sr_mask,unsigned sr_flags)
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// update FIFO state if it was empty
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if (!(pv->status & PVS_FIFORUN)) {
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vf->fifo_slot = Cyc2Sl(vf, lc+9); // FIFO latency ~3 vdp slots
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vf->fifo_slot = Cyc2Sl(vf, lc+5); // FIFO latency ~3 vdp slots
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pv->status |= PVS_FIFORUN;
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pv->fifo_cnt = count << (flags & FQ_BYTE);
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}
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@ -300,10 +408,10 @@ int PicoVideoFIFOHint(void)
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// switch FIFO mode between active/inactive display
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void PicoVideoFIFOMode(int active, int h40)
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{
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static const unsigned char *vdpcyc2sl[2][2] =
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{ {vdpcyc2sl_32_bl, vdpcyc2sl_40_bl} , {vdpcyc2sl_32, vdpcyc2sl_40} };
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static const unsigned short *vdpcyc2sl[2][2] =
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{ {vdpcyc2sl_32_bl, vdpcyc2sl_40_bl},{vdpcyc2sl_32_ac, vdpcyc2sl_40_ac} };
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static const unsigned short *vdpsl2cyc[2][2] =
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{ {vdpsl2cyc_32_bl, vdpsl2cyc_40_bl} , {vdpsl2cyc_32, vdpsl2cyc_40} };
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{ {vdpsl2cyc_32_bl, vdpsl2cyc_40_bl},{vdpsl2cyc_32_ac, vdpsl2cyc_40_ac} };
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struct VdpFIFO *vf = &VdpFIFO;
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struct PicoVideo *pv = &Pico.video;
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@ -316,11 +424,10 @@ void PicoVideoFIFOMode(int active, int h40)
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vf->fifo_cyc2sl = vdpcyc2sl[active][h40];
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vf->fifo_sl2cyc = vdpsl2cyc[active][h40];
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// recalculate FIFO slot for new mode
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vf->fifo_slot = Cyc2Sl(vf, lc)-1;
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vf->fifo_slot = Cyc2Sl(vf, lc);
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vf->fifo_maxslot = Cyc2Sl(vf, 488);
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}
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// VDP memory rd/wr
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static __inline void AutoIncrement(void)
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