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https://github.com/RaySollium99/picodrive.git
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32X: memory access and polling bug fixes
This commit is contained in:
kub
parent
ee46642395
commit
1891e649e5
3 changed files with 33 additions and 23 deletions
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@ -74,7 +74,7 @@ static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
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if (match && cycles - m68k_poll.cycles <= 64 && !SekNotPolling)
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{
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// detect split 32bit access by same cycle count, and ignore those
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if (cycles != m68k_poll.cycles && ++m68k_poll.cnt > POLL_THRESHOLD) {
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if (cycles != m68k_poll.cycles && ++m68k_poll.cnt >= POLL_THRESHOLD) {
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if (!(Pico32x.emu_flags & flags)) {
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elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
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a, cycles - m68k_poll.cycles);
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@ -118,7 +118,7 @@ static void NOINLINE sh2_poll_detect(u32 a, SH2 *sh2, u32 flags, int maxcnt)
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// by checking address (max 2 bytes away) and cycles (max 2 cycles later).
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// no polling if more than 20 cycles have passed since last detect call.
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if (a - sh2->poll_addr <= 2 && CYCLES_GE(sh2->poll_cycles+20, cycles_done)) {
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if (CYCLES_GT(cycles_done,sh2->poll_cycles+2) && ++sh2->poll_cnt > maxcnt) {
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if (CYCLES_GT(cycles_done,sh2->poll_cycles+2) && ++sh2->poll_cnt >= maxcnt) {
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if (!(sh2->state & flags))
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elprintf_sh2(sh2, EL_32X, "state: %02x->%02x",
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sh2->state, sh2->state | flags);
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@ -131,6 +131,8 @@ static void NOINLINE sh2_poll_detect(u32 a, SH2 *sh2, u32 flags, int maxcnt)
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if ((a & 0xc6000000) == 0x06000000) {
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unsigned char *p = sh2->p_drcblk_ram;
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p[(a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT] |= 0x80;
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// mark next word too to enable poll fifo for 32bit access
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p[((a+2) & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT] |= 0x80;
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}
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#endif
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}
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@ -148,7 +150,7 @@ void NOINLINE p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
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elprintf_sh2(sh2, EL_32X, "state: %02x->%02x", sh2->state,
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sh2->state & ~flags);
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if (sh2->m68krcycles_done < m68k_cycles)
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if (sh2->m68krcycles_done < m68k_cycles && !(sh2->state & SH2_STATE_RUN))
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sh2->m68krcycles_done = m68k_cycles;
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pevt_log_sh2_o(sh2, EVT_POLL_END);
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@ -174,12 +176,12 @@ static void sh2s_sync_on_read(SH2 *sh2)
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// This is used to correctly deliver syncronisation data to the 3 cpus. The
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// fifo stores 16 bit values, 8/32 bit accesses must be adapted accordingly.
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#define PFIFO_SZ 4
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#define PFIFO_CNT 4
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#define PFIFO_CNT 8
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struct sh2_poll_fifo {
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u32 cycles;
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u32 a;
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u16 d;
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u16 cpu;
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int cpu;
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} sh2_poll_fifo[PFIFO_CNT][PFIFO_SZ];
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unsigned sh2_poll_rd[PFIFO_CNT], sh2_poll_wr[PFIFO_CNT]; // ringbuffer pointers
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@ -191,6 +193,7 @@ static NOINLINE u32 sh2_poll_read(u32 a, u32 d, unsigned int cycles, SH2* sh2)
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int cpu = sh2 ? sh2->is_slave+1 : 0;
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unsigned idx;
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a &= ~0x20000000; // ignore writethrough bit
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// fetch oldest write to address from fifo, but stop when reaching the present
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idx = sh2_poll_rd[hix];
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while (idx != sh2_poll_wr[hix] && CYCLES_GE(cycles, fifo[idx].cycles)) {
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@ -225,6 +228,7 @@ static NOINLINE void sh2_poll_write(u32 a, u32 d, unsigned int cycles, SH2 *sh2)
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struct sh2_poll_fifo *q = &fifo[(sh2_poll_wr[hix]-1) % PFIFO_SZ];
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int cpu = sh2 ? sh2->is_slave+1 : 0;
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a &= ~0x20000000; // ignore writethrough bit
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// fold 2 consecutive writes to the same address to avoid reading of
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// intermediate values that may cause synchronisation problems.
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// NB this can take an eternity on m68k: mov.b <addr1.l>,<addr2.l> needs
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@ -279,8 +283,8 @@ u32 REGPARM(3) p32x_sh2_poll_memory32(unsigned int a, u32 d, SH2 *sh2)
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sh2s_sync_on_read(sh2);
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cycles = sh2_cycles_done_m68k(sh2);
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// check poll fifo and sign-extend the result correctly
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d = sh2_poll_read(a, d, cycles, sh2) |
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(sh2_poll_read(a+2, d >> 16, cycles, sh2) << 16);
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d = (sh2_poll_read(a, d >> 16, cycles, sh2) << 16) |
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((u16)sh2_poll_read(a+2, d, cycles, sh2));
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}
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sh2_poll_detect(a, sh2, SH2_STATE_RPOLL, 5);
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@ -1503,7 +1507,7 @@ static u32 REGPARM(2) sh2_read32_rom(u32 a, SH2 *sh2)
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// writes
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#ifdef DRC_SH2
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static void NOINLINE sh2_sdram_poll(u32 a, u16 d, SH2 *sh2)
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static void NOINLINE sh2_sdram_poll(u32 a, u32 d, SH2 *sh2)
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{
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unsigned cycles;
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@ -1525,8 +1529,8 @@ void NOINLINE sh2_sdram_checks(u32 a, u32 d, SH2 *sh2, int t)
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void NOINLINE sh2_sdram_checks_l(u32 a, u32 d, SH2 *sh2, int t)
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{
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sh2_sdram_checks(a, d, sh2, t);
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sh2_sdram_checks(a+2, d>>16, sh2, t>>16);
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sh2_sdram_checks(a, d>>16, sh2, t);
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sh2_sdram_checks(a+2, d, sh2, t>>16);
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}
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#ifndef _ASM_32X_MEMORY_C
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@ -1568,6 +1572,7 @@ static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
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}
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if ((a & 0x3fe00) == 0x4200) {
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sh2->poll_cnt = 0;
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((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
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Pico32x.dirty_pal = 1;
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goto out;
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@ -1641,6 +1646,7 @@ static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2)
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}
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if ((a & 0x3fe00) == 0x4200) {
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sh2->poll_cnt = 0;
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Pico32xMem->pal[(a & 0x1ff) / 2] = d;
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Pico32x.dirty_pal = 1;
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goto out;
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@ -2175,11 +2181,7 @@ void Pico32xSwapDRAM(int b)
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ssh2_read32_map[0x04/2].addr = ssh2_read32_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
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// convenience ptrs
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msh2.p_sdram = ssh2.p_sdram = Pico32xMem->sdram;
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msh2.p_dram = ssh2.p_dram = Pico32xMem->dram[b];
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msh2.p_rom = ssh2.p_rom = Pico.rom;
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msh2.p_bios = Pico32xMem->sh2_rom_m.w; msh2.p_da = msh2.data_array;
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ssh2.p_bios = Pico32xMem->sh2_rom_s.w; ssh2.p_da = ssh2.data_array;
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}
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static void bank_switch_rom_sh2(void)
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@ -2359,6 +2361,12 @@ void PicoMemSetup32x(void)
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ssh2.write16_tab = (const void **)(void *)ssh2_write16_map;
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ssh2.write32_tab = (const void **)(void *)ssh2_write32_map;
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// convenience ptrs
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msh2.p_sdram = ssh2.p_sdram = Pico32xMem->sdram;
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msh2.p_rom = ssh2.p_rom = Pico.rom;
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msh2.p_bios = Pico32xMem->sh2_rom_m.w; msh2.p_da = msh2.data_array;
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ssh2.p_bios = Pico32xMem->sh2_rom_s.w; ssh2.p_da = ssh2.data_array;
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sh2_drc_mem_setup(&msh2);
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sh2_drc_mem_setup(&ssh2);
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@ -18,7 +18,7 @@
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.text
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@ u32 a
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@ u32 a, SH2 *sh2
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.global sh2_read8_rom
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.global sh2_read8_sdram
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.global sh2_read8_da
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@ -32,7 +32,7 @@
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.global sh2_read32_da
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.global sh2_read32_dram
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@ u32 a, u32 d
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@ u32 a, u32 d, SH2 *sh2
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.global sh2_write8_sdram
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.global sh2_write8_da
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.global sh2_write8_dram
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@ -270,16 +270,14 @@ sh2_write32_dram:
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streq r1, [ip, r3, lsr #SH2_DRAM_SHIFT]
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bxeq lr
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ldr r0, [ip, r3, lsr #SH2_DRAM_SHIFT]
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mov r2, #0
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tst r1, #0x00ff0000
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orrne r2, r2, #0x00ff0000
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bicne r0, r0, #0x00ff0000
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tst r1, #0xff000000
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orrne r2, r2, #0xff000000
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bicne r0, r0, #0xff000000
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tst r1, #0x000000ff
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orrne r2, r2, #0x000000ff
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bicne r0, r0, #0x000000ff
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tst r1, #0x0000ff00
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orrne r2, r2, #0x0000ff00
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bic r0, r0, r2
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bicne r0, r0, #0x0000ff00
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orr r0, r0, r1
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str r0, [ip, r3, lsr #SH2_DRAM_SHIFT]
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bx lr
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@ -137,6 +137,11 @@ static void dmac_memcpy(struct dma_chan *chan, SH2 *sh2)
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if (!up || chan->tcr < 4)
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return;
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// XXX Mars Check Program fills a 64K buffer, then copies 32K longwords from
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// DRAM to SDRAM in 4-longword mode, which is 128K. This overwrites a comm
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// area in SDRAM, which is why the check fails.
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// Is this a buswidth mismatch problem? As a kludge, usw 16-bit width xfers
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if (size == 3 && (chan->sar & 0xdf000000) == 0x04000000) size = 1;
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if (size == 3) size = 2; // 4-word xfer mode still counts in words
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// XXX check TCR being a multiple of 4 in 4-word xfer mode?
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// XXX check alignment of sar/dar, generating a bus error if unaligned?
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@ -500,7 +505,6 @@ static void dreq1_do(SH2 *sh2, struct dma_chan *chan)
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if ((chan->dar & ~0xf) != 0x20004030)
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elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar);
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sh2->state |= SH2_STATE_SLEEP;
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dmac_transfer_one(sh2, chan);
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if (chan->tcr == 0)
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dmac_transfer_complete(sh2, chan);
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