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32x: drc: self-reentrant blocks

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git-svn-id: file:///home/notaz/opt/svn/PicoDrive@841 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz 2009-12-15 13:44:59 +00:00
parent 8beb44303e
commit 18b9412743
3 changed files with 453 additions and 179 deletions
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27
cpu/drc/emit_arm.c
View file

@ -264,12 +264,12 @@ static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int
emith_op_imm2(cond, s, op, r, r, imm)
// test op
#define emith_top_imm(cond, op, r, imm) { \
#define emith_top_imm(cond, op, r, imm) do { \
u32 ror2, v; \
for (ror2 = 0, v = imm; v && !(v & 3); v >>= 2) \
ror2--; \
EOP_C_DOP_IMM(cond, op, 1, r, 0, ror2 & 0x0f, v & 0xff); \
}
} while (0)
#define is_offset_24(val) \
((val) >= (int)0xff000000 && (val) <= 0x00ffffff)
@ -595,6 +595,15 @@ static int emith_xbranch(int cond, void *target, int is_call)
#define emith_jump(target) \
emith_jump_cond(A_COND_AL, target)
#define emith_jump_patchable(cond) \
emith_jump_cond(cond, 0)
#define emith_jump_patch(ptr, target) do { \
u32 *ptr_ = ptr; \
u32 val = (u32 *)(target) - (u32 *)ptr_ - 2; \
*ptr_ = (*ptr_ & 0xff000000) | (val & 0x00ffffff); \
} while (0)
#define emith_jump_reg(r) \
EOP_BX(r)
@ -605,11 +614,6 @@ static int emith_xbranch(int cond, void *target, int is_call)
#define emith_sh2_drc_exit() \
EOP_LDMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R15M)
#define emith_sh2_test_t() { \
int r = rcache_get_reg(SHR_SR, RC_GR_READ); \
EOP_TST_IMM(r, 0, 1); \
}
#define emith_sh2_dtbf_loop() { \
int cr, rn; \
int tmp_ = rcache_get_tmp(); \
@ -631,11 +635,10 @@ static int emith_xbranch(int cond, void *target, int is_call)
rcache_free_tmp(tmp_); \
}
#define emith_write_sr(srcr) { \
int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
emith_lsr(srr, srr, 12); \
emith_or_r_r_r_lsl(srr, srr, srcr, 20); \
emith_ror(srr, srr, 20); \
#define emith_write_sr(sr, srcr) { \
emith_lsr(sr, sr, 10); \
emith_or_r_r_r_lsl(sr, sr, srcr, 22); \
emith_ror(sr, sr, 22); \
}
#define emith_carry_to_t(srr, is_sub) { \

118
cpu/drc/emit_x86.c
View file

@ -11,37 +11,38 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
#define CONTEXT_REG xBP
#define IOP_JMP 0xeb
#define IOP_JO 0x70
#define IOP_JNO 0x71
#define IOP_JB 0x72
#define IOP_JAE 0x73
#define IOP_JE 0x74
#define IOP_JNE 0x75
#define IOP_JBE 0x76
#define IOP_JA 0x77
#define IOP_JS 0x78
#define IOP_JNS 0x79
#define IOP_JL 0x7c
#define IOP_JGE 0x7d
#define IOP_JLE 0x7e
#define IOP_JG 0x7f
#define ICOND_JO 0x00
#define ICOND_JNO 0x01
#define ICOND_JB 0x02
#define ICOND_JAE 0x03
#define ICOND_JE 0x04
#define ICOND_JNE 0x05
#define ICOND_JBE 0x06
#define ICOND_JA 0x07
#define ICOND_JS 0x08
#define ICOND_JNS 0x09
#define ICOND_JL 0x0c
#define ICOND_JGE 0x0d
#define ICOND_JLE 0x0e
#define ICOND_JG 0x0f
#define IOP_JMP 0xeb
// unified conditions (we just use rel8 jump instructions for x86)
#define DCOND_EQ IOP_JE
#define DCOND_NE IOP_JNE
#define DCOND_MI IOP_JS // MInus
#define DCOND_PL IOP_JNS // PLus or zero
#define DCOND_HI IOP_JA // higher (unsigned)
#define DCOND_HS IOP_JAE // higher || same (unsigned)
#define DCOND_LO IOP_JB // lower (unsigned)
#define DCOND_LS IOP_JBE // lower || same (unsigned)
#define DCOND_GE IOP_JGE // greater || equal (signed)
#define DCOND_GT IOP_JG // greater (signed)
#define DCOND_LE IOP_JLE // less || equal (signed)
#define DCOND_LT IOP_JL // less (signed)
#define DCOND_VS IOP_JO // oVerflow Set
#define DCOND_VC IOP_JNO // oVerflow Clear
#define DCOND_EQ ICOND_JE
#define DCOND_NE ICOND_JNE
#define DCOND_MI ICOND_JS // MInus
#define DCOND_PL ICOND_JNS // PLus or zero
#define DCOND_HI ICOND_JA // higher (unsigned)
#define DCOND_HS ICOND_JAE // higher || same (unsigned)
#define DCOND_LO ICOND_JB // lower (unsigned)
#define DCOND_LS ICOND_JBE // lower || same (unsigned)
#define DCOND_GE ICOND_JGE // greater || equal (signed)
#define DCOND_GT ICOND_JG // greater (signed)
#define DCOND_LE ICOND_JLE // less || equal (signed)
#define DCOND_LT ICOND_JL // less (signed)
#define DCOND_VS ICOND_JO // oVerflow Set
#define DCOND_VC ICOND_JNO // oVerflow Clear
#define EMIT_PTR(ptr, val, type) \
*(type *)(ptr) = val
@ -72,7 +73,11 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
tcache_ptr += 2
#define JMP8_EMIT(op, ptr) \
EMIT_PTR(ptr, op, u8); \
EMIT_PTR(ptr, 0x70|(op), u8); \
EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
#define JMP8_EMIT_NC(ptr) \
EMIT_PTR(ptr, IOP_JMP, u8); \
EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
// _r_r
@ -170,10 +175,10 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
#define emith_move_r_imm_s8(r, imm) \
emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))
#define emith_arith_r_imm(op, r, imm) { \
#define emith_arith_r_imm(op, r, imm) do { \
EMIT_OP_MODRM(0x81, 3, op, r); \
EMIT(imm, u32); \
}
} while (0)
// 2 - adc, 3 - sbb
#define emith_add_r_imm(r, imm) \
@ -194,10 +199,10 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
#define emith_cmp_r_imm(r, imm) \
emith_arith_r_imm(7, r, imm)
#define emith_tst_r_imm(r, imm) { \
#define emith_tst_r_imm(r, imm) do { \
EMIT_OP_MODRM(0xf7, 3, 0, r); \
EMIT(imm, u32); \
}
} while (0)
// fake
#define emith_bic_r_imm(r, imm) \
@ -238,7 +243,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
#define emith_and_r_r_imm(d, s, imm) { \
if (d != s) \
emith_move_r_r(d, s); \
emith_and_r_imm(d, imm) \
emith_and_r_imm(d, imm); \
}
// shift
@ -395,13 +400,28 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
} while (0)
#define emith_jump(ptr) { \
u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
EMIT_OP(0xe9); \
EMIT(disp, u32); \
}
#define emith_jump_cond(cond, ptr) { \
u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 6); \
EMIT(0x0f, u8); \
EMIT_OP(0x80 | (cond)); \
EMIT(disp, u32); \
}
#define emith_jump_patchable(cond) \
emith_jump_cond(cond, 0)
#define emith_jump_patch(ptr, target) do { \
u32 disp = (u32)(target) - ((u32)(ptr) + 6); \
EMIT_PTR((u8 *)(ptr) + 2, disp, u32); \
} while (0)
#define emith_call(ptr) { \
u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
EMIT_OP(0xe8); \
EMIT(disp, u32); \
}
@ -459,13 +479,6 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
EMIT_OP(0xc3); /* ret */\
}
#define emith_sh2_test_t() { \
int t = rcache_get_reg(SHR_SR, RC_GR_READ); \
EMIT(0x66, u8); \
EMIT_OP_MODRM(0xf7, 3, 0, t); \
EMIT(0x01, u16); /* test <reg>, word 1 */ \
}
#define emith_sh2_dtbf_loop() { \
u8 *jmp0; /* negative cycles check */ \
u8 *jmp1; /* unsinged overflow check */ \
@ -479,7 +492,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
emith_asr(tmp_, cr, 2+12); \
JMP8_POS(jmp0); /* no negative cycles */ \
emith_move_r_imm(tmp_, 0); \
JMP8_EMIT(IOP_JNS, jmp0); \
JMP8_EMIT(ICOND_JNS, jmp0); \
emith_and_r_imm(cr, 0xffe); \
emith_subf_r_r(rn, tmp_); \
JMP8_POS(jmp1); /* no overflow */ \
@ -488,16 +501,15 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
emith_or_r_r(cr, rn); \
emith_or_r_imm(cr, 1); \
emith_move_r_imm(rn, 0); \
JMP8_EMIT(IOP_JA, jmp1); \
JMP8_EMIT(ICOND_JA, jmp1); \
rcache_free_tmp(tmp_); \
}
#define emith_write_sr(srcr) { \
#define emith_write_sr(sr, srcr) { \
int tmp_ = rcache_get_tmp(); \
int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
emith_clear_msb(tmp_, srcr, 20); \
emith_bic_r_imm(srr, 0xfff); \
emith_or_r_r(srr, tmp_); \
emith_clear_msb(tmp_, srcr, 22); \
emith_bic_r_imm(sr, 0x3ff); \
emith_or_r_r(sr, tmp_); \
rcache_free_tmp(tmp_); \
}
@ -522,9 +534,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
JMP8_POS(jmp0); /* je do_sub */ \
emith_add_r_r(rn, rm); \
JMP8_POS(jmp1); /* jmp done */ \
JMP8_EMIT(IOP_JE, jmp0); /* do_sub: */ \
JMP8_EMIT(ICOND_JE, jmp0); /* do_sub: */ \
emith_sub_r_r(rn, rm); \
JMP8_EMIT(IOP_JMP, jmp1);/* done: */ \
JMP8_EMIT_NC(jmp1); /* done: */ \
emith_setc(tmp_); \
EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
rcache_free_tmp(tmp_); \

487
cpu/sh2/compiler.c
View file

@ -128,15 +128,16 @@ static temp_reg_t reg_temp[] = {
#define I 0x000000f0
#define Q 0x00000100
#define M 0x00000200
#define T_save 0x00000800
#define Q_SHIFT 8
#define M_SHIFT 9
typedef struct block_desc_ {
u32 addr; // SH2 PC address
u32 end_addr; // TODO rm?
void *tcache_ptr; // translated block for above PC
struct block_desc_ *next; // next block with the same PC hash
u32 addr; // SH2 PC address
u32 end_addr; // TODO rm?
void *tcache_ptr; // translated block for above PC
struct block_desc_ *next; // next block with the same PC hash
#if (DRC_DEBUG & 1)
int refcount;
#endif
@ -155,6 +156,9 @@ static int block_counts[3];
#define HASH_MASK (MAX_HASH_ENTRIES - 1)
static void **hash_table;
#define HASH_FUNC(hash_tab, addr) \
((block_desc **)(hash_tab))[(addr) & HASH_MASK]
static void REGPARM(2) (*sh2_drc_entry)(const void *block, SH2 *sh2);
static void (*sh2_drc_exit)(void);
@ -208,11 +212,29 @@ static block_desc *dr_add_block(u32 addr, int tcache_id, int *blk_id)
*blk_id = *bcount;
(*bcount)++;
if ((addr & 0xc6000000) == 0x02000000) { // ROM
bd->next = HASH_FUNC(hash_table, addr);
HASH_FUNC(hash_table, addr) = bd;
#if (DRC_DEBUG & 1)
if (bd->next != NULL) {
printf(" hash collision with %08x\n", bd->next->addr);
hash_collisions++;
}
#endif
}
return bd;
}
#define HASH_FUNC(hash_tab, addr) \
((block_desc **)(hash_tab))[(addr) & HASH_MASK]
int find_in_array(u32 *array, size_t size, u32 what)
{
size_t i;
for (i = 0; i < size; i++)
if (what == array[i])
return i;
return -1;
}
// ---------------------------------------------------------------
@ -595,7 +617,16 @@ static void sh2_generate_utils(void)
}
#define DELAYED_OP \
delayed_op = 2
drcf.delayed_op = 2
#define DELAY_SAVE_T(sr) { \
emith_bic_r_imm(sr, T_save); \
emith_tst_r_imm(sr, T); \
EMITH_SJMP_START(DCOND_EQ); \
emith_or_r_imm_c(DCOND_NE, sr, T_save); \
EMITH_SJMP_END(DCOND_EQ); \
drcf.use_saved_t = 1; \
}
#define CHECK_UNHANDLED_BITS(mask) { \
if ((op & (mask)) != 0) \
@ -614,58 +645,163 @@ static void sh2_generate_utils(void)
if (GET_Fx() >= n) \
goto default_
static void *sh2_translate(SH2 *sh2, block_desc *other_block)
#define MAX_LOCAL_BRANCHES 16
// op_flags: data from 1st pass
#define OP_FLAGS(pc) op_flags[((pc) - base_pc) / 2]
#define OF_DELAY_OP (1 << 0)
static void *sh2_translate(SH2 *sh2, int tcache_id)
{
// XXX: maybe use structs instead?
void *branch_target_ptr[MAX_LOCAL_BRANCHES];
u32 branch_target_pc[MAX_LOCAL_BRANCHES];
int branch_target_count = 0;
void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
int branch_patch_count = 0;
int branch_patch_cond = -1;
u8 op_flags[BLOCK_CYCLE_LIMIT + 1];
struct {
u32 delayed_op:2;
u32 test_irq:1;
u32 use_saved_t:1; // delayed op modifies T
} drcf = { 0, };
void *block_entry;
block_desc *this_block;
unsigned int pc = sh2->pc;
int op, delayed_op = 0, test_irq = 0;
int tcache_id = 0, blkid = 0;
int cycles = 0;
u32 tmp, tmp2, tmp3, tmp4, sr;
u32 pc, base_pc, end_pc; // PC of current, first, last insn
int blkid_main = 0;
u32 tmp, tmp2;
int cycles;
int op;
int i;
base_pc = sh2->pc;
// validate PC
tmp = sh2->pc >> 29;
if ((tmp != 0 && tmp != 1 && tmp != 6) || sh2->pc == 0) {
printf("invalid PC, aborting: %08x\n", sh2->pc);
tmp = base_pc >> 29;
if ((tmp != 0 && tmp != 1 && tmp != 6) || base_pc == 0) {
printf("invalid PC, aborting: %08x\n", base_pc);
// FIXME: be less destructive
exit(1);
}
if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
// data_array, BIOS have separate tcache (shared)
tcache_id = 1 + sh2->is_slave;
}
tcache_ptr = tcache_ptrs[tcache_id];
this_block = dr_add_block(pc, tcache_id, &blkid);
this_block = dr_add_block(base_pc, tcache_id, &blkid_main);
// predict tcache overflow
tmp = tcache_ptr - tcache_bases[tcache_id];
if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE || this_block == NULL) {
flush_tcache(tcache_id);
tcache_ptr = tcache_ptrs[tcache_id];
other_block = NULL; // also gone too due to flush
this_block = dr_add_block(pc, tcache_id, &blkid);
}
this_block->next = other_block;
if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
HASH_FUNC(hash_table, pc) = this_block;
if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE || this_block == NULL)
return NULL;
block_entry = tcache_ptr;
#if (DRC_DEBUG & 1)
printf("== %csh2 block #%d,%d %08x -> %p\n", sh2->is_slave ? 's' : 'm',
tcache_id, block_counts[tcache_id], pc, block_entry);
if (other_block != NULL) {
printf(" hash collision with %08x\n", other_block->addr);
hash_collisions++;
}
#endif
dbg(1, "== %csh2 block #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
tcache_id, blkid_main, base_pc, block_entry);
while (cycles < BLOCK_CYCLE_LIMIT || delayed_op)
// 1st pass: scan forward for local branches
memset(op_flags, 0, sizeof(op_flags));
for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT; cycles++, pc += 2) {
op = p32x_sh2_read16(pc, sh2);
if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR
pc += 2;
OP_FLAGS(pc) |= OF_DELAY_OP;
break;
}
if ((op & 0xf000) == 0) {
op &= 0xff;
if (op == 0x23 || op == 0x03 || op == 0x0b) { // BRAF, BSRF, RTS
pc += 2;
OP_FLAGS(pc) |= OF_DELAY_OP;
break;
}
continue;
}
if ((op & 0xf0df) == 0x400b) { // JMP, JSR
pc += 2;
OP_FLAGS(pc) |= OF_DELAY_OP;
break;
}
if ((op & 0xf900) == 0x8900) { // BT(S), BF(S)
signed int offs = ((signed int)(op << 24) >> 23);
if (op & 0x0400)
OP_FLAGS(pc + 2) |= OF_DELAY_OP;
branch_target_pc[branch_target_count++] = pc + offs + 4;
if (branch_target_count == MAX_LOCAL_BRANCHES) {
printf("warning: branch target overflow\n");
// will only spawn additional blocks
break;
}
}
}
end_pc = pc;
// clean branch_targets that are not really local,
// and that land on delay slots
for (i = 0, tmp = 0; i < branch_target_count; i++) {
pc = branch_target_pc[i];
if (base_pc <= pc && pc <= end_pc && !(OP_FLAGS(pc) & OF_DELAY_OP))
branch_target_pc[tmp++] = branch_target_pc[i];
}
branch_target_count = tmp;
memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
// -------------------------------------------------
// 2nd pass: actual compilation
pc = base_pc;
for (cycles = 0; pc <= end_pc || drcf.delayed_op; )
{
if (delayed_op > 0)
delayed_op--;
u32 tmp3, tmp4, sr;
if (drcf.delayed_op > 0)
drcf.delayed_op--;
i = find_in_array(branch_target_pc, branch_target_count, pc);
if (i >= 0)
{
if (pc != sh2->pc)
{
/* make "subblock" - just a mid-block entry */
block_desc *subblock;
u16 *drcblk;
int blkid;
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_sub_r_imm(sr, cycles << 12);
cycles = 0;
rcache_flush();
do_host_disasm(tcache_id);
subblock = dr_add_block(pc, tcache_id, &blkid);
if (subblock == NULL)
return NULL;
subblock->end_addr = pc;
if (tcache_id != 0) { // data array, BIOS
drcblk = Pico32xMem->drcblk_da[sh2->is_slave];
drcblk += (pc & 0x00fff) >> SH2_DRCBLK_DA_SHIFT;
*drcblk = (blkid << 1) | 1;
} else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM
drcblk = Pico32xMem->drcblk_ram;
drcblk += (pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
*drcblk = (blkid << 1) | 1;
}
dbg(1, "=== %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
tcache_id, blkid, pc, tcache_ptr);
}
branch_target_ptr[i] = tcache_ptr;
// must update PC
emit_move_r_imm32(SHR_PC, pc);
rcache_clean();
// check cycles
sr = rcache_get_reg(SHR_SR, RC_GR_READ);
emith_cmp_r_imm(sr, 0);
emith_jump_cond(DCOND_LE, sh2_drc_exit);
}
op = p32x_sh2_read16(pc, sh2);
@ -705,19 +841,23 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
emith_move_r_r(tmp, tmp3);
if (tmp2 == SHR_SR)
emith_clear_msb(tmp, tmp, 20); // reserved bits defined by ISA as 0
emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
goto end_op;
case 0x03:
CHECK_UNHANDLED_BITS(0xd0);
// BRAF Rm 0000mmmm00100011
// BSRF Rm 0000mmmm00000011
DELAYED_OP;
if (!(op & 0x20))
emit_move_r_imm32(SHR_PR, pc + 2);
tmp = rcache_get_reg(SHR_PPC, RC_GR_WRITE);
tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
emith_move_r_r(tmp, tmp2);
emith_add_r_imm(tmp, pc + 2);
if (op & 0x20)
emith_add_r_imm(tmp, pc + 2);
else { // BSRF
tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
emith_move_r_imm(tmp3, pc + 2);
emith_add_r_r(tmp, tmp3);
}
cycles++;
goto end_op;
case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
@ -740,10 +880,14 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
{
case 0: // CLRT 0000000000001000
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_bic_r_imm(sr, T);
break;
case 1: // SETT 0000000000011000
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_or_r_imm(sr, T);
break;
case 2: // CLRMAC 0000000000101000
@ -765,6 +909,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
case 1: // DIV0U 0000000000011001
CHECK_UNHANDLED_BITS(0xf00);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_bic_r_imm(sr, M|Q|T);
break;
case 2: // MOVT Rn 0000nnnn00101001
@ -801,14 +947,14 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
{
case 0: // RTS 0000000000001011
DELAYED_OP;
emit_move_r_r(SHR_PPC, SHR_PR);
emit_move_r_r(SHR_PC, SHR_PR);
cycles++;
break;
case 1: // SLEEP 0000000000011011
emit_move_r_imm32(SHR_PC, pc - 2);
tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_clear_msb(tmp, tmp, 20); // clear cycles
test_irq = 1;
drcf.test_irq = 1;
cycles = 1;
break;
case 2: // RTE 0000000000101011
@ -817,7 +963,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
// pop PC
rcache_get_reg_arg(0, SHR_SP);
tmp = emit_memhandler_read(2);
tmp2 = rcache_get_reg(SHR_PPC, RC_GR_WRITE);
tmp2 = rcache_get_reg(SHR_PC, RC_GR_WRITE);
emith_move_r_r(tmp2, tmp);
rcache_free_tmp(tmp);
rcache_clean();
@ -825,11 +971,12 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
tmp = rcache_get_reg_arg(0, SHR_SP);
emith_add_r_imm(tmp, 4);
tmp = emit_memhandler_read(2);
emith_write_sr(tmp);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_write_sr(sr, tmp);
rcache_free_tmp(tmp);
tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
emith_add_r_imm(tmp, 4*2);
test_irq = 1;
drcf.test_irq = 1;
cycles += 3;
break;
default:
@ -917,6 +1064,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_bic_r_imm(sr, M|Q|T);
emith_tst_r_imm(tmp2, (1<<31));
EMITH_SJMP_START(DCOND_EQ);
@ -935,6 +1084,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_bic_r_imm(sr, T);
emith_tst_r_r(tmp2, tmp3);
emit_or_t_if_eq(sr);
@ -960,6 +1111,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
emith_eor_r_r_r(tmp, tmp2, tmp3);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_bic_r_imm(sr, T);
emith_tst_r_imm(tmp, 0x000000ff);
emit_or_t_if_eq(tmp);
@ -1011,6 +1164,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_bic_r_imm(sr, T);
emith_cmp_r_r(tmp2, tmp3);
switch (op & 0x07)
@ -1051,6 +1206,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_tpop_carry(sr, 0);
emith_adcf_r_r(tmp2, tmp2);
emith_tpush_carry(sr, 0); // keep Q1 in T for now
@ -1061,16 +1218,16 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
// add or sub, invert T if carry to get Q1 ^ Q2
// in: (Q ^ M) passed in Q, Q1 in T
emith_sh2_div1_step(tmp2, tmp3, sr);
emith_bic_r_imm(sr, Q);
emith_tst_r_imm(sr, M);
EMITH_SJMP_START(DCOND_EQ);
emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
EMITH_SJMP_END(DCOND_EQ);
emith_tst_r_imm(sr, T);
EMITH_SJMP_START(DCOND_EQ);
emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
EMITH_SJMP_END(DCOND_EQ);
emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
emith_bic_r_imm(sr, Q);
emith_tst_r_imm(sr, M);
EMITH_SJMP_START(DCOND_EQ);
emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
EMITH_SJMP_END(DCOND_EQ);
emith_tst_r_imm(sr, T);
EMITH_SJMP_START(DCOND_EQ);
emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
EMITH_SJMP_END(DCOND_EQ);
emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
goto end_op;
case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
@ -1093,6 +1250,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
if (op & 4) { // adc
emith_tpop_carry(sr, 0);
emith_adcf_r_r(tmp, tmp2);
@ -1108,6 +1267,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_bic_r_imm(sr, T);
if (op & 4) {
emith_addf_r_r(tmp, tmp2);
@ -1138,6 +1299,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
case 2: // SHAL Rn 0100nnnn00100000
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_tpop_carry(sr, 0); // dummy
emith_lslf(tmp, tmp, 1);
emith_tpush_carry(sr, 0);
@ -1149,6 +1312,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
}
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_bic_r_imm(sr, T);
emith_subf_r_imm(tmp, 1);
emit_or_t_if_eq(sr);
@ -1162,6 +1327,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
case 2: // SHAR Rn 0100nnnn00100001
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_tpop_carry(sr, 0); // dummy
if (op & 0x20) {
emith_asrf(tmp, tmp, 1);
@ -1172,6 +1339,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
case 1: // CMP/PZ Rn 0100nnnn00010001
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_bic_r_imm(sr, T);
emith_cmp_r_imm(tmp, 0);
EMITH_SJMP_START(DCOND_LT);
@ -1222,6 +1391,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
case 0x05: // ROTR Rn 0100nnnn00000101
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_tpop_carry(sr, 0); // dummy
if (op & 1) {
emith_rorf(tmp, tmp, 1);
@ -1233,6 +1404,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
case 0x25: // ROTCR Rn 0100nnnn00100101
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_tpop_carry(sr, 0);
if (op & 1) {
emith_rorcf(tmp);
@ -1243,6 +1416,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
case 0x15: // CMP/PL Rn 0100nnnn00010101
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_bic_r_imm(sr, T);
emith_cmp_r_imm(tmp, 0);
EMITH_SJMP_START(DCOND_LE);
@ -1280,8 +1455,11 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
rcache_get_reg_arg(0, GET_Rn());
tmp2 = emit_memhandler_read(2);
if (tmp == SHR_SR) {
emith_write_sr(tmp2);
test_irq = 1;
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_write_sr(sr, tmp2);
drcf.test_irq = 1;
} else {
tmp = rcache_get_reg(tmp, RC_GR_WRITE);
emith_move_r_r(tmp, tmp2);
@ -1343,7 +1521,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
DELAYED_OP;
if (!(op & 0x20))
emit_move_r_imm32(SHR_PR, pc + 2);
emit_move_r_r(SHR_PPC, (op >> 8) & 0x0f);
emit_move_r_r(SHR_PC, (op >> 8) & 0x0f);
cycles++;
break;
case 1: // TAS.B @Rn 0100nnnn00011011
@ -1352,6 +1530,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
rcache_get_reg_arg(0, GET_Rn());
tmp = emit_memhandler_read(0);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_bic_r_imm(sr, T);
emith_cmp_r_imm(tmp, 0);
emit_or_t_if_eq(sr);
@ -1385,8 +1565,11 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
goto default_;
}
if (tmp2 == SHR_SR) {
emith_write_sr(tmp);
test_irq = 1;
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_write_sr(sr, tmp);
drcf.test_irq = 1;
} else {
tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
emith_move_r_r(tmp2, tmp);
@ -1490,6 +1673,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
break;
case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_tpop_carry(sr, 1);
emith_negcf_r_r(tmp2, tmp);
emith_tpush_carry(sr, 1);
@ -1553,6 +1738,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
tmp = rcache_get_tmp();
tmp2 = rcache_get_reg(0, RC_GR_READ);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_move_r_imm_s8(tmp, op & 0xff);
emith_bic_r_imm(sr, T);
emith_cmp_r_r(tmp2, tmp);
@ -1570,11 +1757,19 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
int jmp_cond = (op & 0x0200) ? DCOND_NE : DCOND_EQ;
int insn_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE;
signed int offs = ((signed int)(op << 24) >> 23);
tmp = rcache_get_reg(delayed_op ? SHR_PPC : SHR_PC, RC_GR_WRITE);
emith_move_r_imm(tmp, pc + (delayed_op ? 2 : 0));
emith_sh2_test_t();
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (find_in_array(branch_target_pc, branch_target_count, pc + offs + 2) >= 0) {
branch_patch_pc[branch_patch_count] = pc + offs + 2;
branch_patch_cond = insn_cond;
goto end_op;
}
// can't resolve branch, cause end of block
tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
emith_move_r_imm(tmp, pc + (drcf.delayed_op ? 2 : 0));
emith_tst_r_imm(sr, T);
EMITH_SJMP_START(jmp_cond);
if (!delayed_op)
if (!drcf.delayed_op)
offs += 2;
if (offs < 0) {
emith_sub_r_imm_c(insn_cond, tmp, -offs);
@ -1582,7 +1777,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
emith_add_r_imm_c(insn_cond, tmp, offs);
EMITH_SJMP_END(jmp_cond);
cycles += 2;
if (!delayed_op)
if (!drcf.delayed_op)
goto end_block_btf;
goto end_op;
}}
@ -1606,7 +1801,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
DELAYED_OP;
do_bra:
tmp = ((signed int)(op << 20) >> 19);
emit_move_r_imm32(SHR_PPC, pc + tmp + 2);
emit_move_r_imm32(SHR_PC, pc + tmp + 2);
cycles++;
break;
@ -1654,7 +1849,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
tmp = rcache_get_reg_arg(0, SHR_SP);
emith_add_r_imm(tmp, 4);
tmp = rcache_get_reg_arg(1, SHR_SR);
emith_clear_msb(tmp, tmp, 20);
emith_clear_msb(tmp, tmp, 22);
emit_memhandler_write(2);
// push PC
rcache_get_reg_arg(0, SHR_SP);
@ -1676,6 +1871,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
case 0x0800: // TST #imm,R0 11001000iiiiiiii
tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_bic_r_imm(sr, T);
emith_tst_r_imm(tmp, op & 0xff);
emit_or_t_if_eq(sr);
@ -1695,6 +1892,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (drcf.delayed_op)
DELAY_SAVE_T(sr);
emith_bic_r_imm(sr, T);
emith_tst_r_imm(tmp, op & 0xff);
emit_or_t_if_eq(sr);
@ -1759,58 +1958,100 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
}
end_op:
if (delayed_op == 1)
emit_move_r_r(SHR_PC, SHR_PPC);
// block-local conditional branch handling (with/without delay)
if (branch_patch_cond != -1 && drcf.delayed_op != 2) {
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
// handle cycles
emith_sub_r_imm(sr, cycles << 12);
cycles = 0;
rcache_clean();
if (test_irq && delayed_op != 2) {
if (!delayed_op)
emit_move_r_imm32(SHR_PC, pc);
rcache_flush();
emith_pass_arg_r(0, CONTEXT_REG);
emith_call(sh2_test_irq);
goto end_block_btf;
if (drcf.use_saved_t)
emith_tst_r_imm(sr, T_save);
else
emith_tst_r_imm(sr, T);
branch_patch_ptr[branch_patch_count] = tcache_ptr;
emith_jump_patchable(branch_patch_cond);
drcf.use_saved_t = 0;
branch_patch_cond = -1;
branch_patch_count++;
drcf.delayed_op = 0; // XXX: delayed_op ends block, so must override
if (branch_patch_count == MAX_LOCAL_BRANCHES) {
printf("too many local branches\n");
break;
}
}
if (delayed_op == 1)
// test irq?
if (drcf.test_irq && drcf.delayed_op != 2)
break;
if (drcf.delayed_op == 1)
break;
do_host_disasm(tcache_id);
}
// delayed_op means some kind of branch - PC already handled
if (!delayed_op)
if (!drcf.delayed_op)
emit_move_r_imm32(SHR_PC, pc);
if (drcf.test_irq) {
rcache_flush();
emith_pass_arg_r(0, CONTEXT_REG);
emith_call(sh2_test_irq);
}
end_block_btf:
this_block->end_addr = pc;
// mark memory blocks as containing compiled code
if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
// data array, BIOS
u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave];
tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
Pico32xMem->drcblk_da[sh2->is_slave][tmp] = (blkid << 1) | 1;
for (++tmp; tmp < tmp2; tmp++) {
if (drcblk[tmp])
break; // dont overwrite overlay block
drcblk[tmp] = blkid << 1;
}
}
else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM
tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
Pico32xMem->drcblk_ram[tmp] = (blkid << 1) | 1;
for (++tmp; tmp < tmp2; tmp++) {
if (Pico32xMem->drcblk_ram[tmp])
break;
Pico32xMem->drcblk_ram[tmp] = blkid << 1;
}
}
tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_sub_r_imm(tmp, cycles << 12);
rcache_flush();
emith_jump(sh2_drc_exit);
// link local branches
for (i = 0; i < branch_patch_count; i++) {
void *target;
int t;
//printf("patch %08x %p\n", branch_patch_pc[i], branch_patch_ptr[i]);
t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
if (branch_target_ptr[t] != NULL)
target = branch_target_ptr[t];
else {
// flush pc and go back to dispatcher (for now)
printf("stray branch to %08x %p\n", branch_patch_pc[i], tcache_ptr);
target = tcache_ptr;
emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
rcache_flush();
emith_jump(sh2_drc_exit);
}
emith_jump_patch(branch_patch_ptr[i], target);
}
// mark memory blocks as containing compiled code
if (tcache_id != 0) {
// data array, BIOS
u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave];
tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
drcblk[tmp] = (blkid_main << 1) | 1;
for (++tmp; tmp < tmp2; tmp++) {
if (drcblk[tmp])
continue; // dont overwrite overlay block(s)
drcblk[tmp] = blkid_main << 1;
}
}
else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM
tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
Pico32xMem->drcblk_ram[tmp] = (blkid_main << 1) | 1;
for (++tmp; tmp < tmp2; tmp++) {
if (Pico32xMem->drcblk_ram[tmp])
continue;
Pico32xMem->drcblk_ram[tmp] = blkid_main << 1;
}
}
tcache_ptrs[tcache_id] = tcache_ptr;
#ifdef ARM
@ -1824,6 +2065,13 @@ end_block_btf:
insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled);
if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
/*
printf("~~~\n");
tcache_dsm_ptrs[tcache_id] = block_entry;
do_host_disasm(tcache_id);
printf("~~~\n");
*/
#if (DRC_DEBUG & 2)
fflush(stdout);
#endif
@ -1846,16 +2094,18 @@ void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2)
{
void *block = NULL;
block_desc *bd = NULL;
int tcache_id = 0;
// FIXME: must avoid doing it so often..
//sh2_test_irq(sh2);
// we have full block id tables for data_array and RAM
// BIOS goes to data_array table too
if ((sh2->pc & 0xff000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
int blkid = Pico32xMem->drcblk_da[sh2->is_slave][(sh2->pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT];
tcache_id = 1 + sh2->is_slave;
if (blkid & 1) {
bd = &block_tables[1 + sh2->is_slave][blkid >> 1];
bd = &block_tables[tcache_id][blkid >> 1];
block = bd->tcache_ptr;
}
}
@ -1863,7 +2113,7 @@ void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2)
else if ((sh2->pc & 0xc6000000) == 0x06000000) {
int blkid = Pico32xMem->drcblk_ram[(sh2->pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT];
if (blkid & 1) {
bd = &block_tables[0][blkid >> 1];
bd = &block_tables[tcache_id][blkid >> 1];
block = bd->tcache_ptr;
}
}
@ -1880,7 +2130,12 @@ void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2)
}
if (block == NULL)
block = sh2_translate(sh2, bd);
block = sh2_translate(sh2, tcache_id);
if (block == NULL) {
// sh2_translate failed, possibly tcache overflow, clean up and try again
flush_tcache(tcache_id);
block = sh2_translate(sh2, tcache_id);
}
dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
sh2->pc, block, (signed int)sh2->sr >> 12);
@ -1889,6 +2144,7 @@ void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2)
bd->refcount++;
#endif
sh2_drc_entry(block, sh2);
dbg(4, "= leave %p", block);
}
}
@ -1897,6 +2153,7 @@ static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a)
u16 id = *p >> 1;
block_desc *bd = btab + id;
// FIXME: skip subblocks; do both directions
dbg(1, " killing block %08x", bd->addr);
bd->addr = bd->end_addr = 0;
@ -1942,6 +2199,8 @@ void sh2_execute(SH2 *sh2c, int cycles)
cycles = sh2c->cycles_aim - sh2c->cycles_done;
// cycles are kept in SHR_SR unused bits (upper 20)
// bit19 contains T saved for delay slot
// others are usual SH2 flags
sh2c->sr &= 0x3f3;
sh2c->sr |= cycles << 12;
sh2_drc_dispatcher(sh2c);