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sh2 drc, fix for SH2 T handling in Mips/RiscV

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This commit is contained in:
kub 2020-06-25 16:49:17 +02:00
parent 09cab6d27a
commit 18c95d9f57
2 changed files with 10 additions and 17 deletions
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2
cpu/drc/emit_mips.c
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@ -1801,7 +1801,7 @@ static void emith_set_t_cond(int sr, int cond)
EMIT(MIPS_SLTU_IMM(AT,AT, 1)); r=AT; val++; break;
} else if ((b>>5) == OP_BNE) {
EMIT(MIPS_XOR_REG(AT, r, b&0x1f));
EMIT(MIPS_SLTU_IMM(AT,Z0,AT)); r=AT; val++; break;
EMIT(MIPS_SLTU_REG(AT,Z0,AT)); r=AT; val++; break;
}
}
if (val) {