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sh2 drc, fix for SH2 T handling in Mips/RiscV

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This commit is contained in:
kub 2020-06-25 16:49:17 +02:00
parent 09cab6d27a
commit 18c95d9f57
2 changed files with 10 additions and 17 deletions
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25
cpu/drc/emit_riscv.c
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@ -1601,28 +1601,21 @@ static void emith_set_t_cond(int sr, int cond)
u32 val = 0, inv = 0;
// try to avoid jumping around if possible
if (emith_cmp_rs >= 0) {
if (emith_cmp_rt >= 0)
b = emith_cmpr_check(emith_cmp_rs, emith_cmp_rt, cond, &r, &s);
else
b = emith_cmpi_check(emith_cmp_rs, emith_cmp_imm, cond, &r, &s);
} else {
b = emith_cond_check(cond, &r, &s);
if (r == Z0) {
if (b == F1_BEQ || b == F1_BGE || b == F1_BGEU)
emith_or_r_imm(sr, T);
return;
} else if (r == FC)
val++, inv = (b == F1_BEQ);
}
b = emith_cond_check(cond, &r, &s);
if (r == Z0) {
if (b == F1_BEQ || b == F1_BGE || b == F1_BGEU)
emith_or_r_imm(sr, T);
return;
} else if (r == FC)
val++, inv = (b == F1_BEQ);
if (!val) switch (b) {
case F1_BEQ: if (s == Z0) { EMIT(R5_SLTU_IMM(AT,r ,1)); r=AT; val++; break; }
EMIT(R5_XOR_REG(AT, r, s));
EMIT(R5_SLTU_IMM(AT,AT, 1)); r=AT; val++; break;
case F1_BNE: if (s == Z0) { EMIT(R5_SLTU_IMM(AT,Z0,r)); r=AT; val++; break; }
case F1_BNE: if (s == Z0) { EMIT(R5_SLTU_REG(AT,Z0,r)); r=AT; val++; break; }
EMIT(R5_XOR_REG(AT, r, s));
EMIT(R5_SLTU_IMM(AT,Z0,AT)); r=AT; val++; break;
EMIT(R5_SLTU_REG(AT,Z0,AT)); r=AT; val++; break;
case F1_BLTU: EMIT(R5_SLTU_REG(AT, r, s)); r=AT; val++; break;
case F1_BGEU: EMIT(R5_SLTU_REG(AT, r, s)); r=AT; val++; inv++; break;
case F1_BLT: EMIT(R5_SLT_REG(AT, r, s)); r=AT; val++; break;