mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
rework sh2 sync, again..
also some new debug and poll code VF seems to be ok at least..
This commit is contained in:
notaz
parent
51d86e55f6
commit
19886062f1
9 changed files with 507 additions and 169 deletions
180
pico/32x/32x.c
180
pico/32x/32x.c
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@ -12,6 +12,8 @@
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struct Pico32x Pico32x;
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SH2 sh2s[2];
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#define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_SLEEP)
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static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
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{
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if (sh2->pending_irl > sh2->pending_int_irq) {
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@ -28,11 +30,15 @@ static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
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}
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// if !nested_call, must sync CPUs before calling this
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void p32x_update_irls(int nested_call)
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void p32x_update_irls(SH2 *active_sh2)
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{
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int irqs, mlvl = 0, slvl = 0;
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int m68k_cycles = 0;
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int mrun, srun;
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if (active_sh2 != NULL)
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m68k_cycles = sh2_cycles_done_m68k(active_sh2);
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// msh2
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irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES);
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while ((irqs >>= 1))
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@ -45,9 +51,14 @@ void p32x_update_irls(int nested_call)
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slvl++;
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slvl *= 2;
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mrun = sh2_irl_irq(&msh2, mlvl, nested_call);
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srun = sh2_irl_irq(&ssh2, slvl, nested_call);
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p32x_poll_event(mrun | (srun << 1), 0);
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mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 != NULL);
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if (mrun)
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p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
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srun = sh2_irl_irq(&ssh2, slvl, active_sh2 != NULL);
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if (srun)
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p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
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elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
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}
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@ -158,8 +169,9 @@ void PicoReset32x(void)
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{
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if (PicoAHW & PAHW_32X) {
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Pico32x.sh2irqs |= P32XI_VRES;
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p32x_update_irls(0);
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p32x_poll_event(3, 0);
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p32x_update_irls(NULL);
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p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
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p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
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p32x_timers_recalc();
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}
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}
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@ -204,10 +216,19 @@ static void p32x_start_blank(void)
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}
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Pico32x.sh2irqs |= P32XI_VINT;
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p32x_update_irls(0);
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p32x_poll_event(3, 1);
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p32x_update_irls(NULL);
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p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
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p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
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}
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// compare cycles, handling overflows
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// check if a > b
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#define CYCLES_GT(a, b) \
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((int)((a) - (b)) > 0)
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// check if a >= b
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#define CYCLES_GE(a, b) \
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((int)((a) - (b)) >= 0)
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/* events */
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static void pwm_irq_event(unsigned int now)
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{
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@ -215,13 +236,14 @@ static void pwm_irq_event(unsigned int now)
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p32x_pwm_schedule(now);
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Pico32x.sh2irqs |= P32XI_PWM;
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p32x_update_irls(0);
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p32x_update_irls(NULL);
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}
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static void fillend_event(unsigned int now)
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{
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Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN;
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p32x_poll_event(3, 1);
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p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, now);
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p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now);
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}
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typedef void (event_cb)(unsigned int now);
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@ -233,18 +255,32 @@ static event_cb *event_cbs[] = {
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[P32X_EVENT_FILLEND] = fillend_event,
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};
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// schedule event at some time (in m68k clocks)
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void p32x_event_schedule(enum p32x_event event, unsigned int now, int after)
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// schedule event at some time 'after', in m68k clocks
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void p32x_event_schedule(unsigned int now, enum p32x_event event, int after)
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{
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unsigned int when = (now + after) | 1;
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unsigned int when;
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when = (now + after) | 1;
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elprintf(EL_32X, "new event #%u %u->%u", event, now, when);
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event_times[event] = when;
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if (event_time_next == 0 || (int)(event_time_next - now) > after)
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if (event_time_next == 0 || CYCLES_GT(event_time_next, when))
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event_time_next = when;
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}
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void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after)
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{
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unsigned int now = sh2_cycles_done_m68k(sh2);
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int left_to_next;
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p32x_event_schedule(now, event, after);
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left_to_next = (event_time_next - now) * 3;
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if (sh2_cycles_left(sh2) > left_to_next)
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sh2_end_run(sh2, left_to_next);
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}
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static void run_events(unsigned int until)
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{
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int oldest, oldest_diff, time;
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@ -283,13 +319,61 @@ static void run_events(unsigned int until)
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elprintf(EL_32X, "next event #%d at %u", oldest, event_time_next);
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}
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// compare cycles, handling overflows
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// check if a > b
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#define CYCLES_GT(a, b) \
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((int)((a) - (b)) > 0)
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// check if a >= b
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#define CYCLES_GE(a, b) \
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((int)((a) - (b)) >= 0)
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static inline void run_sh2(SH2 *sh2, int m68k_cycles)
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{
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int cycles, done;
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pevt_log_sh2_o(sh2, EVT_RUN_START);
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sh2->state |= SH2_STATE_RUN;
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cycles = C_M68K_TO_SH2(*sh2, m68k_cycles);
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elprintf(EL_32X, "%csh2 +run %u %d",
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sh2->is_slave?'s':'m', sh2->m68krcycles_done, cycles);
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done = sh2_execute(sh2, cycles);
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sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done);
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sh2->state &= ~SH2_STATE_RUN;
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pevt_log_sh2_o(sh2, EVT_RUN_END);
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elprintf(EL_32X, "%csh2 -run %u %d",
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sh2->is_slave?'s':'m', sh2->m68krcycles_done, done);
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}
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// sync other sh2 to this one
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// note: recursive call
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void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
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{
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SH2 *osh2 = &sh2s[sh2->is_slave ^ 1];
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int left_to_event;
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int m68k_cycles;
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if (osh2->state & SH2_STATE_RUN)
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return;
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m68k_cycles = m68k_target - osh2->m68krcycles_done;
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if (m68k_cycles < 200)
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return;
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if (osh2->state & SH2_IDLE_STATES) {
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osh2->m68krcycles_done = m68k_target;
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return;
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}
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elprintf(EL_32X, "%csh2 sync to %u %d",
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osh2->is_slave?'s':'m', m68k_target, m68k_cycles);
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run_sh2(osh2, m68k_cycles);
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// there might be new event to schedule current sh2 to
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if (event_time_next) {
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left_to_event = event_time_next - m68k_target;
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left_to_event *= 3;
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if (sh2_cycles_left(sh2) > left_to_event) {
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if (left_to_event < 1)
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left_to_event = 1;
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sh2_end_run(sh2, left_to_event);
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}
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}
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}
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#define sync_sh2s_normal p32x_sync_sh2s
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//#define sync_sh2s_lockstep p32x_sync_sh2s
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@ -298,7 +382,7 @@ static void run_events(unsigned int until)
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void sync_sh2s_normal(unsigned int m68k_target)
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{
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unsigned int now, target, timer_cycles;
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int cycles, done;
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int cycles;
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elprintf(EL_32X, "sh2 sync to %u", m68k_target);
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@ -327,42 +411,50 @@ void sync_sh2s_normal(unsigned int m68k_target)
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target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done,
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m68k_target - now, Pico32x.emu_flags);
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if (Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL)) {
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ssh2.m68krcycles_done = target;
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}
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else {
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if (!(ssh2.state & SH2_IDLE_STATES)) {
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cycles = target - ssh2.m68krcycles_done;
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if (cycles > 0) {
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done = sh2_execute(&ssh2, C_M68K_TO_SH2(ssh2, cycles));
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ssh2.m68krcycles_done += C_SH2_TO_M68K(ssh2, done);
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run_sh2(&ssh2, cycles);
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if (event_time_next && CYCLES_GT(target, event_time_next))
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target = event_time_next;
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}
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}
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if (Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL)) {
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msh2.m68krcycles_done = target;
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}
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else {
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if (!(msh2.state & SH2_IDLE_STATES)) {
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cycles = target - msh2.m68krcycles_done;
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if (cycles > 0) {
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done = sh2_execute(&msh2, C_M68K_TO_SH2(msh2, cycles));
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msh2.m68krcycles_done += C_SH2_TO_M68K(msh2, done);
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run_sh2(&msh2, cycles);
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if (event_time_next && CYCLES_GT(target, event_time_next))
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target = event_time_next;
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}
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}
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now = msh2.m68krcycles_done;
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if (CYCLES_GT(now, ssh2.m68krcycles_done))
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now = ssh2.m68krcycles_done;
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now = target;
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if (!(msh2.state & SH2_IDLE_STATES)) {
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if (CYCLES_GT(now, msh2.m68krcycles_done))
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now = msh2.m68krcycles_done;
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}
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if (!(ssh2.state & SH2_IDLE_STATES)) {
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if (CYCLES_GT(now, ssh2.m68krcycles_done))
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now = ssh2.m68krcycles_done;
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}
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}
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p32x_timers_do(now - timer_cycles);
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timer_cycles = now;
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}
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// advance idle CPUs
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if (msh2.state & SH2_IDLE_STATES) {
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if (CYCLES_GT(m68k_target, msh2.m68krcycles_done))
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msh2.m68krcycles_done = m68k_target;
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}
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if (ssh2.state & SH2_IDLE_STATES) {
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if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done))
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ssh2.m68krcycles_done = m68k_target;
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}
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}
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#define STEP_68K 24
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@ -383,8 +475,8 @@ void sync_sh2s_lockstep(unsigned int m68k_target)
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#define CPUS_RUN(m68k_cycles,s68k_cycles) do { \
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SekRunM68k(m68k_cycles); \
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if (Pico32x.emu_flags & P32XF_68KPOLL) \
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p32x_sync_sh2s(SekCycleCntT + SekCycleCnt); \
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if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
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p32x_sync_sh2s(SekCyclesDoneT2()); \
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} while (0)
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#define PICO_32X
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@ -396,13 +488,15 @@ void PicoFrame32x(void)
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if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
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Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
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p32x_poll_event(3, 1);
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p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
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p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
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PicoFrameStart();
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PicoFrameHints();
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sh2_drc_frame();
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elprintf(EL_32X, "poll: %02x", Pico32x.emu_flags);
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elprintf(EL_32X, "poll: %02x %02x %02x",
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Pico32x.emu_flags & 3, msh2.state, ssh2.state);
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}
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// calculate multipliers against 68k clock (7670442)
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@ -428,9 +522,9 @@ void Pico32xStateLoaded(int is_early)
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return;
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}
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SekCycleCnt = 0;
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sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCycleCntT;
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p32x_update_irls(0);
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p32x_poll_event(3, 0);
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p32x_update_irls(NULL);
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p32x_timers_recalc();
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run_events(SekCycleCntT);
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}
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@ -42,13 +42,6 @@
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#include "../memory.h"
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#include "../../cpu/sh2/compiler.h"
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#if 0
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#undef ash2_end_run
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#undef SekEndRun
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#define ash2_end_run(x)
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#define SekEndRun(x)
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#endif
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static const char str_mars[] = "MARS";
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void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
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@ -57,64 +50,96 @@ struct Pico32xMem *Pico32xMem;
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static void bank_switch(int b);
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// poll detection
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#define POLL_THRESHOLD 6
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#define POLL_THRESHOLD 3
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struct poll_det {
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u32 addr, cycles, cyc_max;
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int cnt, flag;
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};
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static struct poll_det m68k_poll, sh2_poll[2];
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static struct {
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u32 addr, cycles;
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int cnt;
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} m68k_poll;
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static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp)
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static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
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{
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int ret = 0, flag = pd->flag;
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int ret = 0;
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if (is_vdp)
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flag <<= 3;
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if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) {
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pd->cnt++;
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if (pd->cnt > POLL_THRESHOLD) {
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if (!(Pico32x.emu_flags & flag)) {
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elprintf(EL_32X, "%s poll addr %08x, cyc %u",
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flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" :
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(flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles);
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if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2
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&& cycles - m68k_poll.cycles <= 64)
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{
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if (m68k_poll.cnt++ > POLL_THRESHOLD) {
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if (!(Pico32x.emu_flags & flags)) {
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elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
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a, cycles - m68k_poll.cycles);
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ret = 1;
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}
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Pico32x.emu_flags |= flag;
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Pico32x.emu_flags |= flags;
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}
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}
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else {
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pd->cnt = 0;
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pd->addr = a;
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m68k_poll.cnt = 0;
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m68k_poll.addr = a;
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}
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pd->cycles = cycles;
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m68k_poll.cycles = cycles;
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return ret;
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}
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static int p32x_poll_undetect(struct poll_det *pd, int is_vdp)
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void p32x_m68k_poll_event(u32 flags)
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{
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int ret = 0, flag = pd->flag;
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if (is_vdp)
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flag <<= 3; // VDP only
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if (Pico32x.emu_flags & flags) {
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elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags,
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Pico32x.emu_flags & ~flags);
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Pico32x.emu_flags &= ~flags;
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SekSetStop(0);
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}
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m68k_poll.addr = m68k_poll.cnt = 0;
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}
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|
||||
static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags)
|
||||
{
|
||||
int cycles_left = sh2_cycles_left(sh2);
|
||||
|
||||
if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
|
||||
if (sh2->poll_cnt++ > 3) {
|
||||
if (!(sh2->state & flags))
|
||||
elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m',
|
||||
sh2->state, sh2->state | flags);
|
||||
|
||||
sh2->state |= flags;
|
||||
sh2_end_run(sh2, 1);
|
||||
pevt_log_sh2(sh2, EVT_POLL_START);
|
||||
return;
|
||||
}
|
||||
}
|
||||
else
|
||||
flag |= flag << 3; // both
|
||||
if (Pico32x.emu_flags & flag) {
|
||||
elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag);
|
||||
ret = 1;
|
||||
}
|
||||
Pico32x.emu_flags &= ~flag;
|
||||
pd->addr = pd->cnt = 0;
|
||||
return ret;
|
||||
sh2->poll_cnt = 0;
|
||||
sh2->poll_addr = a;
|
||||
sh2->poll_cycles = cycles_left;
|
||||
}
|
||||
|
||||
void p32x_poll_event(int cpu_mask, int is_vdp)
|
||||
void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
|
||||
{
|
||||
if (cpu_mask & 1)
|
||||
p32x_poll_undetect(&sh2_poll[0], is_vdp);
|
||||
if (cpu_mask & 2)
|
||||
p32x_poll_undetect(&sh2_poll[1], is_vdp);
|
||||
if (sh2->state & flags) {
|
||||
elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m',
|
||||
sh2->state, sh2->state & ~flags);
|
||||
|
||||
if (sh2->m68krcycles_done < m68k_cycles)
|
||||
sh2->m68krcycles_done = m68k_cycles;
|
||||
|
||||
pevt_log_sh2_o(sh2, EVT_POLL_END);
|
||||
}
|
||||
|
||||
sh2->state &= ~flags;
|
||||
sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
|
||||
}
|
||||
|
||||
static void sh2s_sync_on_read(SH2 *sh2)
|
||||
{
|
||||
int cycles;
|
||||
if (sh2->poll_cnt != 0)
|
||||
return;
|
||||
|
||||
cycles = sh2_cycles_done(sh2);
|
||||
if (cycles > 600)
|
||||
p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3);
|
||||
}
|
||||
|
||||
// SH2 faking
|
||||
|
|
@ -165,8 +190,7 @@ static void dma_68k2sh2_do(void)
|
|||
elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen);
|
||||
|
||||
// HACK: assume bus is busy and SH2 is halted
|
||||
// XXX: use different mechanism for this, not poll det
|
||||
Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL;
|
||||
msh2.state |= SH2_STATE_SLEEP;
|
||||
|
||||
for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) {
|
||||
elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen);
|
||||
|
|
@ -182,7 +206,7 @@ static void dma_68k2sh2_do(void)
|
|||
Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
|
||||
if (dmac0->tcr0 == 0) {
|
||||
dmac0->chcr0 |= 2; // DMA has ended normally
|
||||
p32x_poll_undetect(&sh2_poll[0], 0);
|
||||
p32x_sh2_poll_event(&sh2s[0], SH2_STATE_SLEEP, SekCyclesDoneT());
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -211,7 +235,7 @@ static u32 p32x_reg_read16(u32 a)
|
|||
p32x_sync_sh2s(cycles);
|
||||
if (Pico32x.comm_dirty_sh2 & comreg)
|
||||
Pico32x.comm_dirty_sh2 &= ~comreg;
|
||||
else if (p32x_poll_detect(&m68k_poll, a, cycles, 0)) {
|
||||
else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
|
||||
SekSetStop(1);
|
||||
SekEndTimeslice(16);
|
||||
}
|
||||
|
|
@ -255,12 +279,12 @@ static void p32x_reg_write8(u32 a, u32 d)
|
|||
if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
|
||||
p32x_sync_sh2s(SekCyclesDoneT());
|
||||
Pico32x.sh2irqi[0] |= P32XI_CMD;
|
||||
p32x_update_irls(0);
|
||||
p32x_update_irls(NULL);
|
||||
}
|
||||
if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
|
||||
p32x_sync_sh2s(SekCyclesDoneT());
|
||||
Pico32x.sh2irqi[1] |= P32XI_CMD;
|
||||
p32x_update_irls(0);
|
||||
p32x_update_irls(NULL);
|
||||
}
|
||||
return;
|
||||
case 5: // bank
|
||||
|
|
@ -285,14 +309,14 @@ static void p32x_reg_write8(u32 a, u32 d)
|
|||
|
||||
if (r8[a ^ 1] == d)
|
||||
return;
|
||||
|
||||
|
||||
comreg = 1 << (a & 0x0f) / 2;
|
||||
if (Pico32x.comm_dirty_68k & comreg)
|
||||
p32x_sync_sh2s(cycles);
|
||||
|
||||
r8[a ^ 1] = d;
|
||||
p32x_poll_undetect(&sh2_poll[0], 0);
|
||||
p32x_poll_undetect(&sh2_poll[1], 0);
|
||||
p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
|
||||
p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
|
||||
Pico32x.comm_dirty_68k |= comreg;
|
||||
|
||||
if (cycles - (int)msh2.m68krcycles_done > 120)
|
||||
|
|
@ -351,8 +375,8 @@ static void p32x_reg_write16(u32 a, u32 d)
|
|||
p32x_sync_sh2s(cycles);
|
||||
|
||||
r[a / 2] = d;
|
||||
p32x_poll_undetect(&sh2_poll[0], 0);
|
||||
p32x_poll_undetect(&sh2_poll[1], 0);
|
||||
p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
|
||||
p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
|
||||
Pico32x.comm_dirty_68k |= comreg;
|
||||
|
||||
if (cycles - (int)msh2.m68krcycles_done > 120)
|
||||
|
|
@ -382,9 +406,6 @@ static void p32x_vdp_write8(u32 a, u32 d)
|
|||
u16 *r = Pico32x.vdp_regs;
|
||||
a &= 0x0f;
|
||||
|
||||
// for FEN checks between writes
|
||||
sh2_poll[0].cnt = 0;
|
||||
|
||||
// TODO: verify what's writeable
|
||||
switch (a) {
|
||||
case 0x01:
|
||||
|
|
@ -412,7 +433,7 @@ static void p32x_vdp_write8(u32 a, u32 d)
|
|||
}
|
||||
}
|
||||
|
||||
static void p32x_vdp_write16(u32 a, u32 d, u32 cycles)
|
||||
static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
|
||||
{
|
||||
a &= 0x0e;
|
||||
if (a == 6) { // fill start
|
||||
|
|
@ -430,9 +451,10 @@ static void p32x_vdp_write16(u32 a, u32 d, u32 cycles)
|
|||
}
|
||||
Pico32x.vdp_regs[0x06 / 2] = a;
|
||||
Pico32x.vdp_regs[0x08 / 2] = d;
|
||||
if (cycles > 0) {
|
||||
if (sh2 != NULL && len > 4) {
|
||||
Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
|
||||
p32x_event_schedule(P32X_EVENT_FILLEND, cycles, len);
|
||||
// supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles?
|
||||
p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
|
@ -452,8 +474,8 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
|
|||
case 0x00: // adapter/irq ctl
|
||||
return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
|
||||
case 0x04: // H count (often as comm too)
|
||||
if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(&sh2s[cpuid]), 0))
|
||||
ash2_end_run(&sh2s[cpuid], 8);
|
||||
sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
|
||||
sh2s_sync_on_read(&sh2s[cpuid]);
|
||||
return Pico32x.sh2_regs[4 / 2];
|
||||
case 0x10: // DREQ len
|
||||
return r[a / 2];
|
||||
|
|
@ -467,12 +489,12 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
|
|||
int comreg = 1 << (a & 0x0f) / 2;
|
||||
if (Pico32x.comm_dirty_68k & comreg)
|
||||
Pico32x.comm_dirty_68k &= ~comreg;
|
||||
else if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(&sh2s[cpuid]), 0))
|
||||
ash2_end_run(&sh2s[cpuid], 8);
|
||||
else
|
||||
sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
|
||||
sh2s_sync_on_read(&sh2s[cpuid]);
|
||||
return r[a / 2];
|
||||
}
|
||||
if ((a & 0x30) == 0x30) {
|
||||
sh2_poll[cpuid].cnt = 0;
|
||||
return p32x_pwm_read16(a);
|
||||
}
|
||||
|
||||
|
|
@ -482,22 +504,32 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
|
|||
static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
|
||||
{
|
||||
a &= 0xff;
|
||||
|
||||
sh2s[cpuid].poll_addr = 0;
|
||||
|
||||
switch (a) {
|
||||
case 0: // FM
|
||||
Pico32x.regs[0] &= ~P32XS_FM;
|
||||
Pico32x.regs[0] |= (d << 8) & P32XS_FM;
|
||||
return;
|
||||
case 1: //
|
||||
case 1: // HEN/irq masks
|
||||
if ((d ^ Pico32x.sh2_regs[0]) & 0x80)
|
||||
elprintf(EL_ANOMALY|EL_32X, "HEN");
|
||||
Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
|
||||
Pico32x.sh2_regs[0] &= ~0x80;
|
||||
Pico32x.sh2_regs[0] |= d & 0x80;
|
||||
if (d & 1)
|
||||
p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // XXX: timing?
|
||||
p32x_update_irls(1);
|
||||
p32x_pwm_schedule_sh2(&sh2s[cpuid]);
|
||||
p32x_update_irls(&sh2s[cpuid]);
|
||||
return;
|
||||
case 5: // H count
|
||||
Pico32x.sh2_regs[4 / 2] = d & 0xff;
|
||||
p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
|
||||
d &= 0xff;
|
||||
if (Pico32x.sh2_regs[4 / 2] != d) {
|
||||
Pico32x.sh2_regs[4 / 2] = d;
|
||||
p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
|
||||
sh2_cycles_done_m68k(&sh2s[cpuid]));
|
||||
sh2_end_run(&sh2s[cpuid], 4);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -508,9 +540,9 @@ static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
|
|||
return;
|
||||
|
||||
r8[a ^ 1] = d;
|
||||
if (p32x_poll_undetect(&m68k_poll, 0))
|
||||
SekSetStop(0);
|
||||
p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
|
||||
p32x_m68k_poll_event(P32XF_68KCPOLL);
|
||||
p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
|
||||
sh2_cycles_done_m68k(&sh2s[cpuid]));
|
||||
comreg = 1 << (a & 0x0f) / 2;
|
||||
Pico32x.comm_dirty_sh2 |= comreg;
|
||||
return;
|
||||
|
|
@ -521,6 +553,8 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
|
|||
{
|
||||
a &= 0xfe;
|
||||
|
||||
sh2s[cpuid].poll_addr = 0;
|
||||
|
||||
// comm
|
||||
if ((a & 0x30) == 0x20) {
|
||||
int comreg;
|
||||
|
|
@ -528,9 +562,9 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
|
|||
return;
|
||||
|
||||
Pico32x.regs[a / 2] = d;
|
||||
if (p32x_poll_undetect(&m68k_poll, 0))
|
||||
SekSetStop(0);
|
||||
p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
|
||||
p32x_m68k_poll_event(P32XF_68KCPOLL);
|
||||
p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
|
||||
sh2_cycles_done_m68k(&sh2s[cpuid]));
|
||||
comreg = 1 << (a & 0x0f) / 2;
|
||||
Pico32x.comm_dirty_sh2 |= comreg;
|
||||
return;
|
||||
|
|
@ -553,7 +587,7 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
|
|||
case 0x1c:
|
||||
Pico32x.sh2irqs &= ~P32XI_PWM;
|
||||
if (!(Pico32x.emu_flags & P32XF_PWM_PEND))
|
||||
p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // timing?
|
||||
p32x_pwm_schedule_sh2(&sh2s[cpuid]);
|
||||
goto irls;
|
||||
}
|
||||
|
||||
|
|
@ -561,7 +595,7 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
|
|||
return;
|
||||
|
||||
irls:
|
||||
p32x_update_irls(1);
|
||||
p32x_update_irls(&sh2s[cpuid]);
|
||||
}
|
||||
|
||||
// ------------------------------------------------------------------
|
||||
|
|
@ -693,7 +727,7 @@ static void sh2_peripheral_write32(u32 a, u32 d, int id)
|
|||
dmac0->tcr0 &= 0xffffff;
|
||||
|
||||
// HACK: assume 68k starts writing soon and end the timeslice
|
||||
ash2_end_run(&sh2s[id], 16);
|
||||
sh2_end_run(&sh2s[id], 16);
|
||||
|
||||
// DREQ is only sent after first 4 words are written.
|
||||
// we do multiple of 4 words to avoid messing up alignment
|
||||
|
|
@ -829,7 +863,7 @@ static void PicoWrite16_32x_on(u32 a, u32 d)
|
|||
}
|
||||
|
||||
if ((a & 0xfff0) == 0x5180) { // a15180
|
||||
p32x_vdp_write16(a, d, 0); // FIXME?
|
||||
p32x_vdp_write16(a, d, NULL); // FIXME?
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1014,8 +1048,7 @@ static u32 sh2_read8_cs0(u32 a, int id)
|
|||
|
||||
if ((a & 0x3ff00) == 0x4100) {
|
||||
d = p32x_vdp_read16(a);
|
||||
if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(&sh2s[id]), 1))
|
||||
ash2_end_run(&sh2s[id], 8);
|
||||
sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
|
||||
goto out_16to8;
|
||||
}
|
||||
|
||||
|
|
@ -1069,8 +1102,7 @@ static u32 sh2_read16_cs0(u32 a, int id)
|
|||
|
||||
if ((a & 0x3ff00) == 0x4100) {
|
||||
d = p32x_vdp_read16(a);
|
||||
if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(&sh2s[id]), 1))
|
||||
ash2_end_run(&sh2s[id], 8);
|
||||
sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
|
||||
goto out;
|
||||
}
|
||||
|
||||
|
|
@ -1116,6 +1148,7 @@ static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id)
|
|||
id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
|
||||
|
||||
if ((a & 0x3ff00) == 0x4100) {
|
||||
sh2s[id].poll_addr = 0;
|
||||
p32x_vdp_write8(a, d);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1185,8 +1218,8 @@ static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id)
|
|||
id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
|
||||
|
||||
if ((a & 0x3ff00) == 0x4100) {
|
||||
sh2_poll[id].cnt = 0; // for poll before VDP accesses
|
||||
p32x_vdp_write16(a, d, sh2s[id].m68krcycles_done);
|
||||
sh2s[id].poll_addr = 0;
|
||||
p32x_vdp_write16(a, d, &sh2s[id]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1596,14 +1629,6 @@ void PicoMemSetup32x(void)
|
|||
msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
|
||||
msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
|
||||
|
||||
// setup poll detector
|
||||
m68k_poll.flag = P32XF_68KPOLL;
|
||||
m68k_poll.cyc_max = 64;
|
||||
sh2_poll[0].flag = P32XF_MSH2POLL;
|
||||
sh2_poll[0].cyc_max = 21;
|
||||
sh2_poll[1].flag = P32XF_SSH2POLL;
|
||||
sh2_poll[1].cyc_max = 16;
|
||||
|
||||
sh2_drc_mem_setup(&msh2);
|
||||
sh2_drc_mem_setup(&ssh2);
|
||||
}
|
||||
|
|
@ -1615,6 +1640,13 @@ void Pico32xMemStateLoaded(void)
|
|||
memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
|
||||
Pico32x.dirty_pal = 1;
|
||||
|
||||
Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL);
|
||||
memset(&m68k_poll, 0, sizeof(m68k_poll));
|
||||
msh2.state = 0;
|
||||
msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0;
|
||||
ssh2.state = 0;
|
||||
ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0;
|
||||
|
||||
sh2_drc_flush_all();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -86,21 +86,35 @@ void p32x_timers_do(unsigned int cycles)
|
|||
}
|
||||
}
|
||||
|
||||
void p32x_pwm_schedule(unsigned int now)
|
||||
static int p32x_pwm_schedule_(void)
|
||||
{
|
||||
int tm;
|
||||
|
||||
if (Pico32x.emu_flags & P32XF_PWM_PEND)
|
||||
return; // already scheduled
|
||||
return 0; // already scheduled
|
||||
if (Pico32x.sh2irqs & P32XI_PWM)
|
||||
return; // previous not acked
|
||||
return 0; // previous not acked
|
||||
if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 1))
|
||||
return; // masked by everyone
|
||||
return 0; // masked by everyone
|
||||
|
||||
Pico32x.emu_flags |= P32XF_PWM_PEND;
|
||||
tm = (Pico32x.regs[0x30 / 2] & 0x0f00) >> 8;
|
||||
tm = ((tm - 1) & 0x0f) + 1;
|
||||
p32x_event_schedule(P32X_EVENT_PWM, now, pwm_cycles * tm / 3);
|
||||
Pico32x.emu_flags |= P32XF_PWM_PEND;
|
||||
return pwm_cycles * tm / 3;
|
||||
}
|
||||
|
||||
void p32x_pwm_schedule(unsigned int now)
|
||||
{
|
||||
int after = p32x_pwm_schedule_();
|
||||
if (after != 0)
|
||||
p32x_event_schedule(now, P32X_EVENT_PWM, after);
|
||||
}
|
||||
|
||||
void p32x_pwm_schedule_sh2(SH2 *sh2)
|
||||
{
|
||||
int after = p32x_pwm_schedule_();
|
||||
if (after != 0)
|
||||
p32x_event_schedule_sh2(sh2, P32X_EVENT_PWM, after);
|
||||
}
|
||||
|
||||
unsigned int p32x_pwm_read16(unsigned int a)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue