mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-06 15:48:05 -04:00
rework sh2 sync, again..
also some new debug and poll code VF seems to be ok at least..
This commit is contained in:
notaz
parent
51d86e55f6
commit
19886062f1
9 changed files with 507 additions and 169 deletions
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@ -42,13 +42,6 @@
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#include "../memory.h"
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#include "../../cpu/sh2/compiler.h"
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#if 0
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#undef ash2_end_run
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#undef SekEndRun
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#define ash2_end_run(x)
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#define SekEndRun(x)
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#endif
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static const char str_mars[] = "MARS";
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void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
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@ -57,64 +50,96 @@ struct Pico32xMem *Pico32xMem;
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static void bank_switch(int b);
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// poll detection
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#define POLL_THRESHOLD 6
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#define POLL_THRESHOLD 3
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struct poll_det {
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u32 addr, cycles, cyc_max;
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int cnt, flag;
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};
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static struct poll_det m68k_poll, sh2_poll[2];
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static struct {
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u32 addr, cycles;
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int cnt;
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} m68k_poll;
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static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp)
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static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
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{
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int ret = 0, flag = pd->flag;
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int ret = 0;
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if (is_vdp)
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flag <<= 3;
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if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) {
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pd->cnt++;
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if (pd->cnt > POLL_THRESHOLD) {
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if (!(Pico32x.emu_flags & flag)) {
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elprintf(EL_32X, "%s poll addr %08x, cyc %u",
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flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" :
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(flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles);
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if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2
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&& cycles - m68k_poll.cycles <= 64)
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{
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if (m68k_poll.cnt++ > POLL_THRESHOLD) {
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if (!(Pico32x.emu_flags & flags)) {
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elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
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a, cycles - m68k_poll.cycles);
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ret = 1;
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}
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Pico32x.emu_flags |= flag;
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Pico32x.emu_flags |= flags;
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}
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}
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else {
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pd->cnt = 0;
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pd->addr = a;
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m68k_poll.cnt = 0;
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m68k_poll.addr = a;
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}
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pd->cycles = cycles;
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m68k_poll.cycles = cycles;
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return ret;
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}
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static int p32x_poll_undetect(struct poll_det *pd, int is_vdp)
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void p32x_m68k_poll_event(u32 flags)
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{
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int ret = 0, flag = pd->flag;
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if (is_vdp)
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flag <<= 3; // VDP only
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if (Pico32x.emu_flags & flags) {
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elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags,
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Pico32x.emu_flags & ~flags);
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Pico32x.emu_flags &= ~flags;
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SekSetStop(0);
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}
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m68k_poll.addr = m68k_poll.cnt = 0;
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}
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static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags)
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{
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int cycles_left = sh2_cycles_left(sh2);
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if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
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if (sh2->poll_cnt++ > 3) {
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if (!(sh2->state & flags))
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elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m',
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sh2->state, sh2->state | flags);
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sh2->state |= flags;
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sh2_end_run(sh2, 1);
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pevt_log_sh2(sh2, EVT_POLL_START);
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return;
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}
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}
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else
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flag |= flag << 3; // both
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if (Pico32x.emu_flags & flag) {
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elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag);
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ret = 1;
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}
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Pico32x.emu_flags &= ~flag;
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pd->addr = pd->cnt = 0;
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return ret;
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sh2->poll_cnt = 0;
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sh2->poll_addr = a;
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sh2->poll_cycles = cycles_left;
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}
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void p32x_poll_event(int cpu_mask, int is_vdp)
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void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
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{
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if (cpu_mask & 1)
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p32x_poll_undetect(&sh2_poll[0], is_vdp);
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if (cpu_mask & 2)
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p32x_poll_undetect(&sh2_poll[1], is_vdp);
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if (sh2->state & flags) {
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elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m',
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sh2->state, sh2->state & ~flags);
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if (sh2->m68krcycles_done < m68k_cycles)
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sh2->m68krcycles_done = m68k_cycles;
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pevt_log_sh2_o(sh2, EVT_POLL_END);
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}
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sh2->state &= ~flags;
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sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
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}
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static void sh2s_sync_on_read(SH2 *sh2)
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{
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int cycles;
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if (sh2->poll_cnt != 0)
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return;
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cycles = sh2_cycles_done(sh2);
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if (cycles > 600)
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p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3);
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}
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// SH2 faking
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@ -165,8 +190,7 @@ static void dma_68k2sh2_do(void)
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elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen);
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// HACK: assume bus is busy and SH2 is halted
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// XXX: use different mechanism for this, not poll det
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Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL;
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msh2.state |= SH2_STATE_SLEEP;
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for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) {
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elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen);
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@ -182,7 +206,7 @@ static void dma_68k2sh2_do(void)
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Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
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if (dmac0->tcr0 == 0) {
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dmac0->chcr0 |= 2; // DMA has ended normally
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p32x_poll_undetect(&sh2_poll[0], 0);
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p32x_sh2_poll_event(&sh2s[0], SH2_STATE_SLEEP, SekCyclesDoneT());
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}
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}
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@ -211,7 +235,7 @@ static u32 p32x_reg_read16(u32 a)
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p32x_sync_sh2s(cycles);
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if (Pico32x.comm_dirty_sh2 & comreg)
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Pico32x.comm_dirty_sh2 &= ~comreg;
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else if (p32x_poll_detect(&m68k_poll, a, cycles, 0)) {
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else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
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SekSetStop(1);
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SekEndTimeslice(16);
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}
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@ -255,12 +279,12 @@ static void p32x_reg_write8(u32 a, u32 d)
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if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
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p32x_sync_sh2s(SekCyclesDoneT());
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Pico32x.sh2irqi[0] |= P32XI_CMD;
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p32x_update_irls(0);
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p32x_update_irls(NULL);
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}
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if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
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p32x_sync_sh2s(SekCyclesDoneT());
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Pico32x.sh2irqi[1] |= P32XI_CMD;
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p32x_update_irls(0);
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p32x_update_irls(NULL);
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}
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return;
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case 5: // bank
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@ -285,14 +309,14 @@ static void p32x_reg_write8(u32 a, u32 d)
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if (r8[a ^ 1] == d)
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return;
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comreg = 1 << (a & 0x0f) / 2;
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if (Pico32x.comm_dirty_68k & comreg)
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p32x_sync_sh2s(cycles);
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r8[a ^ 1] = d;
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p32x_poll_undetect(&sh2_poll[0], 0);
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p32x_poll_undetect(&sh2_poll[1], 0);
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p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
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p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
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Pico32x.comm_dirty_68k |= comreg;
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if (cycles - (int)msh2.m68krcycles_done > 120)
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@ -351,8 +375,8 @@ static void p32x_reg_write16(u32 a, u32 d)
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p32x_sync_sh2s(cycles);
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r[a / 2] = d;
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p32x_poll_undetect(&sh2_poll[0], 0);
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p32x_poll_undetect(&sh2_poll[1], 0);
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p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
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p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
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Pico32x.comm_dirty_68k |= comreg;
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if (cycles - (int)msh2.m68krcycles_done > 120)
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@ -382,9 +406,6 @@ static void p32x_vdp_write8(u32 a, u32 d)
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u16 *r = Pico32x.vdp_regs;
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a &= 0x0f;
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// for FEN checks between writes
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sh2_poll[0].cnt = 0;
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// TODO: verify what's writeable
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switch (a) {
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case 0x01:
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@ -412,7 +433,7 @@ static void p32x_vdp_write8(u32 a, u32 d)
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}
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}
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static void p32x_vdp_write16(u32 a, u32 d, u32 cycles)
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static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
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{
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a &= 0x0e;
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if (a == 6) { // fill start
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@ -430,9 +451,10 @@ static void p32x_vdp_write16(u32 a, u32 d, u32 cycles)
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}
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Pico32x.vdp_regs[0x06 / 2] = a;
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Pico32x.vdp_regs[0x08 / 2] = d;
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if (cycles > 0) {
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if (sh2 != NULL && len > 4) {
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Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
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p32x_event_schedule(P32X_EVENT_FILLEND, cycles, len);
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// supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles?
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p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len);
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}
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return;
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}
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@ -452,8 +474,8 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
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case 0x00: // adapter/irq ctl
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return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
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case 0x04: // H count (often as comm too)
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if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(&sh2s[cpuid]), 0))
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ash2_end_run(&sh2s[cpuid], 8);
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sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
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sh2s_sync_on_read(&sh2s[cpuid]);
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return Pico32x.sh2_regs[4 / 2];
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case 0x10: // DREQ len
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return r[a / 2];
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@ -467,12 +489,12 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
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int comreg = 1 << (a & 0x0f) / 2;
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if (Pico32x.comm_dirty_68k & comreg)
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Pico32x.comm_dirty_68k &= ~comreg;
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else if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(&sh2s[cpuid]), 0))
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ash2_end_run(&sh2s[cpuid], 8);
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else
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sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
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sh2s_sync_on_read(&sh2s[cpuid]);
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return r[a / 2];
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}
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if ((a & 0x30) == 0x30) {
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sh2_poll[cpuid].cnt = 0;
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return p32x_pwm_read16(a);
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}
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@ -482,22 +504,32 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
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static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
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{
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a &= 0xff;
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sh2s[cpuid].poll_addr = 0;
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switch (a) {
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case 0: // FM
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Pico32x.regs[0] &= ~P32XS_FM;
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Pico32x.regs[0] |= (d << 8) & P32XS_FM;
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return;
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case 1: //
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case 1: // HEN/irq masks
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if ((d ^ Pico32x.sh2_regs[0]) & 0x80)
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elprintf(EL_ANOMALY|EL_32X, "HEN");
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Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
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Pico32x.sh2_regs[0] &= ~0x80;
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Pico32x.sh2_regs[0] |= d & 0x80;
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if (d & 1)
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p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // XXX: timing?
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p32x_update_irls(1);
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p32x_pwm_schedule_sh2(&sh2s[cpuid]);
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p32x_update_irls(&sh2s[cpuid]);
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return;
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case 5: // H count
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Pico32x.sh2_regs[4 / 2] = d & 0xff;
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p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
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d &= 0xff;
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if (Pico32x.sh2_regs[4 / 2] != d) {
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Pico32x.sh2_regs[4 / 2] = d;
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p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
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sh2_cycles_done_m68k(&sh2s[cpuid]));
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sh2_end_run(&sh2s[cpuid], 4);
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}
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return;
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}
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@ -508,9 +540,9 @@ static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
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return;
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r8[a ^ 1] = d;
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if (p32x_poll_undetect(&m68k_poll, 0))
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SekSetStop(0);
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p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
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p32x_m68k_poll_event(P32XF_68KCPOLL);
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p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
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sh2_cycles_done_m68k(&sh2s[cpuid]));
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comreg = 1 << (a & 0x0f) / 2;
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Pico32x.comm_dirty_sh2 |= comreg;
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return;
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@ -521,6 +553,8 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
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{
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a &= 0xfe;
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sh2s[cpuid].poll_addr = 0;
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// comm
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if ((a & 0x30) == 0x20) {
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int comreg;
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@ -528,9 +562,9 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
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return;
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Pico32x.regs[a / 2] = d;
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if (p32x_poll_undetect(&m68k_poll, 0))
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SekSetStop(0);
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p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
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p32x_m68k_poll_event(P32XF_68KCPOLL);
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p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
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sh2_cycles_done_m68k(&sh2s[cpuid]));
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comreg = 1 << (a & 0x0f) / 2;
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Pico32x.comm_dirty_sh2 |= comreg;
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return;
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@ -553,7 +587,7 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
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case 0x1c:
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Pico32x.sh2irqs &= ~P32XI_PWM;
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if (!(Pico32x.emu_flags & P32XF_PWM_PEND))
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p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // timing?
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p32x_pwm_schedule_sh2(&sh2s[cpuid]);
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goto irls;
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}
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@ -561,7 +595,7 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
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return;
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irls:
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p32x_update_irls(1);
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p32x_update_irls(&sh2s[cpuid]);
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}
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// ------------------------------------------------------------------
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@ -693,7 +727,7 @@ static void sh2_peripheral_write32(u32 a, u32 d, int id)
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dmac0->tcr0 &= 0xffffff;
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// HACK: assume 68k starts writing soon and end the timeslice
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ash2_end_run(&sh2s[id], 16);
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||||
sh2_end_run(&sh2s[id], 16);
|
||||
|
||||
// DREQ is only sent after first 4 words are written.
|
||||
// we do multiple of 4 words to avoid messing up alignment
|
||||
|
|
@ -829,7 +863,7 @@ static void PicoWrite16_32x_on(u32 a, u32 d)
|
|||
}
|
||||
|
||||
if ((a & 0xfff0) == 0x5180) { // a15180
|
||||
p32x_vdp_write16(a, d, 0); // FIXME?
|
||||
p32x_vdp_write16(a, d, NULL); // FIXME?
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1014,8 +1048,7 @@ static u32 sh2_read8_cs0(u32 a, int id)
|
|||
|
||||
if ((a & 0x3ff00) == 0x4100) {
|
||||
d = p32x_vdp_read16(a);
|
||||
if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(&sh2s[id]), 1))
|
||||
ash2_end_run(&sh2s[id], 8);
|
||||
sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
|
||||
goto out_16to8;
|
||||
}
|
||||
|
||||
|
|
@ -1069,8 +1102,7 @@ static u32 sh2_read16_cs0(u32 a, int id)
|
|||
|
||||
if ((a & 0x3ff00) == 0x4100) {
|
||||
d = p32x_vdp_read16(a);
|
||||
if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(&sh2s[id]), 1))
|
||||
ash2_end_run(&sh2s[id], 8);
|
||||
sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
|
||||
goto out;
|
||||
}
|
||||
|
||||
|
|
@ -1116,6 +1148,7 @@ static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id)
|
|||
id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
|
||||
|
||||
if ((a & 0x3ff00) == 0x4100) {
|
||||
sh2s[id].poll_addr = 0;
|
||||
p32x_vdp_write8(a, d);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1185,8 +1218,8 @@ static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id)
|
|||
id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
|
||||
|
||||
if ((a & 0x3ff00) == 0x4100) {
|
||||
sh2_poll[id].cnt = 0; // for poll before VDP accesses
|
||||
p32x_vdp_write16(a, d, sh2s[id].m68krcycles_done);
|
||||
sh2s[id].poll_addr = 0;
|
||||
p32x_vdp_write16(a, d, &sh2s[id]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1596,14 +1629,6 @@ void PicoMemSetup32x(void)
|
|||
msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
|
||||
msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
|
||||
|
||||
// setup poll detector
|
||||
m68k_poll.flag = P32XF_68KPOLL;
|
||||
m68k_poll.cyc_max = 64;
|
||||
sh2_poll[0].flag = P32XF_MSH2POLL;
|
||||
sh2_poll[0].cyc_max = 21;
|
||||
sh2_poll[1].flag = P32XF_SSH2POLL;
|
||||
sh2_poll[1].cyc_max = 16;
|
||||
|
||||
sh2_drc_mem_setup(&msh2);
|
||||
sh2_drc_mem_setup(&ssh2);
|
||||
}
|
||||
|
|
@ -1615,6 +1640,13 @@ void Pico32xMemStateLoaded(void)
|
|||
memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
|
||||
Pico32x.dirty_pal = 1;
|
||||
|
||||
Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL);
|
||||
memset(&m68k_poll, 0, sizeof(m68k_poll));
|
||||
msh2.state = 0;
|
||||
msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0;
|
||||
ssh2.state = 0;
|
||||
ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0;
|
||||
|
||||
sh2_drc_flush_all();
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue