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more accuracy fixes

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git-svn-id: file:///home/notaz/opt/svn/PicoDrive@186 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz 2007-07-07 14:54:33 +00:00
parent 2d0b15bb2c
commit 1c88b865ce
5 changed files with 57 additions and 34 deletions
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5
cpu/Cyclone/Cyclone.txt
View file

@ -42,8 +42,9 @@ v0.0087 notaz
- Merged some duplicate handler endings
+ Cyclone now does better job avoiding pipeline interlocks.
+ Replaced incorrect handler of DBT with proper one.
+ Fixed "MOVEA (An)+ An" behaviour.
+ Fixed flags for ROXR and LSR. Hopefully got them right now.
+ Changed "MOVEA (An)+ An" behaviour.
+ Fixed flag behaviour of ROXR, ASL, LSR and NBCD in certain situations.
Hopefully got them right now.
+ Additional functionality added for MAME and other ports (see config.h).
v0.0086 notaz

62
cpu/Cyclone/OpArith.cpp
View file

@ -237,7 +237,7 @@ int OpMul(int op)
EaCalc(10,0x0e00,rea, 2);
EaRead(10, 2,rea, 2,0x0e00);
ot(" movs r0,r0,asl #16\n");
ot(" movs r1,r0,asl #16\n");
if (type==0) // div
{
@ -249,20 +249,25 @@ int OpMul(int op)
if (sign)
{
ot(" mov r11,#0 ;@ r11 = 1 or 2 if the result is negative\n");
ot(" orrmi r11,r11,#1\n");
ot(" mov r0,r0,asr #16\n");
ot(" rsbmi r0,r0,#0 ;@ Make r0 positive\n");
ot("\n");
ot(" tst r2,r2\n");
ot(" orrmi r11,r11,#2\n");
ot(" rsbmi r2,r2,#0 ;@ Make r2 positive\n");
ot("\n");
ot(" movs r0,r1,asr #16\n");
ot(" orrmi r11,r11,#1\n");
ot(" rsbmi r0,r0,#0 ;@ Make r0 positive\n");
ot("\n");
ot(";@ detect the nasty 0x80000000 / -1 situation\n");
ot(" mov r3,r2,asr #31\n");
ot(" eors r3,r3,r1,asr #16\n");
ot(" beq wrendofop%.4x\n",op);
}
else
{
ot(" mov r0,r0,lsr #16 ;@ use only 16 bits of divisor\n");
ot(" mov r0,r1,lsr #16 ;@ use only 16 bits of divisor\n");
}
ot("\n");
ot(";@ Divide r2 by r0\n");
ot(" mov r3,#0\n");
ot(" mov r1,r0\n");
@ -299,6 +304,8 @@ int OpMul(int op)
ot(" cmp r3,r1,asr #16 ;@ signed overflow?\n");
ot(" orrne r9,r9,#0x10000000 ;@ set overflow flag\n");
ot(" bne endofop%.4x ;@ overflow!\n",op);
ot("\n");
ot("wrendofop%.4x%s\n",op,ms?"":":");
}
else
{
@ -306,6 +313,7 @@ int OpMul(int op)
ot(" movs r1,r3,lsr #16 ;@ check for overflow condition\n");
ot(" orrne r9,r9,#0x10000000 ;@ set overflow flag\n");
ot(" bne endofop%.4x ;@ overflow!\n",op);
ot("\n");
}
ot(" mov r1,r3,lsl #16 ;@ Clip to 16-bits\n");
@ -319,7 +327,7 @@ int OpMul(int op)
if (type==1)
{
ot(";@ Get 16-bit signs right:\n");
ot(" mov r0,r0,%s #16\n",sign?"asr":"lsr");
ot(" mov r0,r1,%s #16\n",sign?"asr":"lsr");
ot(" mov r2,r2,lsl #16\n");
ot(" mov r2,r2,%s #16\n",sign?"asr":"lsr");
ot("\n");
@ -486,29 +494,31 @@ int OpNbcd(int op)
ot(" mov r0,r0,asl #24\n");
ot(" and r2,r2,#0x20000000\n");
ot(" add r2,r0,r2,lsr #5 ;@ add X\n");
ot(" rsbs r1,r2,#0x9a000000 ;@ do arithmetic\n");
ot(" rsb r11,r2,#0x9a000000 ;@ do arithmetic\n");
ot(" orrmi r9,r9,#0x80000000 ;@ N\n");
ot(" cmp r1,#0x9a000000\n");
ot(" cmp r11,#0x9a000000\n");
ot(" beq finish%.4x\n",op);
ot("\n");
ot(" mvn r3,r9,lsr #3 ;@ Undefined V behavior\n",op);
ot(" and r2,r1,#0x0f000000\n");
ot(" mvn r3,r11,lsr #31 ;@ Undefined V behavior\n",op);
ot(" and r2,r11,#0x0f000000\n");
ot(" cmp r2,#0x0a000000\n");
ot(" andeq r1,r1,#0xf0000000\n");
ot(" addeq r1,r1,#0x10000000\n");
ot(" and r3,r3,r1,lsr #3 ;@ Undefined V behavior part II\n",op);
ot(" tst r1,r1\n");
ot(" orr r9,r9,r3 ;@ save V\n",op);
ot(" andeq r11,r11,#0xf0000000\n");
ot(" addeq r11,r11,#0x10000000\n");
ot(" and r3,r3,r11,lsr #31 ;@ Undefined V behavior part II\n",op);
ot(" movs r1,r11,asr #24\n");
ot(" bicne r9,r9,#0x40000000 ;@ Z\n");
ot(" orr r9,r9,r3,lsl #28 ;@ save V\n",op);
ot(" orr r9,r9,#0x20000000 ;@ C\n");
ot("\n");
EaWrite(10, 1, ea,0,0x3f,1);
EaWrite(10, 1, ea,0,0x3f,0,0);
ot("finish%.4x%s\n",op,ms?"":":");
ot(" tst r11,r11\n");
ot(" orrmi r9,r9,#0x80000000 ;@ N\n");
ot(" str r9,[r7,#0x4c] ;@ Save X\n");
ot("\n");
OpEnd(ea);
@ -541,9 +551,19 @@ int OpAritha(int op)
if(size==2&&(sea<0x10||sea==0x3c)) Cycles+=2;
if(type==1) Cycles=6;
// to handle suba.w (A0)+, A0 properly, must calc reg EA first
EaCalcReadNoSE(type!=1?10:-1,11,dea,2,0x0e00);
EaCalcReadNoSE(-1,0,sea,size,0x003f);
// EA calculation order defines how situations like suba.w (A0)+, A0 get handled.
// different emus act differently in this situation, I couldn't fugure which is right behaviour.
// This is Musashi's behaviour.
if (type == 1)
{
EaCalcReadNoSE(-1,0,sea,size,0x003f);
EaCalcReadNoSE(type!=1?10:-1,11,dea,2,0x0e00);
}
else
{
EaCalcReadNoSE(type!=1?10:-1,11,dea,2,0x0e00);
EaCalcReadNoSE(-1,0,sea,size,0x003f);
}
if (size<2) ot(" mov r0,r0,asl #%d\n\n",size?16:24);
if (size<2) asr=(char *)(size?",asr #16":",asr #24");

12
cpu/Cyclone/OpBranch.cpp
View file

@ -11,8 +11,7 @@ static void CheckPc(int reg)
ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
ot(" mov r4,r0\n");
#else
if (reg != 4)
ot(" mov r4,r%i\n", reg);
ot(" bic r4,r%d,#1\n",reg); // we do not emulate address errors
#endif
ot("\n");
}
@ -194,7 +193,7 @@ int Op4E70(int op)
case 6: // trapv
OpStart(op,0x10); Cycles=4;
ot(" tst r9,#0x10000000\n");
ot(" subne r5,r5,#%i\n",30);
ot(" subne r5,r5,#%i\n",34);
ot(" movne r0,#0x1c ;@ TRAPV exception\n");
ot(" blne Exception\n");
OpEnd(0x10);
@ -336,6 +335,7 @@ int OpDbra(int op)
ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");
ot(" subeq r5,r5,#4 ;@ additional cycles\n");
ot(" addne r4,r4,r0 ;@ r4 = New PC\n");
ot(" bic r4,r4,#1\n"); // we do not emulate address errors
ot("\n");
#endif
Cycles=12-2;
@ -384,6 +384,7 @@ int OpBranch(int op)
if (offset==0) size=1;
if (offset==-1) size=2;
if (size==2) size=0; // 000 model does not support long displacement
if (size) use=op; // 16-bit or 32-bit
else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches
@ -451,6 +452,8 @@ int OpBranch(int op)
Cycles=18; // always 18
}
ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);
#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8
if (offset!=0 && offset!=-1) checkpc=1;
#endif
@ -462,12 +465,11 @@ int OpBranch(int op)
#endif
if (checkpc)
{
ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);
CheckPc(0);
}
else
{
ot(" add r4,r4,r11%s ;@ r4 = New PC\n",asr_r11);
ot(" bic r4,r0,#1\n"); // we do not emulate address errors
ot("\n");
}

5
cpu/Cyclone/OpLogic.cpp
View file

@ -403,7 +403,7 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
ot("\n");
}
if (type==0 && dir) ot(" mov r3,r0 ;@ save old value for V flag calculation\n");
if (type==0 && dir) ot(" adds r3,r0,#0 ;@ save old value for V flag calculation, also clear V\n");
ot(";@ Shift register:\n");
if (type==0) ot(" movs r0,r0,%s %s\n",dir?"asl":"asr",pct);
@ -434,7 +434,8 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
ot(" mov r1,#0x80000000\n");
ot(" ands r3,r3,r1,asr %s\n", pct);
ot(" cmpne r3,r1,asr %s\n", pct);
ot(" biceq r9,r9,#0x10000000\n");
ot(" eoreq r1,r0,r3\n"); // above check doesn't catch (-1)<<(32+), so we need this
ot(" tsteq r1,#0x80000000\n");
ot(" orrne r9,r9,#0x10000000\n");
ot("\n");
}

7
cpu/Cyclone/tests/test_misc2_gen.c
View file

@ -87,8 +87,6 @@ int main()
{
if ((op&0x00ff) == 0)
write_op(op, 6, 0, 0);
else if ((op&0x00ff) == 0xff)
write_op(op, 0, 6, 0);
}
else if ((op&0xf0f8)==0x50c8) // DBxx
{
@ -96,7 +94,7 @@ int main()
}
else if ((op&0xff80)==0x4e80) // Jsr
{
int addr = 0x300 + i*8 + 8;
int addr = 0x300 + op*8 + 8;
if ((op&0x3f) == 0x39)
write_op(op, addr >> 16, addr & 0xffff, 0);
}
@ -112,7 +110,8 @@ int main()
}
// jump to the beginning
write_op(0x4ef8, 0x300, 0, 0);
write_op(0x4ef8, 0x300, 0x4ef8, 0x300);
write_op(0x4ef8, 0x300, 0x4ef8, 0x300);
fclose(f);
return 0;