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lowercasing filenames, part3
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@576 be3aeb3a-fb24-0410-a615-afba39da0efa
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640
pico/carthw/svp/stub_arm.S
Normal file
640
pico/carthw/svp/stub_arm.S
Normal file
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@ -0,0 +1,640 @@
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@ vim:filetype=armasm
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@ Compiler helper functions and some SVP HLE code
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@ (c) Copyright 2008, Grazvydas "notaz" Ignotas
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@ Free for non-commercial use.
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.if 0
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#include "compiler.h"
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.endif
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.global tcache
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.global ssp_block_table
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.global ssp_block_table_iram
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.global ssp_drc_entry
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.global ssp_drc_next
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.global ssp_drc_next_patch
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.global ssp_drc_end
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.global ssp_hle_800
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.global ssp_hle_902
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.global ssp_hle_07_030
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.global ssp_hle_07_036
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.global ssp_hle_07_6d6
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.global ssp_hle_11_12c
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.global ssp_hle_11_384
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.global ssp_hle_11_38a
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@ translation cache buffer + pointer table
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.data
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.align 12 @ 4096
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@.size tcache, SSP_TCACHE_SIZE
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@.size ssp_block_table, SSP_BLOCKTAB_SIZE
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@.size ssp_block_table_iram, SSP_BLOCKTAB_IRAM_SIZE
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tcache:
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.space SSP_TCACHE_SIZE
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ssp_block_table:
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.space SSP_BLOCKTAB_SIZE
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ssp_block_table_iram:
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.space SSP_BLOCKTAB_IRAM_SIZE
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.space SSP_BLOCKTAB_ALIGN_SIZE
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.text
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.align 2
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@ SSP_GR0, SSP_X, SSP_Y, SSP_A,
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@ SSP_ST, SSP_STACK, SSP_PC, SSP_P,
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@ SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
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@ SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
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@ register map:
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@ r4: XXYY
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@ r5: A
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@ r6: STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
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@ r7: SSP context
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@ r8: r0-r2 (.210)
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@ r9: r4-r6 (.654)
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@ r10: P
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@ r11: cycles
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@ r12: tmp
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#define SSP_OFFS_GR 0x400
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#define SSP_PC 6
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#define SSP_P 7
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#define SSP_PM0 8
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#define SSP_PMC 14
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#define SSP_OFFS_PM_WRITE 0x46c // pmac_write[]
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#define SSP_OFFS_EMUSTAT 0x484 // emu_status
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#define SSP_OFFS_IRAM_ROM 0x48c // ptr_iram_rom
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#define SSP_OFFS_DRAM 0x490 // ptr_dram
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#define SSP_OFFS_IRAM_DIRTY 0x494
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#define SSP_OFFS_IRAM_CTX 0x498 // iram_context
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#define SSP_OFFS_BLTAB 0x49c // block_table
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#define SSP_OFFS_BLTAB_IRAM 0x4a0
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#define SSP_OFFS_TMP0 0x4a4 // for entry PC
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#define SSP_OFFS_TMP1 0x4a8
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#define SSP_OFFS_TMP2 0x4ac
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#define SSP_WAIT_PM0 0x2000
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.macro ssp_drc_do_next patch_jump=0
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.if \patch_jump
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str lr, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
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.endif
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mov r0, r0, lsl #16
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mov r0, r0, lsr #16
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str r0, [r7, #SSP_OFFS_TMP0]
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cmp r0, #0x400
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blt 0f @ ssp_de_iram
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ldr r2, [r7, #SSP_OFFS_BLTAB]
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ldr r2, [r2, r0, lsl #2]
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tst r2, r2
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.if \patch_jump
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bne ssp_drc_do_patch
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.else
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bxne r2
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.endif
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bl ssp_translate_block
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mov r2, r0
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ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
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ldr r1, [r7, #SSP_OFFS_BLTAB]
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str r2, [r1, r0, lsl #2]
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.if \patch_jump
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b ssp_drc_do_patch
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.else
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bx r2
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.endif
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0: @ ssp_de_iram:
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ldr r1, [r7, #SSP_OFFS_IRAM_DIRTY]
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tst r1, r1
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ldreq r1, [r7, #SSP_OFFS_IRAM_CTX]
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beq 1f @ ssp_de_iram_ctx
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bl ssp_get_iram_context
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mov r1, #0
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str r1, [r7, #SSP_OFFS_IRAM_DIRTY]
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mov r1, r0
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str r1, [r7, #SSP_OFFS_IRAM_CTX]
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ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
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1: @ ssp_de_iram_ctx:
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ldr r2, [r7, #SSP_OFFS_BLTAB_IRAM]
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add r2, r2, r1, lsl #12 @ block_tab_iram + iram_context * 0x800/2*4
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add r1, r2, r0, lsl #2
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ldr r2, [r1]
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tst r2, r2
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.if \patch_jump
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bne ssp_drc_do_patch
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.else
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bxne r2
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.endif
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str r1, [r7, #SSP_OFFS_TMP1]
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bl ssp_translate_block
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mov r2, r0
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ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
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ldr r1, [r7, #SSP_OFFS_TMP1] @ &block_table_iram[iram_context][rPC]
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str r2, [r1]
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.if \patch_jump
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b ssp_drc_do_patch
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.else
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bx r2
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.endif
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.endm @ ssp_drc_do_next
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ssp_drc_entry:
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stmfd sp!, {r4-r11, lr}
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mov r11, r0
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ssp_regfile_load:
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ldr r7, =ssp
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ldr r7, [r7]
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add r2, r7, #0x400
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add r2, r2, #4
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ldmia r2, {r3,r4,r5,r6,r8}
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mov r3, r3, lsr #16
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mov r3, r3, lsl #16
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orr r4, r3, r4, lsr #16 @ XXYY
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and r8, r8, #0x0f0000
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mov r8, r8, lsl #13 @ sss0 *
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and r9, r6, #0x670000
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tst r6, #0x80000000
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orrne r8, r8, #0x8
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tst r6, #0x20000000
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orrne r8, r8, #0x4 @ sss0 * NZ..
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orr r6, r8, r9, lsr #12 @ sss0 * .uu. .lll NZ..
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ldr r8, [r7, #0x440] @ r0-r2
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ldr r9, [r7, #0x444] @ r4-r6
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ldr r10,[r7, #(0x400+SSP_P*4)] @ P
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ldr r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
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mov r0, r0, lsr #16
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ssp_drc_next:
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ssp_drc_do_next 0
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ssp_drc_next_patch:
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ssp_drc_do_next 1
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ssp_drc_do_patch:
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ldr r1, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
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subs r12,r2, r1
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moveq r3, #0xe1000000
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orreq r3, r3, #0x00a00000 @ nop
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streq r3, [r1, #-4]
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beq ssp_drc_dp_end
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cmp r12,#4
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ldreq r3, [r1]
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addeq r3, r3, #1
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streq r3, [r1, #-4] @ move the other cond up
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moveq r3, #0xe1000000
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orreq r3, r3, #0x00a00000
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streq r3, [r1] @ fill it's place with nop
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beq ssp_drc_dp_end
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ldr r3, [r1, #-4]
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sub r12,r12,#4
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mov r3, r3, lsr #24
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bic r3, r3, #1 @ L bit
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orr r3, r3, r12,lsl #6
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mov r3, r3, ror #8 @ patched branch instruction
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str r3, [r1, #-4] @ patch the bl/b to jump directly to another handler
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ssp_drc_dp_end:
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str r2, [r7, #SSP_OFFS_TMP1]
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sub r0, r1, #4
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add r1, r1, #4
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bl cache_flush_d_inval_i
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ldr r2, [r7, #SSP_OFFS_TMP1]
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ldr r0, [r7, #SSP_OFFS_TMP0]
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bx r2
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ssp_drc_end:
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mov r0, r0, lsl #16
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str r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
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ssp_regfile_store:
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str r10,[r7, #(0x400+SSP_P*4)] @ P
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str r8, [r7, #0x440] @ r0-r2
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str r9, [r7, #0x444] @ r4-r6
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mov r9, r6, lsr #13
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and r9, r9, #(7<<16) @ STACK
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mov r3, r6, lsl #28
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msr cpsr_flg, r3 @ to to ARM PSR
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and r6, r6, #0x670
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mov r6, r6, lsl #12
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orrmi r6, r6, #0x80000000 @ N
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orreq r6, r6, #0x20000000 @ Z
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mov r3, r4, lsl #16 @ Y
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mov r2, r4, lsr #16
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mov r2, r2, lsl #16 @ X
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add r8, r7, #0x400
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add r8, r8, #4
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stmia r8, {r2,r3,r5,r6,r9}
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mov r0, r11
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ldmfd sp!, {r4-r11, lr}
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bx lr
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@ ld A, PM0
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@ andi 2
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@ bra z=1, gloc_0800
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ssp_hle_800:
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ldr r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
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ldr r1, [r7, #SSP_OFFS_EMUSTAT]
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tst r0, #0x20000
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orreq r1, r1, #SSP_WAIT_PM0
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subeq r11,r11, #1024
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streq r1, [r7, #SSP_OFFS_EMUSTAT]
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mov r0, #0x400
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beq ssp_drc_end
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orrne r0, r0, #0x004
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b ssp_drc_next
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.macro hle_flushflags
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bic r6, r6, #0xf
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mrs r1, cpsr
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orr r6, r6, r1, lsr #28
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.endm
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.macro hle_popstack
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sub r6, r6, #0x20000000
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add r1, r7, #0x400
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add r1, r1, #0x048 @ stack
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add r1, r1, r6, lsr #28
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ldrh r0, [r1]
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.endm
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ssp_hle_902:
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cmp r11, #0
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ble ssp_drc_end
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add r1, r7, #0x200
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ldrh r0, [r1]
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ldr r3, [r7, #SSP_OFFS_IRAM_ROM]
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add r2, r3, r0, lsl #1 @ (r7|00)
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ldrh r0, [r2], #2
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mov r5, r5, lsl #16
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mov r5, r5, lsr #16
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bic r0, r0, #0xfc00
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add r3, r3, r0, lsl #1 @ IRAM dest
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ldrh r12,[r2], #2 @ length
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bic r3, r3, #3 @ always seen aligned
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@ orr r5, r5, #0x08000000
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@ orr r5, r5, #0x00880000
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@ sub r5, r5, r12, lsl #16
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bic r6, r6, #0xf
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add r12,r12,#1
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mov r0, #1
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str r0, [r7, #SSP_OFFS_IRAM_DIRTY]
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sub r11,r11,r12,lsl #1
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sub r11,r11,r12 @ -= length*3
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ssp_hle_902_loop:
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ldrh r0, [r2], #2
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ldrh r1, [r2], #2
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subs r12,r12,#2
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orr r0, r0, r1, lsl #16
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str r0, [r3], #4
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bgt ssp_hle_902_loop
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tst r12, #1
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ldrneh r0, [r2], #2
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strneh r0, [r3], #2
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ldr r0, [r7, #SSP_OFFS_IRAM_ROM]
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add r1, r7, #0x200
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sub r2, r2, r0
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mov r2, r2, lsr #1
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strh r2, [r1] @ (r7|00)
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sub r0, r3, r0
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mov r0, r0, lsr #1
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orr r0, r0, #0x08000000
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orr r0, r0, #0x001c8000
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str r0, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
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str r0, [r7, #(SSP_OFFS_PM_WRITE+4*4)]
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hle_popstack
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subs r11,r11,#16 @ timeslice is likely to end
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ble ssp_drc_end
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b ssp_drc_next
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@ this one is car rendering related
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.macro hle_11_12c_mla offs_in
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ldrsh r5, [r7, #(\offs_in+0)]
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ldrsh r0, [r7, #(\offs_in+2)]
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ldrsh r1, [r7, #(\offs_in+4)]
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mul r5, r2, r5
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ldrsh r12,[r7, #(\offs_in+6)]
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mla r5, r3, r0, r5
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mla r5, r4, r1, r5
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add r5, r5, r12,lsl #11
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movs r5, r5, lsr #13
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add r1, r7, r8, lsr #23
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strh r5, [r1]
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add r8, r8, #(1<<24)
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.endm
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ssp_hle_11_12c:
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cmp r11, #0
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ble ssp_drc_end
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mov r0, #0
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bl ssp_pm_read
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mov r4, r0
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mov r0, #0
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bl ssp_pm_read
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mov r5, r0
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mov r0, #0
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bl ssp_pm_read
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mov r2, r4, lsl #16
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mov r2, r2, asr #15 @ (r7|00) << 1
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mov r3, r5, lsl #16
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mov r3, r3, asr #15 @ (r7|01) << 1
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mov r4, r0, lsl #16
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mov r4, r4, asr #15 @ (r7|10) << 1
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bic r8, r8, #0xff
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mov r8, r8, ror #16
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hle_11_12c_mla 0x20
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hle_11_12c_mla 0x28
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hle_11_12c_mla 0x30
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mov r8, r8, ror #16
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orr r8, r8, #0x1c
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@ hle_flushflags
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hle_popstack
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sub r11,r11,#33
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b ssp_drc_next
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ssp_hle_11_384:
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mov r3, #2
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b ssp_hle_11_38x
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ssp_hle_11_38a:
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mov r3, #3 @ r5
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ssp_hle_11_38x:
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cmp r11, #0
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ble ssp_drc_end
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mov r2, #0 @ EFh, EEh
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mov r1, #1 @ r4
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add r0, r7, #0x1c0 @ r0 (based)
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ssp_hle_11_38x_loop:
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ldrh r5, [r0], #2
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ldr r12,[r7, #0x224]
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mov r5, r5, lsl #16
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eor r5, r5, r5, asr #31
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add r5, r5, r5, lsr #31 @ abs(r5)
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cmp r5, r12,lsl #16
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orrpl r2, r2, r1,lsl #16 @ EFh |= r4
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ldrh r5, [r0, #2]!
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ldr r12,[r7, #0x220]
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cmp r5, r12,lsr #16
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orrpl r2, r2, r1,lsl #16 @ EFh |= r4
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ldr r12,[r7, #0x1e8]
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add r0, r0, #2
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mov r12,r12,lsl #16
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cmp r5, r12,lsr #16
|
||||
orrmi r2, r2, r1
|
||||
|
||||
mov r1, r1, lsl #1
|
||||
subs r3, r3, #1
|
||||
bpl ssp_hle_11_38x_loop
|
||||
|
||||
str r2, [r7, #0x1dc]
|
||||
sub r0, r0, r7
|
||||
bic r8, r8, #0xff
|
||||
orr r8, r8, r0, lsr #1
|
||||
bic r9, r9, #0xff
|
||||
orr r9, r9, r1
|
||||
|
||||
@ hle_flushflags
|
||||
hle_popstack
|
||||
sub r11,r11,#(9+30*4)
|
||||
b ssp_drc_next
|
||||
|
||||
|
||||
ssp_hle_07_6d6:
|
||||
cmp r11, #0
|
||||
ble ssp_drc_end
|
||||
|
||||
ldr r1, [r7, #0x20c]
|
||||
and r0, r8, #0xff @ assuming alignment
|
||||
add r0, r7, r0, lsl #1
|
||||
mov r2, r1, lsr #16
|
||||
mov r1, r1, lsl #16 @ 106h << 16
|
||||
mov r2, r2, lsl #16 @ 107h << 16
|
||||
|
||||
ssp_hle_07_6d6_loop:
|
||||
ldr r5, [r0], #4
|
||||
tst r5, r5
|
||||
bmi ssp_hle_07_6d6_end
|
||||
mov r5, r5, lsl #16
|
||||
cmp r5, r1
|
||||
movmi r1, r5
|
||||
cmp r5, r2
|
||||
sub r11,r11,#16
|
||||
bmi ssp_hle_07_6d6_loop
|
||||
mov r2, r5
|
||||
b ssp_hle_07_6d6_loop
|
||||
|
||||
ssp_hle_07_6d6_end:
|
||||
sub r0, r0, r7
|
||||
mov r0, r0, lsr #1
|
||||
bic r8, r8, #0xff
|
||||
orr r8, r8, r0
|
||||
orr r1, r2, r1, lsr #16
|
||||
str r1, [r7, #0x20c]
|
||||
hle_popstack
|
||||
sub r11,r11,#6
|
||||
b ssp_drc_next
|
||||
|
||||
|
||||
ssp_hle_07_030:
|
||||
ldrh r0, [r7]
|
||||
mov r0, r0, lsl #4
|
||||
orr r0, r0, r0, lsr #16
|
||||
strh r0, [r7]
|
||||
sub r11,r11,#3
|
||||
|
||||
ssp_hle_07_036:
|
||||
ldr r1, [r7, #0x1e0] @ F1h F0h
|
||||
rsb r5, r1, r1, lsr #16
|
||||
mov r5, r5, lsl #16 @ AL not needed
|
||||
cmp r5, #(4<<16)
|
||||
sub r11,r11,#5
|
||||
bmi hle_07_036_ending2
|
||||
ldr r1, [r7, #0x1dc] @ EEh
|
||||
cmp r5, r1, lsl #16
|
||||
sub r11,r11,#5
|
||||
bpl hle_07_036_ret
|
||||
|
||||
mov r0, r5, lsr #16
|
||||
add r1, r7, #0x100
|
||||
strh r0, [r1, #0xea] @ F5h
|
||||
ldr r0, [r7, #0x1e0] @ F0h
|
||||
and r0, r0, #3
|
||||
strh r0, [r1, #0xf0] @ F8h
|
||||
add r2, r0, #0xc0 @ r2
|
||||
add r2, r7, r2, lsl #1
|
||||
ldrh r2, [r2]
|
||||
ldr r0, [r7]
|
||||
mov r1, #4
|
||||
and r0, r0, r2
|
||||
bl ssp_pm_write
|
||||
@ will handle PMC later
|
||||
ldr r0, [r7, #0x1e8] @ F5h << 16
|
||||
ldr r1, [r7, #0x1f0] @ F8h
|
||||
ldr r2, [r7, #0x1d4] @ EAh
|
||||
sub r0, r0, #(3<<16)
|
||||
add r0, r0, r1, lsl #16
|
||||
sub r0, r2, r0, asr #18
|
||||
and r0, r0, #0x7f
|
||||
rsbs r0, r0, #0x78 @ length
|
||||
ble hle_07_036_ending1
|
||||
|
||||
sub r11,r11,r0
|
||||
|
||||
@ copy part
|
||||
ldr r1, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
|
||||
ldr r2, [r7, #SSP_OFFS_DRAM]
|
||||
mov r1, r1, lsl #16
|
||||
add r1, r2, r1, lsr #15 @ addr (based)
|
||||
ldrh r2, [r7, #0] @ pattern
|
||||
ldrh r3, [r7, #6] @ mode
|
||||
|
||||
mov r12, #0x4000
|
||||
orr r12,r12,#0x0018
|
||||
subs r12,r3, r12
|
||||
subnes r12,r12,#0x0400
|
||||
blne tr_unhandled
|
||||
|
||||
orr r2, r2, r2, lsl #16
|
||||
tst r3, #0x400
|
||||
bne hle_07_036_ovrwr
|
||||
|
||||
hle_07_036_no_ovrwr:
|
||||
tst r1, #2
|
||||
strneh r2, [r1], #0x3e @ align
|
||||
subne r0, r0, #1
|
||||
subs r0, r0, #4
|
||||
blt hle_07_036_l2
|
||||
|
||||
hle_07_036_l1:
|
||||
subs r0, r0, #4
|
||||
str r2, [r1], #0x40
|
||||
str r2, [r1], #0x40
|
||||
bge hle_07_036_l1
|
||||
|
||||
hle_07_036_l2:
|
||||
tst r0, #2
|
||||
strne r2, [r1], #0x40
|
||||
tst r0, #1
|
||||
strneh r2, [r1], #2
|
||||
b hle_07_036_end_copy
|
||||
|
||||
hle_07_036_ovrwr:
|
||||
tst r2, #0x000f
|
||||
orreq r12,r12,#0x000f
|
||||
tst r2, #0x00f0
|
||||
orreq r12,r12,#0x00f0
|
||||
tst r2, #0x0f00
|
||||
orreq r12,r12,#0x0f00
|
||||
tst r2, #0xf000
|
||||
orreq r12,r12,#0xf000
|
||||
orrs r12,r12,r12,lsl #16
|
||||
beq hle_07_036_no_ovrwr
|
||||
|
||||
tst r1, #2
|
||||
beq hle_07_036_ol0
|
||||
ldrh r3, [r1]
|
||||
and r3, r3, r12
|
||||
orr r3, r3, r2
|
||||
strh r3, [r1], #0x3e @ align
|
||||
sub r0, r0, #1
|
||||
|
||||
hle_07_036_ol0:
|
||||
subs r0, r0, #2
|
||||
blt hle_07_036_ol2
|
||||
|
||||
hle_07_036_ol1:
|
||||
subs r0, r0, #2
|
||||
ldr r3, [r1]
|
||||
and r3, r3, r12
|
||||
orr r3, r3, r2
|
||||
str r3, [r1], #0x40
|
||||
bge hle_07_036_ol1
|
||||
|
||||
hle_07_036_ol2:
|
||||
tst r0, #1
|
||||
ldrneh r3, [r1]
|
||||
andne r3, r3, r12
|
||||
orrne r3, r3, r2
|
||||
strneh r3, [r1], #2
|
||||
|
||||
hle_07_036_end_copy:
|
||||
ldr r2, [r7, #SSP_OFFS_DRAM]
|
||||
add r3, r7, #0x400
|
||||
sub r0, r1, r2 @ new addr
|
||||
mov r0, r0, lsr #1
|
||||
strh r0, [r3, #(0x6c+4*4)] @ SSP_OFFS_PM_WRITE+4*4 (low)
|
||||
|
||||
hle_07_036_ending1:
|
||||
ldr r0, [r7, #0x1e0] @ F1h << 16
|
||||
add r0, r0, #(1<<16)
|
||||
and r0, r0, #(3<<16)
|
||||
add r0, r0, #(0xc4<<16)
|
||||
bic r8, r8, #0xff0000
|
||||
orr r8, r8, r0 @ r2
|
||||
add r0, r7, r0, lsr #15
|
||||
ldrh r0, [r0]
|
||||
ldr r2, [r7]
|
||||
and r0, r0, r2
|
||||
movs r5, r0, lsl #16
|
||||
|
||||
ldr r1, [r7, #4] @ new mode
|
||||
add r2, r7, #0x400
|
||||
strh r1, [r2, #(0x6c+4*4+2)] @ SSP_OFFS_PM_WRITE+4*4 (high)
|
||||
mov r1, #4
|
||||
bl ssp_pm_write
|
||||
sub r11,r11,#35
|
||||
|
||||
hle_07_036_ret:
|
||||
hle_popstack
|
||||
b ssp_drc_next
|
||||
|
||||
hle_07_036_ending2:
|
||||
sub r11,r11,#3
|
||||
movs r5, r5, lsl #1
|
||||
bmi hle_07_036_ret
|
||||
mov r0, #0x87
|
||||
b ssp_drc_next @ let the dispatcher finish this
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue