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https://github.com/RaySollium99/picodrive.git
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updated EEPROM code, gmv fixed
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@249 be3aeb3a-fb24-0410-a615-afba39da0efa
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notaz
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32826a1a22
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14 changed files with 306 additions and 170 deletions
132
Pico/Misc.c
132
Pico/Misc.c
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@ -131,54 +131,48 @@ const unsigned short vcounts[] = {
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// rarely used EEPROM SRAM code
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// known games which use this:
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// Wonder Boy in Monster World, Megaman - The Wily Wars (X24C01, 128 bytes)
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// NFL Quarterback Club*, Frank Thomas Big Hurt Baseball (X24C04?)
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// College Slam, Blockbuster World Video Game Championship II, NBA Jam (X24C04?)
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// HardBall '95
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// the above sports games use addr 0x200000 for SCL line (handled in Memory.c)
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// (see Genesis Plus for Wii/GC code and docs for info,
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// full game list and better code).
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unsigned int lastSSRamWrite = 0xffff0000;
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// sram_reg: LAtd sela (L=pending SCL, A=pending SDA, t=type(1==uses 0x200000 for SCL and 2K bytes),
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// sram_reg: LAtd sela (L=pending SCL, A=pending SDA, t=(unused),
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// d=SRAM was detected (header or by access), s=started, e=save is EEPROM, l=old SCL, a=old SDA)
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PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)
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{
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unsigned int sreg = Pico.m.sram_reg, saddr = Pico.m.sram_addr, scyc = Pico.m.sram_cycle, ssa = Pico.m.sram_slave;
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unsigned int sreg = Pico.m.sram_reg, saddr = Pico.m.eeprom_addr, scyc = Pico.m.eeprom_cycle, ssa = Pico.m.eeprom_slave;
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//printf("EEPROM write %i\n", d&3);
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sreg |= saddr&0xc000; // we store word count in add reg: dw?a aaaa ... (d=word count detected, w=words(0==use 2 words, else 1))
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elprintf(EL_EEPROM, "eeprom: scl/sda: %i/%i -> %i/%i, newtime=%i", (sreg&2)>>1, sreg&1,
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(d&2)>>1, d&1, SekCyclesDoneT()-lastSSRamWrite);
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saddr&=0x1fff;
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if(sreg & d & 2) {
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// SCL was and is still high..
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if((sreg & 1) && !(d&1)) {
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// ..and SDA went low, means it's a start command, so clear internal addr reg and clock counter
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//dprintf("-start-");
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if(!(sreg&0x8000) && scyc >= 9) {
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if(scyc != 28) sreg |= 0x4000; // 1 word
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//dprintf("detected word count: %i", scyc==28 ? 2 : 1);
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sreg |= 0x8000;
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}
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elprintf(EL_EEPROM, "eeprom: -start-");
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//saddr = 0;
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scyc = 0;
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sreg |= 8;
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} else if(!(sreg & 1) && (d&1)) {
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// SDA went high == stop command
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//dprintf("-stop-");
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elprintf(EL_EEPROM, "eeprom: -stop-");
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sreg &= ~8;
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}
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}
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else if((sreg & 8) && !(sreg & 2) && (d&2)) {
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else if((sreg & 8) && !(sreg & 2) && (d&2))
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{
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// we are started and SCL went high - next cycle
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scyc++; // pre-increment
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if(sreg & 0x20) {
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if(SRam.eeprom_type) {
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// X24C02+
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if((ssa&1) && scyc == 18) {
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scyc = 9;
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saddr++; // next address in read mode
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if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask
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/*if(SRam.eeprom_type==2) saddr&=0xff; else*/ saddr&=0x1fff; // mask
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}
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else if((sreg&0x4000) && scyc == 27) scyc = 18;
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else if(SRam.eeprom_type == 2 && scyc == 27) scyc = 18;
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else if(scyc == 36) scyc = 27;
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} else {
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// X24C01
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@ -187,21 +181,22 @@ PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)
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if(saddr&1) { saddr+=2; saddr&=0xff; } // next addr in read mode
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}
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}
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//dprintf("scyc: %i", scyc);
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elprintf(EL_EEPROM, "eeprom: scyc: %i", scyc);
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}
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else if((sreg & 8) && (sreg & 2) && !(d&2)) {
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else if((sreg & 8) && (sreg & 2) && !(d&2))
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{
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// we are started and SCL went low (falling edge)
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if(sreg & 0x20) {
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if(SRam.eeprom_type) {
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// X24C02+
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if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles
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else if( (!(sreg&0x4000) && scyc > 27) || ((sreg&0x4000) && scyc > 18) ) {
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else if( (SRam.eeprom_type == 3 && scyc > 27) || (SRam.eeprom_type == 2 && scyc > 18) ) {
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if(!(ssa&1)) {
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// data write
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unsigned char *pm=SRam.data+saddr;
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*pm <<= 1; *pm |= d&1;
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if(scyc == 26 || scyc == 35) {
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saddr=(saddr&~0xf)|((saddr+1)&0xf); // only 4 (?) lowest bits are incremented
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//dprintf("w done: %02x; addr inc: %x", *pm, saddr);
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elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr, *pm);
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}
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SRam.changed = 1;
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}
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@ -209,14 +204,17 @@ PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)
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if(!(ssa&1)) {
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// we latch another addr bit
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saddr<<=1;
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if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask
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if(SRam.eeprom_type == 2) saddr&=0xff; else saddr&=0x1fff; // mask
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saddr|=d&1;
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//if(scyc==17||scyc==26) dprintf("addr reg done: %x", saddr);
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if(scyc==17||scyc==26) {
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elprintf(EL_EEPROM, "eeprom: addr reg done: %x", saddr);
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if(scyc==17&&SRam.eeprom_type==2) { saddr&=0xff; saddr|=(ssa<<7)&0x700; } // add device bits too
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}
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}
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} else {
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// slave address
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ssa<<=1; ssa|=d&1;
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//if(scyc==8) dprintf("slave done: %x", ssa);
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if(scyc==8) elprintf(EL_EEPROM, "eeprom: slave done: %x", ssa);
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}
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} else {
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// X24C01
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@ -228,77 +226,89 @@ PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)
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*pm <<= 1; *pm |= d&1;
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if(scyc == 17) {
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saddr=(saddr&0xf9)|((saddr+2)&6); // only 2 lowest bits are incremented
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//dprintf("addr inc: %x", saddr>>1);
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elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr>>1, *pm);
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}
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SRam.changed = 1;
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}
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} else {
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// we latch another addr bit
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saddr<<=1; saddr|=d&1; saddr&=0xff;
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//if(scyc==8) dprintf("addr done: %x", saddr>>1);
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if(scyc==8) elprintf(EL_EEPROM, "eeprom: addr done: %x", saddr>>1);
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}
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}
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}
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sreg &= ~3; sreg |= d&3; // remember SCL and SDA
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Pico.m.sram_reg = (unsigned char) sreg;
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Pico.m.sram_addr = (unsigned short)(saddr|(sreg&0xc000));
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Pico.m.sram_cycle= (unsigned char) scyc;
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Pico.m.sram_slave= (unsigned char) ssa;
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Pico.m.sram_reg = (unsigned char) sreg;
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Pico.m.eeprom_cycle= (unsigned char) scyc;
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Pico.m.eeprom_slave= (unsigned char) ssa;
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Pico.m.eeprom_addr = (unsigned short)saddr;
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}
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PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void)
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{
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unsigned int shift, d=0;
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unsigned int sreg, saddr, scyc, ssa;
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unsigned int shift, d;
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unsigned int sreg, saddr, scyc, ssa, interval;
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// flush last pending write
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SRAMWriteEEPROM(Pico.m.sram_reg>>6);
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sreg = Pico.m.sram_reg; saddr = Pico.m.sram_addr&0x1fff; scyc = Pico.m.sram_cycle; ssa = Pico.m.sram_slave;
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// if(!(sreg & 2) && (sreg&0x80)) scyc++; // take care of raising edge now to compensate lag
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sreg = Pico.m.sram_reg; saddr = Pico.m.eeprom_addr&0x1fff; scyc = Pico.m.eeprom_cycle; ssa = Pico.m.eeprom_slave;
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interval = SekCyclesDoneT()-lastSSRamWrite;
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d = (sreg>>6)&1; // use SDA as "open bus"
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if(SekCyclesDoneT()-lastSSRamWrite < 46) {
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// data was just written, there was no time to respond (used by sports games)
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d = (sreg>>6)&1;
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} else if((sreg & 8) && scyc > 9 && scyc != 18 && scyc != 27) {
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// NBA Jam is nasty enough to read <before> raising the SCL and starting the new cycle.
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// this is probably valid because data changes occur while SCL is low and data can be read
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// before it's actual cycle begins.
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if (!(sreg&0x80) && interval >= 24) {
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elprintf(EL_EEPROM, "eeprom: early read, cycles=%i", interval);
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scyc++;
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}
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if (!(sreg & 8)); // not started, use open bus
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else if (scyc == 9 || scyc == 18 || scyc == 27) {
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elprintf(EL_EEPROM, "eeprom: r ack");
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d = 0;
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} else if (scyc > 9 && scyc < 18) {
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// started and first command word received
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shift = 17-scyc;
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if(sreg & 0x20) {
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if (SRam.eeprom_type) {
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// X24C02+
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if(ssa&1) {
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//dprintf("read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);
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if (ssa&1) {
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elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);
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if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr]);
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d = (SRam.data[saddr]>>shift)&1;
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}
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} else {
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// X24C01
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if(saddr&1) {
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if (saddr&1) {
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elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr>>1, scyc, sreg);
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if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr>>1]);
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d = (SRam.data[saddr>>1]>>shift)&1;
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}
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}
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}
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//else dprintf("r ack");
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return d;
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return (d << SRam.eeprom_bit_out);
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}
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PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d)
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{
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unsigned int sreg = Pico.m.sram_reg;
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unsigned int d1, sreg = Pico.m.sram_reg;
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if(!(a&1)) sreg|=0x20;
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if(sreg&0x20) { // address through 0x200000
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if(!(a&1)) {
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sreg&=~0x80;
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sreg|=d<<7;
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} else {
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sreg&=~0x40;
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sreg|=(d<<6)&0x40;
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}
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} else {
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sreg&=~0xc0;
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sreg|=d<<6;
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if (!((SRam.eeprom_abits^a)&1))
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{
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// SCL
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sreg &= ~0x80;
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d1 = (d >> SRam.eeprom_bit_cl) & 1;
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sreg |= d1<<7;
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}
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if (!(((SRam.eeprom_abits>>1)^a)&1))
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{
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// SDA in
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sreg &= ~0x40;
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d1 = (d >> SRam.eeprom_bit_in) & 1;
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sreg |= d1<<6;
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}
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Pico.m.sram_reg = (unsigned char) sreg;
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