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https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
32x: improve irq handling + few bugfixes
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@866 be3aeb3a-fb24-0410-a615-afba39da0efa
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notaz
parent
04092e329b
commit
1f1ff763e6
10 changed files with 43 additions and 38 deletions
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@ -17,7 +17,6 @@
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* - some constant propagation
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*
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* TODO:
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* - proper SMC handling
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* - better constant propagation
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* - stack caching?
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* - bug fixing
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@ -74,15 +74,6 @@ void sh2_execute(SH2 *sh2_, int cycles)
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{
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UINT32 opcode;
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/* FIXME: Darxide doesn't like this */
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if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
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{
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int level = sh2->pending_level;
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int vector = sh2->irq_callback(sh2, level);
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sh2_do_irq(sh2, level, vector);
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sh2->test_irq = 0;
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}
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if (sh2->delay)
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{
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sh2->ppc = sh2->delay;
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@ -119,6 +110,15 @@ void sh2_execute(SH2 *sh2_, int cycles)
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}
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sh2->icount--;
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if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
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{
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int level = sh2->pending_level;
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int vector = sh2->irq_callback(sh2, level);
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sh2_do_irq(sh2, level, vector);
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sh2->test_irq = 0;
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}
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}
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while (sh2->icount > 0 || sh2->delay); /* can't interrupt before delay */
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@ -54,15 +54,23 @@ void sh2_do_irq(SH2 *sh2, int level, int vector)
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// sh2->icount -= 13;
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}
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void sh2_irl_irq(SH2 *sh2, int level)
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void sh2_irl_irq(SH2 *sh2, int level, int nested_call)
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{
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sh2->pending_irl = level;
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if (level > sh2->pending_int_irq)
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sh2->pending_level = level;
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else
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sh2->pending_level = sh2->pending_int_irq;
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if (level < sh2->pending_int_irq)
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level = sh2->pending_int_irq;
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sh2->pending_level = level;
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sh2->test_irq = 1;
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if (!nested_call) {
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// not in memhandler, so handle this now (recompiler friendly)
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// do this to avoid missing irqs that other SH2 might clear
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if (level > ((sh2->sr >> 4) & 0x0f)) {
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int vector = sh2->irq_callback(sh2, level);
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sh2_do_irq(sh2, level, vector);
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}
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}
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else
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sh2->test_irq = 1;
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}
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void sh2_internal_irq(SH2 *sh2, int level, int vector)
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@ -61,7 +61,7 @@ extern SH2 *sh2; // active sh2. XXX: consider removing
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int sh2_init(SH2 *sh2, int is_slave);
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void sh2_finish(SH2 *sh2);
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void sh2_reset(SH2 *sh2);
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void sh2_irl_irq(SH2 *sh2, int level);
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void sh2_irl_irq(SH2 *sh2, int level, int nested_call);
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void sh2_internal_irq(SH2 *sh2, int level, int vector);
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void sh2_do_irq(SH2 *sh2, int level, int vector);
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@ -19,7 +19,7 @@ static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
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}
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}
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void p32x_update_irls(void)
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void p32x_update_irls(int nested_call)
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{
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int irqs, mlvl = 0, slvl = 0;
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@ -36,8 +36,8 @@ void p32x_update_irls(void)
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slvl *= 2;
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elprintf(EL_32X, "update_irls: m %d, s %d", mlvl, slvl);
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sh2_irl_irq(&msh2, mlvl);
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sh2_irl_irq(&ssh2, slvl);
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sh2_irl_irq(&msh2, mlvl, nested_call);
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sh2_irl_irq(&ssh2, slvl, nested_call);
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mlvl = mlvl ? 1 : 0;
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slvl = slvl ? 1 : 0;
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p32x_poll_event(mlvl | (slvl << 1), 0);
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@ -141,7 +141,7 @@ void PicoReset32x(void)
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{
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if (PicoAHW & PAHW_32X) {
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Pico32x.sh2irqs |= P32XI_VRES;
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p32x_update_irls();
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p32x_update_irls(0);
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p32x_poll_event(3, 0);
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}
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}
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@ -186,7 +186,7 @@ static void p32x_start_blank(void)
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}
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Pico32x.sh2irqs |= P32XI_VINT;
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p32x_update_irls();
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p32x_update_irls(0);
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p32x_poll_event(3, 1);
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}
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@ -224,12 +224,12 @@ static void p32x_reg_write8(u32 a, u32 d)
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case 3: // irq ctl
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if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
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Pico32x.sh2irqi[0] |= P32XI_CMD;
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p32x_update_irls();
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p32x_update_irls(0);
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SekEndRun(16);
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}
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if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
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Pico32x.sh2irqi[1] |= P32XI_CMD;
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p32x_update_irls();
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p32x_update_irls(0);
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SekEndRun(16);
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}
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return;
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@ -431,7 +431,7 @@ static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
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Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
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Pico32x.sh2_regs[0] &= ~0x80;
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Pico32x.sh2_regs[0] |= d & 0x80;
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p32x_update_irls();
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p32x_update_irls(1);
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return;
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case 5: // H count
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Pico32x.sh2_regs[4 / 2] = d & 0xff;
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@ -486,7 +486,7 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
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return;
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irls:
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p32x_update_irls();
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p32x_update_irls(1);
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}
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// ------------------------------------------------------------------
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@ -950,7 +950,7 @@ static u32 sh2_read8_cs0(u32 a, int id)
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if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
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return Pico32xMem->sh2_rom_s[a ^ 1];
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if ((a & 0x3ff00) == 0x4200) {
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if ((a & 0x3fe00) == 0x4200) {
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d = Pico32xMem->pal[(a & 0x1ff) / 2];
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goto out_16to8;
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}
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@ -1004,7 +1004,7 @@ static u32 sh2_read16_cs0(u32 a, int id)
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if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
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return *(u16 *)(Pico32xMem->sh2_rom_s + a);
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if ((a & 0x3ff00) == 0x4200) {
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if ((a & 0x3fe00) == 0x4200) {
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d = Pico32xMem->pal[(a & 0x1ff) / 2];
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goto out;
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}
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@ -47,7 +47,7 @@ void p32x_timers_recalc(void)
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}
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// PWM irq for every tm samples
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void p32x_timers_do(int new_line)
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void p32x_timers_do(int line_call)
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{
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int tm, cnt, i;
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@ -55,17 +55,17 @@ void p32x_timers_do(int new_line)
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{
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tm = (Pico32x.regs[0x30 / 2] & 0x0f00) >> 8;
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if (tm != 0) {
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if (new_line)
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if (line_call)
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Pico32x.pwm_irq_sample_cnt += pwm_line_samples;
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if (Pico32x.pwm_irq_sample_cnt >= (tm << 16)) {
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Pico32x.pwm_irq_sample_cnt -= tm << 16;
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Pico32x.sh2irqs |= P32XI_PWM;
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p32x_update_irls();
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p32x_update_irls(!line_call);
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}
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}
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}
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if (!new_line)
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if (!line_call)
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return;
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for (i = 0; i < 2; i++) {
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@ -192,10 +192,8 @@ int PicoReset(void)
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if (!(PicoOpt & POPT_DIS_IDLE_DET))
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SekInitIdleDet();
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if (PicoOpt & POPT_EN_32X) {
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if (PicoOpt & POPT_EN_32X)
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PicoReset32x();
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return 0;
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}
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// reset sram state; enable sram access by default if it doesn't overlap with ROM
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Pico.m.sram_reg = 0;
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@ -706,7 +706,7 @@ void PicoReset32x(void);
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void Pico32xStartup(void);
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void PicoUnload32x(void);
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void PicoFrame32x(void);
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void p32x_update_irls(void);
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void p32x_update_irls(int nested_call);
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void p32x_reset_sh2s(void);
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// 32x/memory.c
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@ -734,7 +734,7 @@ extern int Pico32xDrawMode;
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unsigned int p32x_pwm_read16(unsigned int a);
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void p32x_pwm_write16(unsigned int a, unsigned int d);
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void p32x_pwm_update(int *buf32, int length, int stereo);
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void p32x_timers_do(int new_line);
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void p32x_timers_do(int line_call);
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void p32x_timers_recalc(void);
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extern int pwm_frame_smp_cnt;
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@ -1,2 +1,2 @@
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#define VERSION "1.70b2"
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#define VERSION "1.70b3"
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