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sh2 drc, several bug fixes

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kub 2024-06-09 22:30:51 +00:00
parent a43c77c0e5
commit 31efd4546e
11 changed files with 51 additions and 40 deletions
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4
cpu/drc/emit_arm.c
View file

@ -1,7 +1,7 @@
/*
* Basic macros to emit ARM instructions and some utils
* Copyright (C) 2008,2009,2010 notaz
* Copyright (C) 2019 kub
* Copyright (C) 2019-2024 kub
*
* This work is licensed under the terms of MAME license.
* See COPYING file in the top-level directory.
@ -1196,7 +1196,7 @@ static inline void emith_pool_adjust(int tcache_offs, int move_offs)
#define emith_jump_at(ptr, target) do { \
u32 *ptr_ = (u32 *)ptr; \
u32 val_ = (u32 *)(target) - (u32 *)(ptr) - 2; \
u32 val_ = (u32 *)(target) - ptr_ - 2; \
EOP_C_B_PTR(ptr_, A_COND_AL, 0, val_ & 0xffffff); \
} while (0)
#define emith_jump_at_size() 4

2
cpu/drc/emit_arm64.c
View file

@ -1,6 +1,6 @@
/*
* Basic macros to emit ARM A64 instructions and some utils
* Copyright (C) 2019 kub
* Copyright (C) 2019-2024 kub
*
* This work is licensed under the terms of MAME license.
* See COPYING file in the top-level directory.

10
cpu/drc/emit_mips.c
View file

@ -1,6 +1,6 @@
/*
* Basic macros to emit MIPS32/MIPS64 Release 1 or 2 instructions and some utils
* Copyright (C) 2019 kub
* Copyright (C) 2019-2024 kub
*
* This work is licensed under the terms of MAME license.
* See COPYING file in the top-level directory.
@ -1671,12 +1671,20 @@ static NOINLINE void host_instructions_updated(void *base, void *end, int force)
asm volatile(
" rdhwr %2, $1;"
" bal 0f;" // needed to allow for jr.hb:
#if _MIPS_SZPTR == 64
"0: daddiu $ra, $ra, 3f-0b;" // set ra to insn after jr.hb
#else
"0: addiu $ra, $ra, 3f-0b;" // set ra to insn after jr.hb
#endif
" beqz %2, 3f;"
"1: synci 0(%0);"
" sltu %3, %0, %1;"
#if _MIPS_SZPTR == 64
" daddu %0, %0, %2;"
#else
" addu %0, %0, %2;"
#endif
" bnez %3, 1b;"
" sync;"

2
cpu/drc/emit_ppc.c
View file

@ -1,6 +1,6 @@
/*
* Basic macros to emit PowerISA 2.03 64 bit instructions and some utils
* Copyright (C) 2020 kub
* Copyright (C) 2020-2024 kub
*
* This work is licensed under the terms of MAME license.
* See COPYING file in the top-level directory.

6
cpu/drc/emit_riscv.c
View file

@ -1,6 +1,6 @@
/*
* Basic macros to emit RISC-V RV64IM instructions and some utils
* Copyright (C) 2019 kub
* Copyright (C) 2019-2024 kub
*
* This work is licensed under the terms of MAME license.
* See COPYING file in the top-level directory.
@ -710,9 +710,9 @@ static void emith_move_imm(int r, uintptr_t imm)
if (lui >> 12) {
EMIT(R5_MOVT_IMM(r, lui));
if (imm & 0xfff)
EMIT(R5_ADD_IMM(r, r, imm));
EMIT(R5_ADDW_IMM(r, r, imm));
} else
EMIT(R5_ADD_IMM(r, Z0, imm));
EMIT(R5_ADDW_IMM(r, Z0, imm));
}
static void emith_move_ptr_imm(int r, uintptr_t imm)

5
cpu/drc/emit_x86.c
View file

@ -1,7 +1,7 @@
/*
* Basic macros to emit x86 instructions and some utils
* Copyright (C) 2008,2009,2010 notaz
* Copyright (C) 2019 kub
* Copyright (C) 2019-2024 kub
*
* This work is licensed under the terms of MAME license.
* See COPYING file in the top-level directory.
@ -1365,7 +1365,8 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
/* overflow if top 17 bits of MACH aren't all 1 or 0 */ \
/* to check: add MACH >> 31 to MACH >> 15. this is 0 if no overflow */ \
emith_asr(rn, mh, 15); \
emith_addf_r_r_r_lsr(rn, rn, mh, 31); \
emith_lsr(rm, mh, 31); \
emith_addf_r_r(rn, rm); \
EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> -ovl */ \
emith_move_r_imm_c(DCOND_NE, ml, 0x00000000); \
emith_move_r_imm_c(DCOND_NE, mh, 0x00008000); \