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https://github.com/RaySollium99/picodrive.git
synced 2025-09-04 23:07:46 -04:00
32x DMA memory copy performance optimisation
This commit is contained in:
kub
parent
8141d75694
commit
346153e08e
5 changed files with 105 additions and 15 deletions
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@ -2261,7 +2261,7 @@ static int emit_get_rom_data(SH2 *sh2, sh2_reg_e r, u32 offs, int size, u32 *val
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if (gconst_get(r, &a)) {
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a += offs;
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// check if rom is memory mapped (not bank switched), and address is in rom
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if (dr_is_rom(a) && p32x_sh2_get_mem_ptr(a, &mask, sh2)) {
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if (dr_is_rom(a) && p32x_sh2_get_mem_ptr(a, &mask, sh2) != (void *)-1) {
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switch (size & MF_SIZEMASK) {
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case 0: *val = (s8)p32x_sh2_read8(a, sh2s); break; // 8
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case 1: *val = (s16)p32x_sh2_read16(a, sh2s); break; // 16
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@ -4896,12 +4896,7 @@ void sh2_drc_flush_all(void)
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void sh2_drc_mem_setup(SH2 *sh2)
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{
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// fill the convenience pointers
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sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s.w : Pico32xMem->sh2_rom_m.w;
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sh2->p_da = sh2->data_array;
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sh2->p_sdram = Pico32xMem->sdram;
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sh2->p_rom = Pico.rom;
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// sh2->p_dram filled in dram bank switching
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// fill the DRC-only convenience pointers
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sh2->p_drcblk_da = Pico32xMem->drcblk_da[!!sh2->is_slave];
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sh2->p_drcblk_ram = Pico32xMem->drcblk_ram;
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}
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@ -1855,17 +1855,15 @@ void *p32x_sh2_get_mem_ptr(u32 a, u32 *mask, SH2 *sh2)
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{
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const sh2_memmap *mm = sh2->read8_map;
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void *ret = (void *)-1;
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u32 am;
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mm += a >> SH2_READ_SHIFT;
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am = a & ((1 << SH2_READ_SHIFT)-1);
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if (!map_flag_set(mm->addr) && !(am & ~mm->mask)) {
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mm += SH2MAP_ADDR2OFFS_R(a);
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if (!map_flag_set(mm->addr)) {
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// directly mapped memory (SDRAM, ROM, data array)
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ret = (void *)(mm->addr << 1);
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*mask = mm->mask;
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} else if ((a & ~0x7ff) == 0) {
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// BIOS, has handler function since it shares its segment with I/O
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ret = sh2->is_slave ? Pico32xMem->sh2_rom_s.w : Pico32xMem->sh2_rom_m.w;
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ret = sh2->p_bios;
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*mask = 0x7ff;
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} else if ((a & 0xc6000000) == 0x02000000) {
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// banked ROM. Return bank address
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@ -1877,6 +1875,75 @@ void *p32x_sh2_get_mem_ptr(u32 a, u32 *mask, SH2 *sh2)
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return ret;
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}
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int p32x_sh2_memcpy(u32 dst, u32 src, int count, int size, SH2 *sh2)
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{
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u32 mask;
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void *ps, *pd;
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int len, i;
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// check if src and dst points to memory (rom/sdram/dram/da)
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if ((pd = p32x_sh2_get_mem_ptr(dst, &mask, sh2)) == (void *)-1)
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return 0;
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if ((ps = p32x_sh2_get_mem_ptr(src, &mask, sh2)) == (void *)-1)
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return 0;
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ps += src & mask;
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len = count * size;
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// DRAM in byte access is always in overwrite mode
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if (pd == sh2->p_dram && size == 1)
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dst |= 0x20000;
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// align dst to halfword
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if (dst & 1) {
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p32x_sh2_write8(dst, *(u8 *)((uptr)ps ^ 1), sh2);
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ps++, dst++, len --;
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}
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// copy data
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if ((uptr)ps & 1) {
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// unaligned, use halfword copy mode to reduce memory bandwidth
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u16 *sp = (u16 *)(ps - 1);
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u16 dl, dh = *sp++;
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for (i = 0; i < (len & ~1); i += 2, dst += 2, sp++) {
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dl = dh, dh = *sp;
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p32x_sh2_write16(dst, (dh >> 8) | (dl << 8), sh2);
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}
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if (len & 1)
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p32x_sh2_write8(dst, dh, sh2);
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} else {
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// dst and src at least halfword aligned
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u16 *sp = (u16 *)ps;
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// align dst to word
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if ((dst & 2) && len >= 2) {
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p32x_sh2_write16(dst, *sp++, sh2);
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dst += 2, len -= 2;
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}
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if ((uptr)sp & 2) {
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// halfword copy, using word writes to reduce memory bandwidth
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u16 dl, dh;
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for (i = 0; i < (len & ~3); i += 4, dst += 4, sp += 2) {
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dl = sp[0], dh = sp[1];
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p32x_sh2_write32(dst, (dl << 16) | dh, sh2);
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}
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} else {
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// word copy
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u32 d;
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for (i = 0; i < (len & ~3); i += 4, dst += 4, sp += 2) {
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d = *(u32 *)sp;
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p32x_sh2_write32(dst, (d << 16) | (d >> 16), sh2);
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}
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}
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if (len & 2) {
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p32x_sh2_write16(dst, *sp++, sh2);
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dst += 2;
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}
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if (len & 1)
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p32x_sh2_write8(dst, *sp >> 8, sh2);
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}
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return count;
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}
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// -----------------------------------------------------------------
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static void z80_md_bank_write_32x(unsigned int a, unsigned char d)
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@ -2107,8 +2174,12 @@ void Pico32xSwapDRAM(int b)
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ssh2_read16_map[0x04/2].addr = ssh2_read16_map[0x24/2].addr =
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ssh2_read32_map[0x04/2].addr = ssh2_read32_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
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msh2.p_dram = ssh2.p_dram = Pico32xMem->dram[b]; // DRC conveniance ptr
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// convenience ptrs
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msh2.p_sdram = ssh2.p_sdram = Pico32xMem->sdram;
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msh2.p_dram = ssh2.p_dram = Pico32xMem->dram[b];
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msh2.p_rom = ssh2.p_rom = Pico.rom;
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msh2.p_bios = Pico32xMem->sh2_rom_m.w; msh2.p_da = msh2.data_array;
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ssh2.p_bios = Pico32xMem->sh2_rom_s.w; ssh2.p_da = ssh2.data_array;
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}
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static void bank_switch_rom_sh2(void)
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@ -129,6 +129,24 @@ static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan)
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chan->sar += size;
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}
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// optimization for copying around memory with SH2 DMA
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static void dmac_memcpy(struct dma_chan *chan, SH2 *sh2)
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{
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u32 size = (chan->chcr >> 10) & 3, up = chan->chcr & (1 << 14);
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int count;
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if (!up || chan->tcr < 4)
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return;
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if (size == 3) size = 2; // 4-word xfer mode still counts in words
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// XXX check TCR being a multiple of 4 in 4-word xfer mode?
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// XXX check alignment of sar/dar, generating a bus error if unaligned?
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count = p32x_sh2_memcpy(chan->dar, chan->sar, chan->tcr, 1 << size, sh2);
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chan->sar += count << size;
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chan->dar += count << size;
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chan->tcr -= count;
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}
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// DMA trigger by SH2 register write
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static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
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{
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@ -139,6 +157,11 @@ static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
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if (chan->chcr & DMA_AR) {
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// auto-request transfer
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sh2->state |= SH2_STATE_SLEEP;
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if ((((chan->chcr >> 12) ^ (chan->chcr >> 14)) & 3) == 0 &&
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(((chan->chcr >> 14) ^ (chan->chcr >> 15)) & 1) == 1) {
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// SM == DM and either DM0 or DM1 are set. check for mem to mem copy
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dmac_memcpy(chan, sh2);
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}
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while ((int)chan->tcr > 0)
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dmac_transfer_one(sh2, chan);
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dmac_transfer_complete(sh2, chan);
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@ -937,6 +937,7 @@ unsigned int REGPARM(3) p32x_sh2_poll_memory16(unsigned int a, unsigned int d, S
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unsigned int REGPARM(3) p32x_sh2_poll_memory32(unsigned int a, unsigned int d, SH2 *sh2);
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void *p32x_sh2_get_mem_ptr(unsigned int a, unsigned int *mask, SH2 *sh2);
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void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);
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int p32x_sh2_memcpy(unsigned int dst, unsigned int src, int count, int size, SH2 *sh2);
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// 32x/draw.c
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void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);
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