mirror of
https://github.com/RaySollium99/picodrive.git
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svp..
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@328 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
4fd5325d62
commit
3554b0a446
1 changed files with 103 additions and 118 deletions
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@ -97,7 +97,11 @@
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* size: 32?
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* desc: Programmable Memory access Control. Set using 2 16bit writes,
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* first address, then mode word. After setting PMAC, PMAR sould
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* be accessed to program it.
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* be blind accessed (ld -, PMx or ld PMx, -) to program it for
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* reading and writing respectively.
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* Reading the register also shifts it's state (from "waiting for
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* address" to "waiting for mode" and back). Reads always return
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* address related to last PMx register accressed.
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*
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* 15. "AL"
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* size: 16
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@ -185,6 +189,8 @@
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#define u32 unsigned int
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//#define USE_DEBUGGER
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// 0
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#define rX ssp->gr[SSP_X].h
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#define rY ssp->gr[SSP_Y].h
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@ -326,9 +332,11 @@
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static ssp1601_t *ssp = NULL;
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static unsigned short *PC;
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static int g_cycles;
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// debug
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#ifdef USE_DEBUGGER
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static int running = 0;
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static int last_iram = 0;
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#endif
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// -----------------------------------------------------
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// register i/o handlers
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@ -336,31 +344,30 @@ static int last_iram = 0;
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// 0-4, 13
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static u32 read_unknown(void)
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{
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elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown read @ %04x", GET_PPC_OFFS());
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elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS());
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return 0;
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}
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static void write_unknown(u32 d)
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{
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elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown write @ %04x", GET_PPC_OFFS());
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elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS());
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}
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// 4
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static void write_ST(u32 d)
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{
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if ((rST ^ d) & 0x0007) elprintf(EL_SVP, "ssp16: RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
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if ((rST ^ d) & 0x0f98) elprintf(EL_SVP, "ssp16: FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
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//if ((rST ^ d) & 0x0007) elprintf(EL_SVP, "ssp RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
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if ((rST ^ d) & 0x0f98) elprintf(EL_SVP, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
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rST = d;
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}
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// 5
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static u32 read_STACK(void)
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{
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//elprintf(EL_SVP, "pop %i @ %04x", rSTACK, GET_PPC_OFFS());
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--rSTACK;
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if ((short)rSTACK < 0) {
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rSTACK = 5;
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elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
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elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
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}
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return ssp->stack[rSTACK];
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}
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@ -368,8 +375,7 @@ static u32 read_STACK(void)
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static void write_STACK(u32 d)
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{
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if (rSTACK >= 6) {
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running = 0;
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elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
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elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
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rSTACK = 0;
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}
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ssp->stack[rSTACK++] = d;
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@ -392,25 +398,23 @@ static u32 read_P(void)
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{
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int m1 = (signed short)rX;
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int m2 = (signed short)rY;
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rP.v = (m1 * m2 * 2); // correct?
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rP.v = (m1 * m2 * 2);
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return rP.h;
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}
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// -----------------------------------------------------
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static void iram_write(int addr, u32 d, int reg, int inc)
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static int get_inc(int mode)
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{
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if ((addr&0xfc00) != 0x8000)
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elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
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elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
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((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
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ssp->pmac_write[reg] += inc<<16;
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int inc = (mode >> 11) & 7;
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if (inc != 0) {
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if (inc != 7) inc--;
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inc = (1<<16) << inc; // 0 1 2 4 8 16 32 128
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if (mode & 0x8000) inc = -inc; // decrement mode
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}
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return inc;
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}
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int lil[32] = { 0, }, lilp = 0;
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static void debug_dump2file(const char *fname, void *mem, int len);
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#define overwite_write(dst, d) \
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{ \
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if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
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@ -425,7 +429,7 @@ static u32 pm_io(int reg, int write, u32 d)
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{
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// this MUST be blind r or w
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if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
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elprintf(EL_SVP|EL_ANOMALY, "FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
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elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
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reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
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ssp->emu_status &= ~SSP_PMC_SET;
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return 0;
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@ -434,109 +438,91 @@ static u32 pm_io(int reg, int write, u32 d)
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ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
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ssp->emu_status &= ~SSP_PMC_SET;
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if ((rPMC.v & 0x7f) == 0x1c && (rPMC.v & 0x7fff0000) == 0) {
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elprintf(EL_SVP, "IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
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/*
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{
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int i;
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char buff[64];
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for (i = 0; i < 32; i++) {
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if (lil[i] == last_iram) break;
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if (lil[i] == 0) {
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lil[i] = last_iram;
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sprintf(buff, "iramrom_%04x.bin", last_iram);
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debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
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break;
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}
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}
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}
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*/
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elprintf(EL_SVP, "ssp IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
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#ifdef USE_DEBUGGER
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last_iram = (ssp->RAM1[0]-1)<<1;
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#endif
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}
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return 0;
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}
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// just in case
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if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
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elprintf(EL_SVP|EL_ANOMALY, "FIXME: PM%i (%c) with only addr set @ %04x",
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elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x",
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reg, write ? 'w' : 'r', GET_PPC_OFFS());
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ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
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}
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// if (ssp->pmac_read[reg] != 0)
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if (reg == 4 || (rST & 0x60))
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{
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#define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
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unsigned short *dram = (unsigned short *)svp->dram;
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if (write)
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{
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/* TODO: 0c18 mode? */
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int mode = ssp->pmac_write[reg]&0xffff;
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int addr = ssp->pmac_write[reg]>>16;
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switch (mode) {
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case 0x0018: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x", reg, CADDR, d);
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dram[addr] = d;
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break;
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case 0x0418: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (overwr)", reg, CADDR, d);
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overwite_write(dram[addr], d);
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break;
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case 0x0818: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc 1)", reg, CADDR, d);
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dram[addr] = d;
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ssp->pmac_write[reg] += 1<<16;
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break;
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case 0x081c: iram_write(addr, d, reg, 1); break; // checked: used by code @ 0902
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case 0x101c: iram_write(addr, d, reg, 2); break; // checked: used by code @ 3b7c
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case 0x4018: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc)", reg, CADDR, d);
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dram[addr] = d;
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ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
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break;
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case 0x4418: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (overwr, cell inc)", reg, CADDR, d);
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overwite_write(dram[addr], d);
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ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
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break;
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default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
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reg, mode, CADDR, d, GET_PPC_OFFS()); break;
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if ((mode & 0xb800) == 0xb800)
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elprintf(EL_SVP, "ssp FIXME: mode %04x", mode);
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if ((mode & 0x43ff) == 0x0018) // DRAM
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{
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int inc = get_inc(mode);
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elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
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reg, CADDR, d, inc >> 16, (mode>>10)&1);
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if (mode & 0x0400) {
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overwite_write(dram[addr], d);
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} else dram[addr] = d;
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ssp->pmac_write[reg] += inc;
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}
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else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
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{
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elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
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reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
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if (mode & 0x0400) {
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overwite_write(dram[addr], d);
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} else dram[addr] = d;
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ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
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}
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else if ((mode & 0x47ff) == 0x001c) // IRAM
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{
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int inc = get_inc(mode);
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if ((addr&0xfc00) != 0x8000)
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elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
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elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc >> 16);
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((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
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ssp->pmac_write[reg] += inc;
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}
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else
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{
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elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
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reg, mode, CADDR, d, GET_PPC_OFFS());
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}
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}
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else
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{
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int mode = ssp->pmac_read[reg]&0xffff;
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int addr = ssp->pmac_read[reg]>>16;
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if ((mode & 0xfff0) == 0x0800) { // ROM, inc 1, verified to be correct
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if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct
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{
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elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
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((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
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ssp->pmac_read[reg] += 1<<16;
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d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
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goto ext_io_end;
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}
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switch (mode) {
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case 0x0018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x", CADDR, dram[addr]);
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d = dram[addr]; // checked
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break;
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case 0x0818: elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc 1)", reg, CADDR, dram[addr]);
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ssp->pmac_read[reg] += 1<<16;
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d = dram[addr];
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break;
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case 0x3018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 32)", CADDR, dram[addr]);
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ssp->pmac_read[reg] += 32<<16;
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d = dram[addr];
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break;
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case 0xa818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 16)", CADDR, dram[addr]);
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ssp->pmac_read[reg] -= 16<<16;
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d = dram[addr];
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break;
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case 0xb818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 128?)", CADDR, dram[addr]);
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ssp->pmac_read[reg] -= 128<<16;
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d = dram[addr];
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break;
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default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled read mode %04x, [%06x] @ %04x",
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reg, mode, CADDR, GET_PPC_OFFS());
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d = 0;
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break;
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else if ((mode & 0x47ff) == 0x0018) // DRAM
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{
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int inc = get_inc(mode);
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elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr], inc >> 16);
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d = dram[addr];
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ssp->pmac_read[reg] += inc;
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}
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else
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{
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elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x",
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reg, mode, CADDR, GET_PPC_OFFS());
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d = 0;
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}
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}
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ext_io_end:
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// PMC value corresponds to last PMR accessed (not sure).
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rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
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@ -656,25 +642,24 @@ static void write_PM4(u32 d)
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// 14
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static u32 read_PMC(void)
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{
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elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.h,
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(ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS());
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if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
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if (ssp->emu_status & SSP_PMC_SET)
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elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
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//if (ssp->emu_status & SSP_PMC_SET)
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// elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
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ssp->emu_status |= SSP_PMC_SET;
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ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
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elprintf(EL_SVP, "PMC r m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
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return rPMC.l;
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} else {
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ssp->emu_status |= SSP_PMC_HAVE_ADDR;
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elprintf(EL_SVP, "PMC r a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
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return rPMC.h;
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}
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return rPMC.h;
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}
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static void write_PMC(u32 d)
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{
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if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
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if (ssp->emu_status & SSP_PMC_SET)
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elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
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//if (ssp->emu_status & SSP_PMC_SET)
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// elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
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ssp->emu_status |= SSP_PMC_SET;
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ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
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rPMC.l = d;
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@ -689,19 +674,15 @@ static void write_PMC(u32 d)
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// 15
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static u32 read_AL(void)
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{
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// TODO: figure out what's up with those blind reads..
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if (*(PC-1) == 0x000f) {
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elprintf(EL_SVP|EL_ANOMALY, "ssp dummy PM assign %08x, ST=%04x @ %04x", rPMC.v, rST, GET_PPC_OFFS());
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elprintf(EL_SVP|EL_ANOMALY, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
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ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
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} else {
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//elprintf(EL_SVP, "ssp AL read, ST=%04x @ %04x", rST, GET_PPC_OFFS());
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}
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return rAL;
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}
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static void write_AL(u32 d)
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{
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//elprintf(EL_SVP, "ssp AL write %04x, ST=%04x @ %04x", d, rST, GET_PPC_OFFS());
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rAL = d;
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}
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@ -900,6 +881,7 @@ void ssp1601_reset(ssp1601_t *l_ssp)
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}
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#ifdef USE_DEBUGGER
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static void debug_dump(void)
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{
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printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
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@ -997,21 +979,23 @@ static void debug(unsigned int pc, unsigned int op)
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}
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}
|
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}
|
||||
#endif // USE_DEBUGGER
|
||||
|
||||
|
||||
void ssp1601_run(int cycles)
|
||||
{
|
||||
SET_PC(rPC);
|
||||
g_cycles = cycles;
|
||||
|
||||
//if (Pico.m.frame_count == 480) running = 0;
|
||||
|
||||
while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
|
||||
{
|
||||
int op;
|
||||
u32 tmpv;
|
||||
|
||||
op = *PC++;
|
||||
#ifdef USE_DEBUGGER
|
||||
debug(GET_PC()-1, op);
|
||||
#endif
|
||||
switch (op >> 9)
|
||||
{
|
||||
// ld d, s
|
||||
|
|
@ -1090,31 +1074,32 @@ void ssp1601_run(int cycles)
|
|||
case 3: rA32 <<= 1; break; // shl
|
||||
case 6: rA32 = -(signed int)rA32; break; // neg
|
||||
case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
|
||||
default: elprintf(EL_SVP, "ssp16: FIXME unhandled mod %i @ %04x", op&7, GET_PPC_OFFS());
|
||||
default: elprintf(EL_SVP, "ssp FIXME: unhandled mod %i @ %04x", op&7, GET_PPC_OFFS());
|
||||
}
|
||||
UPD_ACC_ZN // ?
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
#if 1
|
||||
// mpys?
|
||||
// ???
|
||||
case 0x1b:
|
||||
#if 0
|
||||
// very uncertain about this one. What about b?
|
||||
if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
|
||||
if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
|
||||
read_P(); // update P
|
||||
rA32 -= ssp->gr[SSP_P].v; // maybe only upper word?
|
||||
// UPD_ACC_ZN // I've seen code checking flags after this
|
||||
rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
|
||||
rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
|
||||
break;
|
||||
#endif
|
||||
break;
|
||||
|
||||
// mpya (rj), (ri), b
|
||||
case 0x4b:
|
||||
// dunno if this is correct. What about b?
|
||||
if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
|
||||
if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
|
||||
read_P(); // update P
|
||||
rA32 += ssp->gr[SSP_P].v; // maybe only upper word?
|
||||
rA32 += ssp->gr[SSP_P].v; // confirmed to be 32bit
|
||||
UPD_ACC_ZN // ?
|
||||
rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
|
||||
rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
|
||||
|
|
@ -1123,8 +1108,8 @@ void ssp1601_run(int cycles)
|
|||
// mld (rj), (ri), b
|
||||
case 0x5b:
|
||||
// dunno if this is correct. What about b?
|
||||
if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
|
||||
rA32 = 0; // maybe only upper word?
|
||||
if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
|
||||
rA32 = 0;
|
||||
rST &= 0x0fff; // ?
|
||||
rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
|
||||
rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
|
||||
|
|
@ -1189,7 +1174,7 @@ void ssp1601_run(int cycles)
|
|||
case 0x7c: OP_EORA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
|
||||
|
||||
default:
|
||||
elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
|
||||
elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
|
||||
break;
|
||||
}
|
||||
g_cycles--;
|
||||
|
|
@ -1199,6 +1184,6 @@ void ssp1601_run(int cycles)
|
|||
rPC = GET_PC();
|
||||
|
||||
if (ssp->gr[SSP_GR0].v != 0xffff0000)
|
||||
elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
|
||||
elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue