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https://github.com/RaySollium99/picodrive.git
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sh2 drc, optimize standard division insns (default off, needs more scrutiny)
This commit is contained in:
kub
parent
48302a8a51
commit
368c918050
2 changed files with 331 additions and 12 deletions
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@ -349,6 +349,15 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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} else emith_or_r_r_r(d, s1, s2); \
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} while (0)
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#define emith_eor_r_r_r_lsr(d, s1, s2, lsrimm) do { \
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if (lsrimm) { \
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int tmp_ = rcache_get_tmp(); \
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emith_lsr(tmp_, s2, lsrimm); \
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emith_eor_r_r_r(d, s1, tmp_); \
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rcache_free_tmp(tmp_); \
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} else emith_eor_r_r_r(d, s1, s2); \
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} while (0)
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// _r_r_shift
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#define emith_or_r_r_lsl(d, s, lslimm) \
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emith_or_r_r_r_lsl(d, d, s, lslimm)
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@ -49,6 +49,7 @@
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#define LOOP_DETECTION 1
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#define LOOP_OPTIMIZER 1
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#define T_OPTIMIZER 1
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#define DIV_OPTIMIZER 0
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#define MAX_LITERAL_OFFSET 0x200 // max. MOVA, MOV @(PC) offset
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#define MAX_LOCAL_TARGETS (BLOCK_INSN_LIMIT / 4)
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@ -152,9 +153,18 @@ enum op_types {
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OP_RTE, // RTE instruction
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OP_TRAPA, // TRAPA instruction
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OP_LDC, // LDC instruction
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OP_DIV0, // DIV0[US] instruction
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OP_UNDEFINED,
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};
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struct div {
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u32 state:1; // 0: expect DIV1/ROTCL, 1: expect DIV1
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u32 rn:5, rm:5, ro:5; // rn and rm for DIV1, ro for ROTCL
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u32 div1:8, rotcl:8; // DIV1 count, ROTCL count
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};
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union _div { u32 imm; struct div div; }; // XXX tut-tut type punning...
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#define div(opd) ((union _div *)&((opd)->imm))->div
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// XXX consider trap insns: OP_TRAPA, OP_UNDEFINED?
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#define OP_ISBRANCH(op) ((BITRANGE(OP_BRANCH, OP_BRANCH_RF)| BITMASK1(OP_RTE)) \
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& BITMASK1(op))
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@ -2979,6 +2989,120 @@ static void emit_do_static_regs(int is_write, int tmpr)
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}
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}
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#if DIV_OPTIMIZER
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// divide operation replacement functions, called by compiled code. Only the
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// 32:16 cases and the 64:32 cases described in the SH2 prog man are replaced.
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static uint32_t REGPARM(2) sh2_drc_divu32(uint32_t dv, uint32_t ds)
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{
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if (ds && ds >= dv) {
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// good case: no divide by 0, and no result overflow
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uint32_t quot = dv / (ds>>16), rem = dv - (quot * (ds>>16));
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if (~quot&1) rem -= ds>>16;
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return (uint16_t)quot | ((2*rem + (quot>>31)) << 16);
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} else {
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// bad case: use the sh2 algo to get the right result
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int q = 0, t = 0, s = 16;
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while (s--) {
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uint32_t _ = dv>>31;
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dv = (dv<<1) | t;
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t = _;
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_ = dv;
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if (q) dv += ds, q = dv < _;
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else dv -= ds, q = !(dv < _);
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q ^= t, t = !q;
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}
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return (dv<<1) | t;
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}
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}
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static uint32_t REGPARM(3) sh2_drc_divu64(uint32_t dh, uint32_t *dl, uint32_t ds)
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{
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if (ds > 1 && ds >= dh) {
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// good case: no divide by 0, and no result overflow
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uint64_t dv = *dl | ((uint64_t)dh << 32);
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uint32_t quot = dv / ds, rem = dv - (quot * ds);
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if (~quot&1) rem -= ds;
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*dl = quot;
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return rem;
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} else {
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// bad case: use the sh2 algo to get the right result
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uint64_t dv = *dl | ((uint64_t)dh << 32);
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int q = 0, t = 0, s = 32;
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while (s--) {
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uint64_t _ = dv>>63;
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dv = (dv<<1) | t;
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t = _;
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_ = dv;
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if (q) dv += ((uint64_t)ds << 32), q = dv < _;
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else dv -= ((uint64_t)ds << 32), q = !(dv < _);
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q ^= t, t = !q;
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}
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*dl = (dv<<1) | t;
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return (dv>>32);
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}
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}
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static uint32_t REGPARM(2) sh2_drc_divs32(int32_t dv, int32_t ds)
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{
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uint32_t adv = abs(dv), ads = abs(ds)>>16;
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if (ads > 1 && ads > adv>>16 && (int32_t)ads > 0 && !(uint16_t)ds) {
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// good case: no divide by 0, and no result overflow
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uint32_t quot = adv / ads, rem = adv - (quot * ads);
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int m1 = (rem ? dv^ds : ds) < 0;
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if (rem && dv < 0) rem = (quot&1 ? -rem : +ads-rem);
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else rem = (quot&1 ? +rem : -ads+rem);
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quot = ((dv^ds)<0 ? -quot : +quot) - m1;
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return (uint16_t)quot | ((2*rem + (quot>>31)) << 16);
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} else {
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// bad case: use the sh2 algo to get the right result
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int m = (uint32_t)ds>>31, q = (uint32_t)dv>>31, t = m^q, s = 16;
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while (s--) {
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uint32_t _ = (uint32_t)dv>>31;
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dv = (dv<<1) | t;
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t = _;
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_ = dv;
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if (m^q) dv += ds, q = (uint32_t)dv < _;
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else dv -= ds, q = !((uint32_t)dv < _);
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q ^= m^t, t = !(m^q);
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}
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return (dv<<1) | t;
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}
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}
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static uint32_t REGPARM(3) sh2_drc_divs64(int32_t dh, uint32_t *dl, int32_t ds)
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{
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int64_t _dv = *dl | ((int64_t)dh << 32);
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uint64_t adv = (_dv < 0 ? -_dv : _dv); // llabs isn't in older toolchains
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uint32_t ads = abs(ds);
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if (ads > 1 && ads > adv>>32 && (int64_t)adv > 0) {
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// good case: no divide by 0, and no result overflow
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uint32_t quot = adv / ads, rem = adv - ((uint64_t)quot * ads);
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int m1 = (rem ? dh^ds : ds) < 0;
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if (rem && dh < 0) rem = (quot&1 ? -rem : +ads-rem);
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else rem = (quot&1 ? +rem : -ads+rem);
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quot = ((dh^ds)<0 ? -quot : +quot) - m1;
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*dl = quot;
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return rem;
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} else {
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// bad case: use the sh2 algo to get the right result
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uint64_t dv = *dl | ((uint64_t)dh << 32);
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int m = (uint32_t)ds>>31, q = (uint64_t)dv>>63, t = m^q, s = 32;
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while (s--) {
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int64_t _ = (uint64_t)dv>>63;
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dv = (dv<<1) | t;
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t = _;
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_ = dv;
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if (m^q) dv += ((uint64_t)ds << 32), q = dv < _;
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else dv -= ((uint64_t)ds << 32), q = !(dv < _);
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q ^= m^t, t = !(m^q);
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}
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*dl = (dv<<1) | t;
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return (dv>>32);
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}
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}
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#endif
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// block local link stuff
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struct linkage {
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u32 pc;
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@ -3115,6 +3239,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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u16 *dr_pc_base;
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struct op_data *opd;
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int blkid_main = 0;
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int skip_op = 0;
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int tmp, tmp2;
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int cycles;
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int i, v;
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@ -3486,6 +3611,10 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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#if (DRC_DEBUG & 2)
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insns_compiled++;
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#endif
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if (skip_op > 0) {
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skip_op--;
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continue;
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}
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if (op_flags[i] & OF_DELAY_OP)
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{
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@ -3772,6 +3901,60 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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emith_invalidate_t();
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emith_bic_r_imm(sr, M|Q|T);
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drcf.Mflag = FLG_0;
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#if DIV_OPTIMIZER
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if (div(opd).div1 == 16 && div(opd).ro == div(opd).rn) {
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// divide 32/16
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rcache_get_reg_arg(0, div(opd).rn, NULL);
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rcache_get_reg_arg(1, div(opd).rm, NULL);
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rcache_invalidate_tmp();
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emith_call(sh2_drc_divu32);
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tmp = rcache_get_tmp_ret();
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#if REMAP_REGISTER
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tmp2 = rcache_map_reg(div(opd).rn, tmp);
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#else
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tmp2 = rcache_get_reg(div(opd).rn, RC_GR_WRITE, NULL);
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#endif
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if (tmp != tmp2)
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emith_move_r_r(tmp2, tmp);
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tmp3 = rcache_get_tmp();
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emith_and_r_r_imm(tmp3, tmp2, 1); // Q = !Rn[0]
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emith_eor_r_r_imm(tmp3, tmp3, 1);
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emith_or_r_r_lsl(sr, tmp3, Q_SHIFT);
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rcache_free_tmp(tmp3);
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emith_or_r_r_r_lsr(sr, sr, tmp2, 31); // T = Rn[31]
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skip_op = div(opd).div1 + div(opd).rotcl;
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}
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else if (div(opd).div1 == 32 && div(opd).ro != div(opd).rn) {
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// divide 64/32
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tmp4 = rcache_get_reg(div(opd).ro, RC_GR_READ, NULL);
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emith_ctx_write(tmp4, offsetof(SH2, drc_tmp));
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tmp = rcache_get_tmp_arg(1);
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emith_add_r_r_ptr_imm(tmp, CONTEXT_REG, offsetof(SH2, drc_tmp));
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rcache_get_reg_arg(0, div(opd).rn, NULL);
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rcache_get_reg_arg(2, div(opd).rm, NULL);
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rcache_invalidate_tmp();
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emith_call(sh2_drc_divu64);
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tmp = rcache_get_tmp_ret();
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#if REMAP_REGISTER
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tmp2 = rcache_map_reg(div(opd).rn, tmp);
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#else
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tmp2 = rcache_get_reg(div(opd).rn, RC_GR_WRITE, NULL);
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#endif
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tmp4 = rcache_get_reg(div(opd).ro, RC_GR_WRITE, NULL);
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if (tmp != tmp2)
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emith_move_r_r(tmp2, tmp);
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emith_ctx_read(tmp4, offsetof(SH2, drc_tmp));
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tmp3 = rcache_get_tmp();
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emith_and_r_r_imm(tmp3, tmp4, 1); // Q = !Ro[0]
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emith_eor_r_r_imm(tmp3, tmp3, 1);
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emith_or_r_r_lsl(sr, tmp3, Q_SHIFT);
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rcache_free_tmp(tmp3);
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emith_or_r_r_r_lsr(sr, sr, tmp4, 31); // T = Ro[31]
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skip_op = div(opd).div1 + div(opd).rotcl;
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}
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#endif
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break;
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case 2: // MOVT Rn 0000nnnn00101001
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sr = rcache_get_reg(SHR_SR, RC_GR_READ, NULL);
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@ -3837,11 +4020,74 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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goto end_op;
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case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW, NULL);
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emith_invalidate_t();
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emith_bic_r_imm(sr, M|Q|T);
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drcf.Mflag = FLG_UNKNOWN;
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#if DIV_OPTIMIZER
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if (div(opd).div1 == 16 && div(opd).ro == div(opd).rn) {
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// divide 32/16
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rcache_get_reg_arg(0, div(opd).rn, NULL);
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tmp2 = rcache_get_reg_arg(1, div(opd).rm, NULL);
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tmp3 = rcache_get_tmp();
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emith_lsr(tmp3, tmp2, 31);
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emith_or_r_r_lsl(sr, tmp3, M_SHIFT); // M = Rm[31]
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rcache_invalidate_tmp();
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emith_call(sh2_drc_divs32);
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tmp = rcache_get_tmp_ret();
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#if REMAP_REGISTER
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tmp2 = rcache_map_reg(div(opd).rn, tmp);
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#else
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tmp2 = rcache_get_reg(div(opd).rn, RC_GR_WRITE, NULL);
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#endif
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if (tmp != tmp2)
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emith_move_r_r(tmp2, tmp);
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tmp3 = rcache_get_tmp();
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emith_eor_r_r_r_lsr(tmp3, tmp2, sr, M_SHIFT);
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emith_and_r_r_imm(tmp3, tmp3, 1);
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emith_eor_r_r_imm(tmp3, tmp3, 1);
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emith_or_r_r_lsl(sr, tmp3, Q_SHIFT); // Q = !Rn[0]^M
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rcache_free_tmp(tmp3);
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emith_or_r_r_r_lsr(sr, sr, tmp2, 31); // T = Rn[31]
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skip_op = div(opd).div1 + div(opd).rotcl;
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}
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else if (div(opd).div1 == 32 && div(opd).ro != div(opd).rn) {
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// divide 64/32
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tmp4 = rcache_get_reg(div(opd).ro, RC_GR_READ, NULL);
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emith_ctx_write(tmp4, offsetof(SH2, drc_tmp));
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rcache_get_reg_arg(0, div(opd).rn, NULL);
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tmp2 = rcache_get_reg_arg(2, div(opd).rm, NULL);
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tmp3 = rcache_get_tmp_arg(1);
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emith_lsr(tmp3, tmp2, 31);
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emith_or_r_r_lsl(sr, tmp3, M_SHIFT); // M = Rm[31]
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emith_add_r_r_ptr_imm(tmp3, CONTEXT_REG, offsetof(SH2, drc_tmp));
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rcache_invalidate_tmp();
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emith_call(sh2_drc_divs64);
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tmp = rcache_get_tmp_ret();
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#if REMAP_REGISTER
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tmp2 = rcache_map_reg(div(opd).rn, tmp);
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#else
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tmp2 = rcache_get_reg(div(opd).rn, RC_GR_WRITE, NULL);
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#endif
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tmp4 = rcache_get_reg(div(opd).ro, RC_GR_WRITE, NULL);
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if (tmp != tmp2)
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emith_move_r_r(tmp2, tmp);
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emith_ctx_read(tmp4, offsetof(SH2, drc_tmp));
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tmp3 = rcache_get_tmp();
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emith_eor_r_r_r_lsr(tmp3, tmp4, sr, M_SHIFT);
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emith_and_r_r_imm(tmp3, tmp3, 1);
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emith_eor_r_r_imm(tmp3, tmp3, 1);
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emith_or_r_r_lsl(sr, tmp3, Q_SHIFT); // Q = !Ro[0]^M
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rcache_free_tmp(tmp3);
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emith_or_r_r_r_lsr(sr, sr, tmp4, 31); // T = Ro[31]
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skip_op = div(opd).div1 + div(opd).rotcl;
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} else
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#endif
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{
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tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ, NULL);
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tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ, NULL);
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tmp = rcache_get_tmp();
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emith_invalidate_t();
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emith_bic_r_imm(sr, M|Q|T);
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emith_lsr(tmp, tmp2, 31); // Q = Nn
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emith_or_r_r_lsl(sr, tmp, Q_SHIFT);
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emith_lsr(tmp, tmp3, 31); // M = Nm
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@ -3849,7 +4095,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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emith_eor_r_r_lsr(tmp, tmp2, 31);
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emith_or_r_r(sr, tmp); // T = Q^M
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rcache_free(tmp);
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drcf.Mflag = FLG_UNKNOWN;
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}
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goto end_op;
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case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW, NULL);
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@ -5758,7 +6004,8 @@ u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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struct op_data *opd;
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int next_is_delay = 0;
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int end_block = 0;
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int i, i_end;
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int is_divop;
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int i, i_end, i_div = -1;
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u32 crc = 0;
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// 2nd pass stuff
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int last_btarget; // loop detector
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@ -5790,6 +6037,7 @@ u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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(lowest_literal && lowest_literal <= pc))
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break; // text area collides with data area
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is_divop = 0;
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op = FETCH_OP(pc);
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switch ((op & 0xf000) >> 12)
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{
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@ -5874,8 +6122,12 @@ u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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break;
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case 1: // DIV0U 0000000000011001
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CHECK_UNHANDLED_BITS(0xf00, undefined);
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opd->op = OP_DIV0;
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opd->source = BITMASK1(SHR_SR);
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opd->dest = BITMASK2(SHR_SR, SHR_T);
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div(opd) = (struct div){ .rn=SHR_MEM, .rm=SHR_MEM, .ro=SHR_MEM };
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i_div = i;
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is_divop = 1;
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break;
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case 2: // MOVT Rn 0000nnnn00101001
|
||||
opd->source = BITMASK1(SHR_T);
|
||||
|
|
@ -5975,8 +6227,12 @@ u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
opd->dest = BITMASK2(GET_Rn(), SHR_MEM);
|
||||
break;
|
||||
case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
|
||||
opd->op = OP_DIV0;
|
||||
opd->source = BITMASK3(SHR_SR, GET_Rm(), GET_Rn());
|
||||
opd->dest = BITMASK2(SHR_SR, SHR_T);
|
||||
div(opd) = (struct div){ .rn=GET_Rn(), .rm=GET_Rm(), .ro=SHR_MEM };
|
||||
i_div = i;
|
||||
is_divop = 1;
|
||||
break;
|
||||
case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
|
||||
opd->source = BITMASK2(GET_Rm(), GET_Rn());
|
||||
|
|
@ -6021,6 +6277,19 @@ u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
|
||||
opd->source = BITMASK4(GET_Rm(), GET_Rn(), SHR_SR, SHR_T);
|
||||
opd->dest = BITMASK3(GET_Rn(), SHR_SR, SHR_T);
|
||||
if (i_div >= 0) {
|
||||
// divide operation: all DIV1 operations must use the same reg pair
|
||||
if (div(&ops[i_div]).rn == SHR_MEM)
|
||||
div(&ops[i_div]).rn=GET_Rn(), div(&ops[i_div]).rm=GET_Rm();
|
||||
if (div(&ops[i_div]).rn == GET_Rn() && div(&ops[i_div]).rm == GET_Rm()) {
|
||||
div(&ops[i_div]).div1 += 1;
|
||||
div(&ops[i_div]).state = 0;
|
||||
is_divop = 1;
|
||||
} else {
|
||||
ops[i_div].imm = 0;
|
||||
i_div = -1;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
|
||||
case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
|
||||
|
|
@ -6126,6 +6395,19 @@ u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
opd->dest = BITMASK2(GET_Rn(), SHR_T);
|
||||
break;
|
||||
case 0x24: // ROTCL Rn 0100nnnn00100100
|
||||
if (i_div >= 0) {
|
||||
// divide operation: all ROTCL operations must use the same register
|
||||
if (div(&ops[i_div]).ro == SHR_MEM)
|
||||
div(&ops[i_div]).ro = GET_Rn();
|
||||
if (div(&ops[i_div]).ro == GET_Rn() && !div(&ops[i_div]).state) {
|
||||
div(&ops[i_div]).rotcl += 1;
|
||||
div(&ops[i_div]).state = 1;
|
||||
is_divop = 1;
|
||||
} else {
|
||||
ops[i_div].imm = 0;
|
||||
i_div = -1;
|
||||
}
|
||||
}
|
||||
case 0x25: // ROTCR Rn 0100nnnn00100101
|
||||
opd->source = BITMASK2(GET_Rn(), SHR_T);
|
||||
opd->dest = BITMASK2(GET_Rn(), SHR_T);
|
||||
|
|
@ -6556,7 +6838,8 @@ u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
next_is_delay = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else if (!is_divop && i_div >= 0)
|
||||
i_div = -1; // divide parser stop
|
||||
}
|
||||
end:
|
||||
i_end = i;
|
||||
|
|
@ -6567,6 +6850,8 @@ end:
|
|||
t = T_UNKNOWN;
|
||||
last_btarget = 0;
|
||||
op = 0; // delay/poll insns counter
|
||||
is_divop = 0; // divide op insns counter
|
||||
i_div = -1; // index of current divide op
|
||||
for (i = 0, pc = base_pc; i < i_end; i++, pc += 2) {
|
||||
opd = &ops[i];
|
||||
crc += FETCH_OP(pc);
|
||||
|
|
@ -6599,6 +6884,31 @@ end:
|
|||
}
|
||||
}
|
||||
|
||||
// divide operation verification:
|
||||
// 1. there must not be a branch target inside
|
||||
// 2. nothing is in a delay slot (could only be DIV0)
|
||||
// 2. DIV0/n*(ROTCL+DIV1)/ROTCL:
|
||||
// div.div1 > 0 && div.rotcl == div.div1+1 && div.rn =! div.ro
|
||||
// 3. DIV0/n*DIV1/ROTCL:
|
||||
// div.div1 > 0 && div.rotcl == 1 && div.ro == div.rn
|
||||
if (i_div >= 0) {
|
||||
if (op_flags[i] & OF_BTARGET) { // condition 1
|
||||
ops[i_div].imm = 0;
|
||||
i_div = -1;
|
||||
} else if (--is_divop == 0)
|
||||
i_div = -1;
|
||||
} else if (opd->op == OP_DIV0) {
|
||||
struct div *div = &div(opd);
|
||||
is_divop = div->div1 + div->rotcl;
|
||||
if (op_flags[i] & OF_DELAY_OP) // condition 2
|
||||
opd->imm = 0;
|
||||
else if (! div->div1 || ! ((div->ro == div->rn && div->rotcl == 1) ||
|
||||
(div->ro != div->rn && div->rotcl == div->div1+1)))
|
||||
opd->imm = 0; // condition 3+4
|
||||
else if (is_divop)
|
||||
i_div = i;
|
||||
}
|
||||
|
||||
// literal pool size detection
|
||||
if (opd->op == OP_MOVA && opd->imm >= base_pc)
|
||||
if (lowest_mova == 0 || opd->imm < lowest_mova)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue