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https://github.com/RaySollium99/picodrive.git
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32x: drc: one manual page worth of opcodes implemented (x86 and arm)
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@827 be3aeb3a-fb24-0410-a615-afba39da0efa
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notaz
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80599a42db
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5 changed files with 441 additions and 69 deletions
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@ -28,9 +28,17 @@
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#define A_COND_AL 0xe
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#define A_COND_EQ 0x0
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#define A_COND_NE 0x1
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#define A_COND_HS 0x2
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#define A_COND_LO 0x3
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#define A_COND_MI 0x4
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#define A_COND_PL 0x5
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#define A_COND_VS 0x6
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#define A_COND_VC 0x7
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#define A_COND_HI 0x8
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#define A_COND_LS 0x9
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#define A_COND_GE 0xa
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#define A_COND_LT 0xb
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#define A_COND_GT 0xc
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#define A_COND_LE 0xd
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/* unified conditions */
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@ -38,6 +46,18 @@
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#define DCOND_NE A_COND_NE
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#define DCOND_MI A_COND_MI
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#define DCOND_PL A_COND_PL
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#define DCOND_HI A_COND_HI
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#define DCOND_HS A_COND_HS
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#define DCOND_LO A_COND_LO
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#define DCOND_GE A_COND_GE
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#define DCOND_GT A_COND_GT
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#define DCOND_LT A_COND_LT
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#define DCOND_LS A_COND_LS
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#define DCOND_LE A_COND_LE
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#define DCOND_VS A_COND_VS
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#define DCOND_VC A_COND_VC
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#define DCOND_CS A_COND_HS
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#define DCOND_CC A_COND_LO
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/* addressing mode 1 */
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#define A_AM1_LSL 0
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@ -55,12 +75,15 @@
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#define A_OP_SUB 0x2
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#define A_OP_RSB 0x3
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#define A_OP_ADD 0x4
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#define A_OP_ADC 0x5
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#define A_OP_SBC 0x6
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#define A_OP_TST 0x8
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#define A_OP_TEQ 0x9
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#define A_OP_CMP 0xa
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#define A_OP_ORR 0xc
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#define A_OP_MOV 0xd
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#define A_OP_BIC 0xe
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#define A_OP_MVN 0xf
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#define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
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EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
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@ -71,6 +94,7 @@
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#define EOP_MOV_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
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#define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
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#define EOP_EOR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_EOR,0,rn,rd,ror2,imm8)
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#define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
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#define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
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#define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
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@ -86,7 +110,12 @@
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#define EOP_MOV_REG(cond,s,rd, rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
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#define EOP_ORR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_ADD_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_ADC_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADC,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_SUB_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SUB,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_SBC_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SBC,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_AND_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_AND,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_EOR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_EOR,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_CMP_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_CMP,1,rn, 0,shift_imm,shift_op,rm)
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#define EOP_TST_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
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#define EOP_TEQ_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TEQ,1,rn, 0,shift_imm,shift_op,rm)
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@ -167,6 +196,12 @@
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#define EOP_C_MUL(cond,s,rd,rs,rm) \
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EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm))
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#define EOP_C_UMULL(cond,s,rdhi,rdlo,rs,rm) \
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EMIT(((cond)<<28) | 0x00800000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
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#define EOP_C_SMULL(cond,s,rdhi,rdlo,rs,rm) \
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EMIT(((cond)<<28) | 0x00c00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
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#define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
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#define EOP_C_MRS(cond,rd) \
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@ -249,31 +284,57 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define EMITH_SJMP_END(cond) \
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(void)(cond)
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#define EMITH_CONDITIONAL(code, is_nonzero) { \
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u32 val, cond, *ptr; \
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cond = (is_nonzero) ? A_COND_NE : A_COND_EQ; \
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ptr = (void *)tcache_ptr; \
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tcache_ptr = (void *)(ptr + 1); \
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code; \
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val = (u32 *)tcache_ptr - (ptr + 2); \
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EMIT_PTR(ptr, ((cond)<<28) | 0x0a000000 | (val & 0xffffff)); \
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}
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#define emith_move_r_r(d, s) \
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EOP_MOV_REG_SIMPLE(d, s)
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#define emith_or_r_r_r_lsl(d, s1, s2, lslimm) \
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EOP_ORR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
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#define emith_eor_r_r_r_lsl(d, s1, s2, lslimm) \
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EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
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#define emith_or_r_r_r(d, s1, s2) \
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emith_or_r_r_r_lsl(d, s1, s2, 0)
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#define emith_eor_r_r_r(d, s1, s2) \
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emith_eor_r_r_r_lsl(d, s1, s2, 0)
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#define emith_add_r_r(d, s) \
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EOP_ADD_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
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#define emith_sub_r_r(d, s) \
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EOP_SUB_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
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#define emith_and_r_r(d, s) \
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EOP_AND_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
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#define emith_or_r_r(d, s) \
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emith_or_r_r_r(d, d, s)
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#define emith_eor_r_r(d, s) \
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emith_eor_r_r_r(d, d, s)
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#define emith_tst_r_r(d, s) \
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EOP_TST_REG(A_COND_AL,d,s,A_AM1_LSL,0)
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#define emith_teq_r_r(d, s) \
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EOP_TEQ_REG(A_COND_AL,d,s,A_AM1_LSL,0)
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#define emith_cmp_r_r(d, s) \
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EOP_CMP_REG(A_COND_AL,d,s,A_AM1_LSL,0)
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#define emith_addf_r_r(d, s) \
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EOP_ADD_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
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#define emith_subf_r_r(d, s) \
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EOP_SUB_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
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#define emith_adcf_r_r(d, s) \
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EOP_ADC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
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#define emith_sbcf_r_r(d, s) \
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EOP_SBC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
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#define emith_move_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_MOV, r, imm)
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@ -305,12 +366,18 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_or_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_ORR, r, imm)
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#define emith_bic_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_BIC, r, imm)
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#define emith_lsl(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSL,cnt)
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#define emith_lsr(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSR,cnt)
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#define emith_lslf(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSL,cnt)
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#define emith_asrf(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ASR,cnt)
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@ -321,6 +388,13 @@ static int emith_xbranch(int cond, void *target, int is_call)
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EOP_MUL(d, s2, s1); \
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}
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#define emith_mul_u64(dlo, dhi, s1, s2) \
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EOP_C_UMULL(A_COND_AL,0,dhi,dlo,s1,s2)
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#define emith_mul_s64(dlo, dhi, s1, s2) \
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EOP_C_SMULL(A_COND_AL,0,dhi,dlo,s1,s2)
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// misc
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#define emith_ctx_read(r, offs) \
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EOP_LDR_IMM(r, CONTEXT_REG, offs)
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@ -348,6 +422,18 @@ static int emith_xbranch(int cond, void *target, int is_call)
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EOP_MOV_REG_ASR(d,d,32 - (bits)); \
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}
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// put bit0 of r0 to carry
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#define emith_set_carry(r0) \
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EOP_TST_REG(A_COND_AL,r0,r0,A_AM1_LSR,1) /* shift out to carry */ \
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// put bit0 of r0 to carry (for subtraction, inverted on ARM)
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#define emith_set_carry_sub(r0) { \
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int t = rcache_get_tmp(); \
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EOP_EOR_IMM(t,r0,0,1); /* invert */ \
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EOP_MOV_REG(A_COND_AL,1,t,t,A_AM1_LSR,1); /* shift out to carry */ \
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rcache_free_tmp(t); \
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}
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#define host_arg2reg(rd, arg) \
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rd = arg
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