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sh2 drc, fix mul/add saturation

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kub 2024-06-02 07:48:15 +00:00
parent 68e50296e6
commit 38fd3bd866
6 changed files with 78 additions and 78 deletions
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24
cpu/drc/emit_riscv.c
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@ -1494,7 +1494,7 @@ static int emith_cond_check(int cond, int *r, int *s)
EMITH_JMP_START(DCOND_LE); \
/* turns = sr.cycles / cycles */ \
emith_asr(t2, sr, 12); \
emith_move_r_imm(t3, (u32)((1ULL<<32) / (cycles)) + 1); \
emith_move_r_imm(t3, (u32)((1ULL<<32) / (cycles))); \
emith_mul_u64(t1, t2, t2, t3); /* multiply by 1/x */ \
rcache_free_tmp(t3); \
if (reg >= 0) { \
@ -1564,13 +1564,13 @@ static int emith_cond_check(int cond, int *r, int *s)
emith_asr(rn, mh, 15); \
emith_add_r_r_r_lsr(rn, rn, mh, 31); /* sum = (MACH>>31)+(MACH>>15) */ \
emith_teq_r_r(rn, Z0); /* (need only N and Z flags) */ \
EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> ov */ \
emith_move_r_imm_c(DCOND_NE, ml, 0x0000); /* -overflow */ \
emith_move_r_imm_c(DCOND_NE, mh, 0x8000); \
EMITH_SJMP_START(DCOND_PL); /* sum > 0 -> +ovl */ \
emith_sub_r_imm_c(DCOND_MI, ml, 1); /* 0xffffffff */ \
emith_sub_r_imm_c(DCOND_MI, mh, 1); /* 0x00007fff */ \
EMITH_SJMP_END(DCOND_PL); \
EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> -ovl */ \
emith_move_r_imm_c(DCOND_NE, ml, 0x00000000); \
emith_move_r_imm_c(DCOND_NE, mh, 0x00008000); \
EMITH_SJMP_START(DCOND_MI); /* sum > 0 -> +ovl */ \
emith_sub_r_imm_c(DCOND_PL, ml, 1); /* 0xffffffff */ \
emith_sub_r_imm_c(DCOND_PL, mh, 1); /* 0x00007fff */ \
EMITH_SJMP_END(DCOND_MI); \
EMITH_SJMP_END(DCOND_EQ); \
EMITH_SJMP_END(DCOND_EQ); \
} while (0)
@ -1593,10 +1593,10 @@ static int emith_cond_check(int cond, int *r, int *s)
EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> overflow */ \
/* XXX: LSB signalling only in SH1, or in SH2 too? */ \
emith_move_r_imm_c(DCOND_NE, mh, 0x00000001); /* LSB of MACH */ \
emith_move_r_imm_c(DCOND_NE, ml, 0x80000000); /* negative ovrfl */ \
EMITH_SJMP_START(DCOND_PL); /* sum > 0 -> positive ovrfl */ \
emith_sub_r_imm_c(DCOND_MI, ml, 1); /* 0x7fffffff */ \
EMITH_SJMP_END(DCOND_PL); \
emith_move_r_imm_c(DCOND_NE, ml, 0x80000000); /* -ovrfl */ \
EMITH_SJMP_START(DCOND_MI); /* sum > 0 -> +ovrfl */ \
emith_sub_r_imm_c(DCOND_PL, ml, 1); /* 0x7fffffff */ \
EMITH_SJMP_END(DCOND_MI); \
EMITH_SJMP_END(DCOND_EQ); \
EMITH_SJMP_END(DCOND_EQ); \
} while (0)