mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
sh2 drc, add detection for in-memory polling
This commit is contained in:
kub
parent
213b7f42c1
commit
397ccdc6cf
9 changed files with 224 additions and 113 deletions
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@ -12,7 +12,7 @@
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struct Pico32x Pico32x;
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SH2 sh2s[2];
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#define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_SLEEP)
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#define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_RPOLL|SH2_STATE_SLEEP)
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static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
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{
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@ -61,29 +61,37 @@ static void (*m68k_write16_io)(u32 a, u32 d);
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#define POLL_THRESHOLD 3
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static struct {
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u32 addr, cycles;
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u32 addr1, addr2, cycles;
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int cnt;
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} m68k_poll;
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static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
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{
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int ret = 0;
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// support polling on 2 addresses - seen in Wolfenstein
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int match = (a - m68k_poll.addr1 <= 2 || a - m68k_poll.addr2 <= 2);
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if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2
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&& cycles - m68k_poll.cycles <= 64 && !SekNotPolling)
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if (match && cycles - m68k_poll.cycles <= 64 && !SekNotPolling)
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{
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if (m68k_poll.cnt++ > POLL_THRESHOLD) {
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// detect split 32bit access by same cycle count, and ignore those
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if (cycles != m68k_poll.cycles && m68k_poll.cnt++ > POLL_THRESHOLD) {
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if (!(Pico32x.emu_flags & flags)) {
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elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
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a, cycles - m68k_poll.cycles);
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ret = 1;
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}
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Pico32x.emu_flags |= flags;
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ret = 1;
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}
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}
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else {
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// reset poll state in case of restart by interrupt
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Pico32x.emu_flags &= ~(P32XF_68KCPOLL|P32XF_68KVPOLL);
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SekSetStop(0);
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m68k_poll.cnt = 0;
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m68k_poll.addr = a;
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if (!match) {
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m68k_poll.addr2 = m68k_poll.addr1;
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m68k_poll.addr1 = a;
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}
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SekNotPolling = 0;
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}
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m68k_poll.cycles = cycles;
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@ -99,15 +107,15 @@ void p32x_m68k_poll_event(u32 flags)
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Pico32x.emu_flags &= ~flags;
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SekSetStop(0);
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}
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m68k_poll.addr = m68k_poll.cnt = 0;
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m68k_poll.addr1 = m68k_poll.addr2 = m68k_poll.cnt = 0;
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}
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static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags, int maxcnt)
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static void NOINLINE sh2_poll_detect(u32 a, SH2 *sh2, u32 flags, int maxcnt)
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{
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int cycles_left = sh2_cycles_left(sh2);
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u32 cycles_done = sh2_cycles_done_t(sh2);
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if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
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if (sh2->poll_cnt++ > maxcnt) {
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if (a - sh2->poll_addr <= 2 && CYCLES_GE(sh2->poll_cycles+20, cycles_done)) {
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if (sh2->poll_cycles != cycles_done && ++sh2->poll_cnt >= maxcnt) {
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if (!(sh2->state & flags))
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elprintf_sh2(sh2, EL_32X, "state: %02x->%02x",
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sh2->state, sh2->state | flags);
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@ -115,16 +123,22 @@ static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags, int maxcnt)
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sh2->state |= flags;
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sh2_end_run(sh2, 1);
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pevt_log_sh2(sh2, EVT_POLL_START);
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return;
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#ifdef DRC_SH2
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if ((a & 0xc6000000) == 0x06000000) {
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unsigned char *p = sh2->p_drcblk_ram;
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p[(a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT] |= 0x80;
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}
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#endif
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}
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}
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else
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else if (!(sh2->state & (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_RPOLL))) {
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sh2->poll_cnt = 0;
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sh2->poll_addr = a;
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sh2->poll_cycles = cycles_left;
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sh2->poll_addr = a;
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}
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sh2->poll_cycles = cycles_done;
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}
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void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
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void NOINLINE p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
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{
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if (sh2->state & flags) {
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elprintf_sh2(sh2, EL_32X, "state: %02x->%02x", sh2->state,
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@ -134,10 +148,17 @@ void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
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sh2->m68krcycles_done = m68k_cycles;
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pevt_log_sh2_o(sh2, EVT_POLL_END);
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sh2->state &= ~flags;
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#ifdef DRC_SH2
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if ((sh2->poll_addr & 0xc6000000) == 0x06000000) {
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unsigned char *p = sh2->p_drcblk_ram;
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p[(sh2->poll_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT] &= ~0x80;
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}
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#endif
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}
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sh2->state &= ~flags;
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sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
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if (!(sh2->state & (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_RPOLL)))
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sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
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}
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static void sh2s_sync_on_read(SH2 *sh2)
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@ -151,6 +172,14 @@ static void sh2s_sync_on_read(SH2 *sh2)
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p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + C_SH2_TO_M68K(sh2, cycles));
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}
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void p32x_sh2_poll_memory(unsigned int a, SH2 *sh2)
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{
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DRC_SAVE_SR(sh2);
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sh2_poll_detect(a, sh2, SH2_STATE_RPOLL, 5);
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sh2s_sync_on_read(sh2);
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DRC_RESTORE_SR(sh2);
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}
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// SH2 faking
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//#define FAKE_SH2
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#ifdef FAKE_SH2
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@ -567,7 +596,7 @@ static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
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return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0]
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| Pico32x.sh2irq_mask[sh2->is_slave];
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case 0x04: // H count (often as comm too)
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sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
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sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 7);
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sh2s_sync_on_read(sh2);
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return Pico32x.sh2_regs[4 / 2];
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case 0x06:
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@ -596,7 +625,7 @@ static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
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// comm port
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if ((a & 0x30) == 0x20) {
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sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
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sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 7);
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sh2s_sync_on_read(sh2);
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return r[a / 2];
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}
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@ -614,7 +643,7 @@ static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
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u32 old;
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a &= 0x3f;
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sh2->poll_addr = 0;
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sh2->poll_cnt = 0;
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switch (a) {
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case 0x00: // FM
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@ -695,6 +724,7 @@ static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
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return;
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REG8IN16(r, a) = d;
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sh2_end_run(sh2, 1);
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p32x_m68k_poll_event(P32XF_68KCPOLL);
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p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
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sh2_cycles_done_m68k(sh2));
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@ -711,7 +741,7 @@ static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
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{
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a &= 0x3e;
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sh2->poll_addr = 0;
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sh2->poll_cnt = 0;
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// comm
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if ((a & 0x30) == 0x20) {
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@ -720,6 +750,7 @@ static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
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return;
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Pico32x.regs[a / 2] = d;
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sh2_end_run(sh2, 1);
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p32x_m68k_poll_event(P32XF_68KCPOLL);
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p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
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sh2_cycles_done_m68k(sh2));
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@ -1251,7 +1282,7 @@ static u32 REGPARM(2) sh2_read8_cs0(u32 a, SH2 *sh2)
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if ((a & 0x3fff0) == 0x4100) {
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d = p32x_vdp_read16(a);
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sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
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sh2_poll_detect(a, sh2, SH2_STATE_VPOLL, 9);
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goto out_16to8;
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}
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@ -1319,7 +1350,7 @@ static u32 REGPARM(2) sh2_read16_cs0(u32 a, SH2 *sh2)
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if ((a & 0x3fff0) == 0x4100) {
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d = p32x_vdp_read16(a);
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sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
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sh2_poll_detect(a, sh2, SH2_STATE_VPOLL, 9);
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goto out;
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}
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@ -1383,6 +1414,28 @@ static u32 REGPARM(2) sh2_read32_rom(u32 a, SH2 *sh2)
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}
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// writes
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#ifdef DRC_SH2
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void NOINLINE sh2_sdram_checks(u32 a, int t, SH2 *sh2)
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{
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int v = t & ~0x80;
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if (v)
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sh2_drc_wcheck_ram(a, v, sh2);
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if (t & 0x80) {
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DRC_SAVE_SR(sh2);
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sh2_end_run(sh2, 1);
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p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_RPOLL, sh2_cycles_done_m68k(sh2));
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DRC_RESTORE_SR(sh2);
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}
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}
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void inline sh2_da_checks(u32 a, int t, SH2 *sh2)
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{
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if (t)
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sh2_drc_wcheck_da(a, t, sh2);
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}
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#endif
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static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2)
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{
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}
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@ -1402,7 +1455,7 @@ static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
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if (Pico32x.regs[0] & P32XS_FM) {
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if ((a & 0x3fff0) == 0x4100) {
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sh2->poll_addr = 0;
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sh2->poll_cnt = 0;
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p32x_vdp_write8(a, d);
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goto out;
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}
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@ -1431,38 +1484,26 @@ static void REGPARM(3) sh2_write8_dram(u32 a, u32 d, SH2 *sh2)
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static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0x3ffff;
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u32 a1 = (a & 0x3ffff) ^ 1;
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((u8 *)sh2->p_sdram)[a1] = d;
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#ifdef DRC_SH2
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u8 *p = sh2->p_drcblk_ram;
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int t = p[a1 >> SH2_DRCBLK_RAM_SHIFT];
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if (t)
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sh2_drc_wcheck_ram(a, t, sh2);
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sh2_sdram_checks(a, t, sh2);
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#endif
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((u8 *)sh2->p_sdram)[a1 ^ 1] = d;
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}
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static void REGPARM(3) sh2_write8_sdram_wt(u32 a, u32 d, SH2 *sh2)
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{
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// xmen sync hack..
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if (a < 0x26000200) {
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DRC_SAVE_SR(sh2);
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sh2_end_run(sh2, 32);
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DRC_RESTORE_SR(sh2);
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}
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sh2_write8_sdram(a, d, sh2);
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}
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static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0xfff;
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u32 a1 = (a & 0xfff) ^ 1;
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sh2->data_array[a1] = d;
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#ifdef DRC_SH2
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u8 *p = sh2->p_drcblk_da;
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int t = p[a1 >> SH2_DRCBLK_DA_SHIFT];
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if (t)
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sh2_drc_wcheck_da(a, t, sh2);
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sh2_da_checks(a, t, sh2);
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#endif
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sh2->data_array[a1 ^ 1] = d;
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}
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// write16
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@ -1481,7 +1522,7 @@ static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2)
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if (Pico32x.regs[0] & P32XS_FM) {
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if ((a & 0x3fff0) == 0x4100) {
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sh2->poll_addr = 0;
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sh2->poll_cnt = 0;
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p32x_vdp_write16(a, d, sh2);
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goto out;
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}
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@ -1511,25 +1552,25 @@ static void REGPARM(3) sh2_write16_dram(u32 a, u32 d, SH2 *sh2)
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static void REGPARM(3) sh2_write16_sdram(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0x3fffe;
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((u16 *)sh2->p_sdram)[a1 / 2] = d;
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#ifdef DRC_SH2
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u8 *p = sh2->p_drcblk_ram;
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int t = p[a1 >> SH2_DRCBLK_RAM_SHIFT];
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if (t)
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sh2_drc_wcheck_ram(a, t, sh2);
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sh2_sdram_checks(a, t, sh2);
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#endif
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((u16 *)sh2->p_sdram)[a1 / 2] = d;
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}
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static void REGPARM(3) sh2_write16_da(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0xffe;
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((u16 *)sh2->data_array)[a1 / 2] = d;
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#ifdef DRC_SH2
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u8 *p = sh2->p_drcblk_da;
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int t = p[a1 >> SH2_DRCBLK_DA_SHIFT];
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if (t)
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sh2_drc_wcheck_da(a, t, sh2);
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sh2_da_checks(a, t, sh2);
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#endif
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((u16 *)sh2->data_array)[a1 / 2] = d;
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}
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static void REGPARM(3) sh2_write16_rom(u32 a, u32 d, SH2 *sh2)
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@ -1580,31 +1621,31 @@ static void REGPARM(3) sh2_write32_dram(u32 a, u32 d, SH2 *sh2)
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static void REGPARM(3) sh2_write32_sdram(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0x3fffc;
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*(u32 *)(sh2->p_sdram + a1) = (d << 16) | (d >> 16);
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#ifdef DRC_SH2
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u8 *p = sh2->p_drcblk_ram;
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int t = p[a1 >> SH2_DRCBLK_RAM_SHIFT];
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if (t)
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sh2_drc_wcheck_ram(a, t, sh2);
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sh2_sdram_checks(a, t, sh2);
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int u = p[(a1+2) >> SH2_DRCBLK_RAM_SHIFT];
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if (u)
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sh2_drc_wcheck_ram(a+2, u, sh2);
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sh2_sdram_checks(a+2, u, sh2);
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#endif
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*(u32 *)(sh2->p_sdram + a1) = (d << 16) | (d >> 16);
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}
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static void REGPARM(3) sh2_write32_da(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0xffc;
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*((u32 *)sh2->data_array + a1/4) = (d << 16) | (d >> 16);
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#ifdef DRC_SH2
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u8 *p = sh2->p_drcblk_da;
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int t = p[a1 >> SH2_DRCBLK_DA_SHIFT];
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if (t)
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sh2_drc_wcheck_da(a, t, sh2);
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sh2_da_checks(a, t, sh2);
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int u = p[(a1+2) >> SH2_DRCBLK_DA_SHIFT];
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if (u)
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sh2_drc_wcheck_da(a+2, u, sh2);
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sh2_da_checks(a+2, u, sh2);
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#endif
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*((u32 *)sh2->data_array + a1/4) = (d << 16) | (d >> 16);
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}
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static void REGPARM(3) sh2_write32_rom(u32 a, u32 d, SH2 *sh2)
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@ -2040,8 +2081,7 @@ void PicoMemSetup32x(void)
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sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr =
|
||||
sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr =
|
||||
sh2_read32_map[0x06/2].addr = sh2_read32_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram);
|
||||
sh2_write8_map[0x06/2] = sh2_write8_sdram;
|
||||
sh2_write8_map[0x26/2] = sh2_write8_sdram_wt;
|
||||
sh2_write8_map[0x06/2] = sh2_write8_map[0x26/2] = sh2_write8_sdram;
|
||||
sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
|
||||
sh2_write32_map[0x06/2] = sh2_write32_map[0x26/2] = sh2_write32_sdram;
|
||||
sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask = 0x03ffff;
|
||||
|
|
|
|||
|
|
@ -227,9 +227,9 @@ sh2_write32_sdram:
|
|||
ldrb r1, [ip, r3, lsr #SH2_RAM_SHIFT+1]!
|
||||
cmp r1, #0
|
||||
beq 1f
|
||||
stmfd sp!, {r0, r1, r2, ip}
|
||||
stmfd sp!, {r0, r2, ip, lr}
|
||||
bl sh2_drc_wcheck_ram
|
||||
ldmfd sp!, {r0, r1, r2, ip}
|
||||
ldmfd sp!, {r0, r2, ip, lr}
|
||||
1: ldrb r1, [ip, #1]
|
||||
cmp r1, #0
|
||||
bxeq lr
|
||||
|
|
@ -250,9 +250,9 @@ sh2_write32_da:
|
|||
ldrb r1, [ip, r3, lsr #SH2_DA_SHIFT+1]!
|
||||
cmp r1, #0
|
||||
beq 1f
|
||||
stmfd sp!, {r0, r1, r2, ip}
|
||||
stmfd sp!, {r0, r2, ip, lr}
|
||||
bl sh2_drc_wcheck_da
|
||||
ldmfd sp!, {r0, r1, r2, ip}
|
||||
ldmfd sp!, {r0, r2, ip, lr}
|
||||
1: ldrb r1, [ip, #1]
|
||||
cmp r1, #0
|
||||
bxeq lr
|
||||
|
|
@ -269,7 +269,6 @@ sh2_write32_dram:
|
|||
moveq r1, r1, ror #16
|
||||
streq r1, [ip, r3, lsr #SH2_DRAM_SHIFT]
|
||||
bxeq lr
|
||||
#if 1
|
||||
ldr r0, [ip, r3, lsr #SH2_DRAM_SHIFT]
|
||||
mov r1, r1, ror #16
|
||||
mov r2, #0
|
||||
|
|
@ -284,20 +283,6 @@ sh2_write32_dram:
|
|||
bic r0, r0, r2
|
||||
orr r0, r0, r1
|
||||
str r0, [ip, r3, lsr #SH2_DRAM_SHIFT]
|
||||
#else
|
||||
add ip, ip, r3, lsr #SH2_DRAM_SHIFT
|
||||
tst r1, #0x00ff0000
|
||||
lsrne r3, r1, #16
|
||||
strneb r3, [ip, #0]
|
||||
tst r1, #0xff000000
|
||||
lsrne r3, r1, #24
|
||||
strneb r3, [ip, #1]
|
||||
tst r1, #0x000000ff
|
||||
strneb r1, [ip, #2]
|
||||
tst r1, #0x0000ff00
|
||||
lsrne r3, r1, #8
|
||||
strneb r3, [ip, #3]
|
||||
#endif
|
||||
bx lr
|
||||
|
||||
.pool
|
||||
|
|
|
|||
|
|
@ -138,6 +138,7 @@ static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
|
|||
|
||||
if (chan->chcr & DMA_AR) {
|
||||
// auto-request transfer
|
||||
sh2->state |= SH2_STATE_SLEEP;
|
||||
while ((int)chan->tcr > 0)
|
||||
dmac_transfer_one(sh2, chan);
|
||||
dmac_transfer_complete(sh2, chan);
|
||||
|
|
@ -237,6 +238,7 @@ u32 REGPARM(2) sh2_peripheral_read8(u32 a, SH2 *sh2)
|
|||
a &= 0x1ff;
|
||||
d = PREG8(r, a);
|
||||
|
||||
sh2->poll_cnt = 0;
|
||||
elprintf_sh2(sh2, EL_32XP, "peri r8 [%08x] %02x @%06x",
|
||||
a | ~0x1ff, d, sh2_pc(sh2));
|
||||
return d;
|
||||
|
|
@ -250,6 +252,7 @@ u32 REGPARM(2) sh2_peripheral_read16(u32 a, SH2 *sh2)
|
|||
a &= 0x1fe;
|
||||
d = r[(a / 2) ^ 1];
|
||||
|
||||
sh2->poll_cnt = 0;
|
||||
elprintf_sh2(sh2, EL_32XP, "peri r16 [%08x] %04x @%06x",
|
||||
a | ~0x1ff, d, sh2_pc(sh2));
|
||||
return d;
|
||||
|
|
@ -258,9 +261,11 @@ u32 REGPARM(2) sh2_peripheral_read16(u32 a, SH2 *sh2)
|
|||
u32 REGPARM(2) sh2_peripheral_read32(u32 a, SH2 *sh2)
|
||||
{
|
||||
u32 d;
|
||||
|
||||
a &= 0x1fc;
|
||||
d = sh2->peri_regs[a / 4];
|
||||
|
||||
sh2->poll_cnt = 0;
|
||||
elprintf_sh2(sh2, EL_32XP, "peri r32 [%08x] %08x @%06x",
|
||||
a | ~0x1ff, d, sh2_pc(sh2));
|
||||
return d;
|
||||
|
|
@ -472,6 +477,7 @@ static void dreq1_do(SH2 *sh2, struct dma_chan *chan)
|
|||
if ((chan->dar & ~0xf) != 0x20004030)
|
||||
elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar);
|
||||
|
||||
sh2->state |= SH2_STATE_SLEEP;
|
||||
dmac_transfer_one(sh2, chan);
|
||||
if (chan->tcr == 0)
|
||||
dmac_transfer_complete(sh2, chan);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue