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drc: some debug improvements

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This commit is contained in:
notaz 2013-07-28 18:24:20 +03:00
parent 1555935b8a
commit 405dfdd77f
3 changed files with 86 additions and 16 deletions
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2
cpu/sh2/mame/sh2.c
View file

@ -115,7 +115,7 @@
#ifndef USE_SH2DRC
/* speed up delay loops, bail out of tight loops */
#define BUSY_LOOP_HACKS 1
//#define BUSY_LOOP_HACKS 1
#define VERBOSE 0

96
cpu/sh2/mame/sh2pico.c
View file

@ -1,6 +1,10 @@
#include "../sh2.h"
#ifdef DRC_CMP
#include "../compiler.c"
#define BUSY_LOOP_HACKS 0
#else
#define BUSY_LOOP_HACKS 1
#endif
// MAME types
@ -68,30 +72,99 @@ static unsigned int op_refs[0x10000];
#include "sh2.c"
#ifndef DRC_SH2
#ifndef DRC_CMP
int sh2_execute(SH2 *sh2, int cycles)
{
UINT32 opcode;
sh2->icount = sh2->cycles_timeslice = cycles;
if (sh2->icount <= 0)
goto out;
do
{
if (sh2->delay)
{
sh2->ppc = sh2->delay;
opcode = RW(sh2, sh2->delay);
sh2->pc -= 2;
}
else
{
sh2->ppc = sh2->pc;
opcode = RW(sh2, sh2->pc);
}
sh2->delay = 0;
sh2->pc += 2;
switch (opcode & ( 15 << 12))
{
case 0<<12: op0000(sh2, opcode); break;
case 1<<12: op0001(sh2, opcode); break;
case 2<<12: op0010(sh2, opcode); break;
case 3<<12: op0011(sh2, opcode); break;
case 4<<12: op0100(sh2, opcode); break;
case 5<<12: op0101(sh2, opcode); break;
case 6<<12: op0110(sh2, opcode); break;
case 7<<12: op0111(sh2, opcode); break;
case 8<<12: op1000(sh2, opcode); break;
case 9<<12: op1001(sh2, opcode); break;
case 10<<12: op1010(sh2, opcode); break;
case 11<<12: op1011(sh2, opcode); break;
case 12<<12: op1100(sh2, opcode); break;
case 13<<12: op1101(sh2, opcode); break;
case 14<<12: op1110(sh2, opcode); break;
default: op1111(sh2, opcode); break;
}
sh2->icount--;
if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
{
int level = sh2->pending_level;
int vector = sh2->irq_callback(sh2, level);
sh2_do_irq(sh2, level, vector);
sh2->test_irq = 0;
}
}
while (sh2->icount > 0 || sh2->delay); /* can't interrupt before delay */
out:
return sh2->cycles_timeslice - sh2->icount;
}
#else // if DRC_CMP
int sh2_execute(SH2 *sh2, int cycles)
{
#ifdef DRC_CMP
static unsigned int base_pc_[2] = { 0, 0 };
static unsigned int end_pc_[2] = { 0, 0 };
static unsigned char op_flags_[2][BLOCK_INSN_LIMIT];
unsigned int *base_pc = &base_pc_[sh2->is_slave];
unsigned int *end_pc = &end_pc_[sh2->is_slave];
unsigned char *op_flags = op_flags_[sh2->is_slave];
unsigned int pc_expect = sh2->pc;
#endif
unsigned int pc_expect;
UINT32 opcode;
sh2->icount = cycles;
sh2->icount = sh2->cycles_timeslice = cycles;
if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
{
int level = sh2->pending_level;
int vector = sh2->irq_callback(sh2, level);
sh2_do_irq(sh2, level, vector);
}
pc_expect = sh2->pc;
if (sh2->icount <= 0)
return cycles;
sh2->cycles_timeslice = cycles;
goto out;
do
{
#ifdef DRC_CMP
if (!sh2->delay) {
if (sh2->pc < *base_pc || sh2->pc >= *end_pc) {
*base_pc = sh2->pc;
@ -110,7 +183,6 @@ int sh2_execute(SH2 *sh2, int cycles)
do_sh2_trace(sh2, sh2->icount);
}
pc_expect += 2;
#endif
if (sh2->delay)
{
@ -158,15 +230,13 @@ int sh2_execute(SH2 *sh2, int cycles)
}
}
#ifndef DRC_CMP
while (sh2->icount > 0 || sh2->delay); /* can't interrupt before delay */
#else
while (1);
#endif
out:
return sh2->cycles_timeslice - sh2->icount;
}
#endif // DRC_CMP
#endif // DRC_SH2
#ifdef SH2_STATS