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sh2 drc, fix for cpu cache handling

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This commit is contained in:
kub 2020-10-10 14:21:10 +02:00
parent 07a08efcfc
commit 4153006fb8
7 changed files with 16 additions and 17 deletions
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4
cpu/drc/emit_arm.c
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@ -1246,8 +1246,8 @@ static inline void emith_pool_adjust(int tcache_offs, int move_offs)
EOP_LDMFD_SP(M2(r_,PC)); \
} while (0)
#define host_instructions_updated(base, end) \
emith_update_add(base, end)
#define host_instructions_updated(base, end, force) \
do { if (force) __builtin___clear_cache(base, end); } while (0)
#define host_arg2reg(rd, arg) \
rd = arg

3
cpu/drc/emit_arm64.c
View file

@ -1173,7 +1173,8 @@ static void emith_ldst_offs(int sz, int rd, int rn, int o9, int ld, int mode)
#define emith_pool_commit(j) /**/
#define emith_insn_ptr() ((u8 *)tcache_ptr)
#define emith_flush() /**/
#define host_instructions_updated(base, end) __builtin___clear_cache(base, end)
#define host_instructions_updated(base, end, force) \
do { if (force) __builtin___clear_cache(base, end); } while (0)
#define emith_update_cache() /**/
#define emith_rw_offs_max() 0xff
#define emith_uext_ptr(r) /**/

2
cpu/drc/emit_mips.c
View file

@ -1563,7 +1563,7 @@ static int emith_cond_check(int cond, int *r)
#define emith_pool_check() /**/
#define emith_pool_commit(j) /**/
// NB: mips32r2 has SYNCI
#define host_instructions_updated(base, end) __builtin___clear_cache(base, end)
#define host_instructions_updated(base, end, force) __builtin___clear_cache(base, end)
#define emith_update_cache() /**/
#define emith_rw_offs_max() 0x7fff
#define emith_uext_ptr(r) /**/

2
cpu/drc/emit_ppc.c
View file

@ -1538,7 +1538,7 @@ static int emith_cond_check(int cond)
#define emith_pool_commit(j) /**/
#define emith_insn_ptr() ((u8 *)tcache_ptr)
#define emith_flush() /**/
#define host_instructions_updated(base, end) __builtin___clear_cache(base, end)
#define host_instructions_updated(base, end, force) __builtin___clear_cache(base, end)
#define emith_update_cache() /**/
#define emith_rw_offs_max() 0x7fff

2
cpu/drc/emit_riscv.c
View file

@ -1400,7 +1400,7 @@ static int emith_cond_check(int cond, int *r, int *s)
// emitter ABI stuff
#define emith_insn_ptr() ((u8 *)tcache_ptr)
#define emith_flush() /**/
#define host_instructions_updated(base, end) __builtin___clear_cache(base, end)
#define host_instructions_updated(base, end, force) __builtin___clear_cache(base, end)
#define emith_update_cache() /**/
#define emith_rw_offs_max() 0x7ff
#define emith_uext_ptr(r) /**/

4
cpu/drc/emit_x86.c
View file

@ -618,7 +618,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
t >>= count; \
if (d != s) \
emith_move_r_r(d, s); \
emith_and_r_imm(d, t); \
if (count) emith_and_r_imm(d, t); \
} while (0)
#define emith_clear_msb_c(cond, d, s, count) do { \
@ -1019,7 +1019,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
emith_move_r_imm(rd, imm); \
} while (0)
#define host_instructions_updated(base, end) (void)(base),(void)(end)
#define host_instructions_updated(base, end, force) (void)(base),(void)(end)
#define emith_update_cache() /**/
// NB this MUST be <0x40000000 to avoid overflow in address calculations