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sh2 drc, fix for cpu cache handling

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kub 2020-10-10 14:21:10 +02:00
parent 07a08efcfc
commit 4153006fb8
7 changed files with 16 additions and 17 deletions
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cpu/drc/emit_mips.c
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@ -1563,7 +1563,7 @@ static int emith_cond_check(int cond, int *r)
#define emith_pool_check() /**/
#define emith_pool_commit(j) /**/
// NB: mips32r2 has SYNCI
#define host_instructions_updated(base, end) __builtin___clear_cache(base, end)
#define host_instructions_updated(base, end, force) __builtin___clear_cache(base, end)
#define emith_update_cache() /**/
#define emith_rw_offs_max() 0x7fff
#define emith_uext_ptr(r) /**/