sh2 drc, fix for cpu cache handling

cpu/drc/emit_arm.c

@@ -1246,8 +1246,8 @@ static inline void emith_pool_adjust(int tcache_offs, int move_offs)
 	EOP_LDMFD_SP(M2(r_,PC)); \
 } while (0)
 
-#define host_instructions_updated(base, end) \
+#define host_instructions_updated(base, end, force) \
-	emith_update_add(base, end)
+	do { if (force) __builtin___clear_cache(base, end); } while (0)
 
 #define host_arg2reg(rd, arg) \
 	rd = arg

cpu/drc/emit_arm64.c

@@ -1173,7 +1173,8 @@ static void emith_ldst_offs(int sz, int rd, int rn, int o9, int ld, int mode)
 #define emith_pool_commit(j)	/**/
 #define emith_insn_ptr()	((u8 *)tcache_ptr)
 #define	emith_flush()		/**/
-#define host_instructions_updated(base, end) __builtin___clear_cache(base, end)
+#define host_instructions_updated(base, end, force) \
+	do { if (force) __builtin___clear_cache(base, end); } while (0)
 #define	emith_update_cache()	/**/
 #define emith_rw_offs_max()	0xff
 #define emith_uext_ptr(r)	/**/

cpu/drc/emit_mips.c

@@ -1563,7 +1563,7 @@ static int emith_cond_check(int cond, int *r)
 #define emith_pool_check()	/**/
 #define emith_pool_commit(j)	/**/
 // NB: mips32r2 has SYNCI
-#define host_instructions_updated(base, end) __builtin___clear_cache(base, end)
+#define host_instructions_updated(base, end, force) __builtin___clear_cache(base, end)
 #define	emith_update_cache()	/**/
 #define emith_rw_offs_max()	0x7fff
 #define emith_uext_ptr(r)	/**/

cpu/drc/emit_ppc.c

@@ -1538,7 +1538,7 @@ static int emith_cond_check(int cond)
 #define emith_pool_commit(j)	/**/
 #define emith_insn_ptr()	((u8 *)tcache_ptr)
 #define emith_flush()		/**/
-#define host_instructions_updated(base, end) __builtin___clear_cache(base, end)
+#define host_instructions_updated(base, end, force) __builtin___clear_cache(base, end)
 #define emith_update_cache()	/**/
 #define emith_rw_offs_max()	0x7fff
 

cpu/drc/emit_riscv.c

@@ -1400,7 +1400,7 @@ static int emith_cond_check(int cond, int *r, int *s)
 // emitter ABI stuff
 #define emith_insn_ptr()	((u8 *)tcache_ptr)
 #define	emith_flush()		/**/
-#define host_instructions_updated(base, end) __builtin___clear_cache(base, end)
+#define host_instructions_updated(base, end, force) __builtin___clear_cache(base, end)
 #define	emith_update_cache()	/**/
 #define emith_rw_offs_max()	0x7ff
 #define emith_uext_ptr(r)	/**/

cpu/drc/emit_x86.c

@@ -618,7 +618,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI,	// x86-64,i386 common
 	t >>= count; \
 	if (d != s) \
 		emith_move_r_r(d, s); \
-	emith_and_r_imm(d, t); \
+	if (count) emith_and_r_imm(d, t); \
 } while (0)
 
 #define emith_clear_msb_c(cond, d, s, count) do { \
@@ -1019,7 +1019,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI,	// x86-64,i386 common
 	emith_move_r_imm(rd, imm); \
 } while (0)
 
-#define host_instructions_updated(base, end)	(void)(base),(void)(end)
+#define host_instructions_updated(base, end, force)	(void)(base),(void)(end)
 #define	emith_update_cache()	/**/
 
 // NB this MUST be <0x40000000 to avoid overflow in address calculations

cpu/sh2/compiler.c

@@ -815,16 +815,14 @@ static void dr_block_link(struct block_entry *be, struct block_link *bl, int emi
         // via blx: @jump near jumpcc to blx; @blx far jump
         emith_jump_patch(jump, bl->blx, &jump);
         emith_jump_at(bl->blx, be->tcache_ptr);
-        if ((((uintptr_t)bl->blx & 0x0f) + emith_jump_at_size()-1) > 0x0f)
+        host_instructions_updated(bl->blx, bl->blx + emith_jump_at_size(),
-          host_instructions_updated(bl->blx, bl->blx + emith_jump_at_size());
+            ((uintptr_t)bl->blx & 0x0f) + emith_jump_at_size()-1 > 0x0f);
       }
     } else {
       printf("unknown BL type %d\n", bl->type);
       exit(1);
     }
-    // only needs sync if patch is possibly crossing cacheline (assume 16 byte)
+    host_instructions_updated(jump, jump + jsz, ((uintptr_t)jump & 0x0f) + jsz-1 > 0x0f);
-    if ((((uintptr_t)jump & 0x0f) + jsz-1) > 0x0f)
-      host_instructions_updated(jump, jump + jsz);
   }
 
   // move bl to block_entry
@@ -855,13 +853,13 @@ static void dr_block_unlink(struct block_link *bl, int emit_jump)
         // via blx: @jump near jumpcc to blx; @blx load target_pc, far jump
         emith_jump_patch(bl->jump, bl->blx, &jump);
         memcpy(bl->blx, bl->jdisp, emith_jump_at_size());
-        host_instructions_updated(bl->blx, bl->blx + emith_jump_at_size());
+        host_instructions_updated(bl->blx, bl->blx + emith_jump_at_size(), 1);
       } else {
         printf("unknown BL type %d\n", bl->type);
         exit(1);
       }
       // update cpu caches since the previous jump target doesn't exist anymore
-      host_instructions_updated(jump, jump + jsz);
+      host_instructions_updated(jump, jump + jsz, 1);
     }
 
     if (bl->prev)
@@ -5143,7 +5141,7 @@ end_op:
       memcpy(bl->jdisp, bl->blx ?: bl->jump, emith_jump_at_size());
 
   ring_alloc(&tcache_ring[tcache_id], tcache_ptr - block_entry_ptr);
-  host_instructions_updated(block_entry_ptr, tcache_ptr);
+  host_instructions_updated(block_entry_ptr, tcache_ptr, 1);
 
   dr_activate_block(block, tcache_id, sh2->is_slave);
   emith_update_cache();
@@ -5879,7 +5877,7 @@ int sh2_drc_init(SH2 *sh2)
 
     tcache_ptr = tcache;
     sh2_generate_utils();
-    host_instructions_updated(tcache, tcache_ptr);
+    host_instructions_updated(tcache, tcache_ptr, 1);
     emith_update_cache();
 
     i = tcache_ptr - tcache;