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32x, tentative kludge for blackthorne

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This commit is contained in:
kub 2022-11-21 21:08:39 +00:00
parent eb990fd62a
commit 4ec1247d23
6 changed files with 48 additions and 33 deletions
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51
pico/32x/sh2soc.c
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@ -270,6 +270,7 @@ u32 REGPARM(2) sh2_peripheral_read8(u32 a, SH2 *sh2)
u8 *r = (void *)sh2->peri_regs;
u32 d;
DRC_SAVE_SR(sh2);
a &= 0x1ff;
d = PREG8(r, a);
@ -277,10 +278,9 @@ u32 REGPARM(2) sh2_peripheral_read8(u32 a, SH2 *sh2)
a | ~0x1ff, d, sh2_pc(sh2));
if ((a & 0x1c0) == 0x140) {
// abused as comm area
DRC_SAVE_SR(sh2);
p32x_sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 3);
DRC_RESTORE_SR(sh2);
}
DRC_RESTORE_SR(sh2);
return d;
}
@ -289,6 +289,7 @@ u32 REGPARM(2) sh2_peripheral_read16(u32 a, SH2 *sh2)
u16 *r = (void *)sh2->peri_regs;
u32 d;
DRC_SAVE_SR(sh2);
a &= 0x1fe;
d = r[MEM_BE2(a / 2)];
@ -296,10 +297,9 @@ u32 REGPARM(2) sh2_peripheral_read16(u32 a, SH2 *sh2)
a | ~0x1ff, d, sh2_pc(sh2));
if ((a & 0x1c0) == 0x140) {
// abused as comm area
DRC_SAVE_SR(sh2);
p32x_sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 3);
DRC_RESTORE_SR(sh2);
}
DRC_RESTORE_SR(sh2);
return d;
}
@ -307,6 +307,7 @@ u32 REGPARM(2) sh2_peripheral_read32(u32 a, SH2 *sh2)
{
u32 d;
DRC_SAVE_SR(sh2);
a &= 0x1fc;
d = sh2->peri_regs[a / 4];
@ -317,10 +318,9 @@ u32 REGPARM(2) sh2_peripheral_read32(u32 a, SH2 *sh2)
sh2->poll_cnt = 0;
else if ((a & 0x1c0) == 0x140) {
// abused as comm area
DRC_SAVE_SR(sh2);
p32x_sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 3);
DRC_RESTORE_SR(sh2);
}
DRC_RESTORE_SR(sh2);
return d;
}
@ -364,18 +364,18 @@ void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2)
u8 *r = (void *)sh2->peri_regs;
u8 old;
DRC_SAVE_SR(sh2);
elprintf_sh2(sh2, EL_32XP, "peri w8 [%08x] %02x @%06x",
a, d, sh2_pc(sh2));
a &= 0x1ff;
old = PREG8(r, a);
PREG8(r, a) = d;
switch (a) {
case 0x002: // SCR - serial control
if (!(PREG8(r, a) & 0x20) && (d & 0x20)) { // TE being set
PREG8(r, a) = d;
if (!(old & 0x20) && (d & 0x20)) // TE being set
sci_trigger(sh2, r);
}
break;
case 0x003: // TDR - transmit data
break;
@ -383,27 +383,31 @@ void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2)
d = (old & (d | 0x06)) | (d & 1);
PREG8(r, a) = d;
sci_trigger(sh2, r);
return;
break;
case 0x005: // RDR - receive data
break;
case 0x010: // TIER
if (d & 0x8e)
elprintf(EL_32XP|EL_ANOMALY, "TIER: %02x", d);
d = (d & 0x8e) | 1;
PREG8(r, a) = d;
break;
case 0x017: // TOCR
d |= 0xe0;
PREG8(r, a) = d;
break;
default:
if ((a & 0x1c0) == 0x140)
p32x_sh2_poll_event(sh2, SH2_STATE_CPOLL, SekCyclesDone());
}
PREG8(r, a) = d;
if ((a & 0x1c0) == 0x140)
p32x_sh2_poll_event(sh2, SH2_STATE_CPOLL, SekCyclesDone());
DRC_RESTORE_SR(sh2);
}
void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
{
u16 *r = (void *)sh2->peri_regs;
DRC_SAVE_SR(sh2);
elprintf_sh2(sh2, EL_32XP, "peri w16 [%08x] %04x @%06x",
a, d, sh2_pc(sh2));
@ -417,12 +421,12 @@ void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
}
if ((d & 0xff00) == 0x5a00) // WTCNT
PREG8(r, 0x81) = d;
return;
} else {
r[MEM_BE2(a / 2)] = d;
if ((a & 0x1c0) == 0x140)
p32x_sh2_poll_event(sh2, SH2_STATE_CPOLL, SekCyclesDone());
}
r[MEM_BE2(a / 2)] = d;
if ((a & 0x1c0) == 0x140)
p32x_sh2_poll_event(sh2, SH2_STATE_CPOLL, SekCyclesDone());
DRC_RESTORE_SR(sh2);
}
void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
@ -431,6 +435,7 @@ void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
u32 old;
struct dmac *dmac;
DRC_SAVE_SR(sh2);
elprintf_sh2(sh2, EL_32XP, "peri w32 [%08x] %08x @%06x",
a, d, sh2_pc(sh2));
@ -480,17 +485,17 @@ void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
if (!(dmac->dmaor & DMA_DME))
return;
DRC_SAVE_SR(sh2);
if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
dmac_trigger(sh2, &dmac->chan[0]);
if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
dmac_trigger(sh2, &dmac->chan[1]);
DRC_RESTORE_SR(sh2);
break;
default:
if ((a & 0x1c0) == 0x140)
p32x_sh2_poll_event(sh2, SH2_STATE_CPOLL, SekCyclesDone());
}
if ((a & 0x1c0) == 0x140)
p32x_sh2_poll_event(sh2, SH2_STATE_CPOLL, SekCyclesDone());
DRC_RESTORE_SR(sh2);
}
/* 32X specific */