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core z80, improve save/load (cycles)

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kub 2024-05-07 23:12:54 +02:00
parent ebde43de9d
commit 52cb58c50d
2 changed files with 4 additions and 3 deletions
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2
pico/state.c
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@ -599,8 +599,6 @@ readend:
z80_unpack(buff_z80); z80_unpack(buff_z80);
// due to dep from 68k cycles..
Pico.t.m68c_frame_start = Pico.t.m68c_aim;
if (PicoIn.AHW & PAHW_32X) if (PicoIn.AHW & PAHW_32X)
Pico32xStateLoaded(0); Pico32xStateLoaded(0);
if (PicoIn.AHW & PAHW_MCD) if (PicoIn.AHW & PAHW_MCD)

5
pico/z80if.c
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@ -157,7 +157,8 @@ struct z80_state {
u8 im; // irq mode u8 im; // irq mode
u8 irq_pending; // irq line level, 1 if active u8 irq_pending; // irq line level, 1 if active
u8 irq_vector[3]; // up to 3 byte vector for irq mode0 handling u8 irq_vector[3]; // up to 3 byte vector for irq mode0 handling
u8 reserved[8]; u16 cyc;
u8 reserved[6];
}; };
void z80_pack(void *data) void z80_pack(void *data)
@ -165,6 +166,7 @@ void z80_pack(void *data)
struct z80_state *s = data; struct z80_state *s = data;
memset(data, 0, Z80_STATE_SIZE); memset(data, 0, Z80_STATE_SIZE);
memcpy(s->magic, "Z80a", 4); memcpy(s->magic, "Z80a", 4);
s->cyc = Pico.t.z80c_cnt;
#if defined(_USE_DRZ80) #if defined(_USE_DRZ80)
#define DRR8(n) (drZ80.Z80##n >> 24) #define DRR8(n) (drZ80.Z80##n >> 24)
#define DRR16(n) (drZ80.Z80##n >> 16) #define DRR16(n) (drZ80.Z80##n >> 16)
@ -222,6 +224,7 @@ int z80_unpack(const void *data)
elprintf(EL_STATUS, "legacy z80 state - ignored"); elprintf(EL_STATUS, "legacy z80 state - ignored");
return 0; return 0;
} }
Pico.t.z80c_cnt = s->cyc;
#if defined(_USE_DRZ80) #if defined(_USE_DRZ80)
#define DRW8(n, v) drZ80.Z80##n = (u32)(v) << 24 #define DRW8(n, v) drZ80.Z80##n = (u32)(v) << 24