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https://github.com/RaySollium99/picodrive.git
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32x: drc: all opcodes covered, some TODOs left
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@830 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
488c0bbf55
commit
52d759c30f
3 changed files with 549 additions and 169 deletions
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@ -77,6 +77,7 @@
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#define A_OP_ADD 0x4
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#define A_OP_ADC 0x5
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#define A_OP_SBC 0x6
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#define A_OP_RSC 0x7
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#define A_OP_TST 0x8
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#define A_OP_TEQ 0x9
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#define A_OP_CMP 0xa
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@ -93,6 +94,7 @@
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#define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs, shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs, shift_op,rm))
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#define EOP_MOV_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
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#define EOP_MVN_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MVN,0, 0,rd,ror2,imm8)
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#define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
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#define EOP_EOR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_EOR,0,rn,rd,ror2,imm8)
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#define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
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@ -108,6 +110,7 @@
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#define EOP_RSB_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_RSB,0,rn,rd,ror2,imm8)
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#define EOP_MOV_REG(cond,s,rd, rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
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#define EOP_MVN_REG(cond,s,rd, rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_MVN,s, 0,rd,shift_imm,shift_op,rm)
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#define EOP_ORR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_ADD_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_ADC_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADC,s,rn,rd,shift_imm,shift_op,rm)
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@ -218,9 +221,9 @@
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#define EOP_MSR_REG(rm) EOP_C_MSR_REG(A_COND_AL,rm)
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static void emith_op_imm(int cond, int s, int op, int r, unsigned int imm)
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static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int imm)
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{
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int ror2, rd = r, rn = r;
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int ror2;
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u32 v;
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if (op == A_OP_MOV)
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@ -237,11 +240,14 @@ static void emith_op_imm(int cond, int s, int op, int r, unsigned int imm)
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if (op == A_OP_MOV) {
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op = A_OP_ORR;
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rn = r;
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rn = rd;
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}
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}
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}
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#define emith_op_imm(cond, s, op, r, imm) \
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emith_op_imm2(cond, s, op, r, r, imm)
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// test op
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#define emith_top_imm(cond, op, r, imm) { \
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u32 ror2, v; \
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@ -293,6 +299,9 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_move_r_r(d, s) \
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EOP_MOV_REG_SIMPLE(d, s)
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#define emith_mvn_r_r(d, s) \
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EOP_MVN_REG(A_COND_AL,0,d,s,A_AM1_LSL,0)
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#define emith_or_r_r_r_lsl(d, s1, s2, lslimm) \
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EOP_ORR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
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@ -353,9 +362,15 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_bic_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_BIC, r, imm)
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#define emith_and_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_AND, r, imm)
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#define emith_or_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_ORR, r, imm)
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#define emith_eor_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_EOR, r, imm)
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// note: only use 8bit imm for these
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#define emith_tst_r_imm(r, imm) \
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emith_top_imm(A_COND_AL, A_OP_TST, r, imm)
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@ -378,6 +393,19 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_bic_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_BIC, r, imm)
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#define emith_move_r_imm_s8(r, imm) { \
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if ((imm) & 0x80) \
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EOP_MVN_IMM(r, 0, ((imm) ^ 0xff)); \
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else \
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EOP_MOV_IMM(r, 0, imm); \
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}
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#define emith_and_r_r_imm(d, s, imm) \
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emith_op_imm2(A_COND_AL, 0, A_OP_AND, d, s, imm)
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#define emith_neg_r_r(d, s) \
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EOP_RSB_IMM(d, s, 0, 0)
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#define emith_lsl(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSL,cnt)
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@ -387,6 +415,9 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_ror(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,cnt)
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#define emith_rol(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,32-(cnt)); \
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#define emith_lslf(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSL,cnt)
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@ -412,6 +443,9 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_rorcf(d) \
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EOP_MOV_REG(A_COND_AL,1,d,d,A_AM1_ROR,0) /* ROR #0 -> RRX */
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#define emith_negcf_r_r(d, s) \
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EOP_C_DOP_IMM(A_COND_AL,A_OP_RSC,1,s,d,0,0)
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#define emith_mul(d, s1, s2) { \
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if ((d) != (s1)) /* rd != rm limitation */ \
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EOP_MUL(d, s1, s2); \
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@ -495,23 +529,23 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_sh2_dtbf_loop() { \
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int cr, rn; \
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tmp = rcache_get_tmp(); \
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int tmp_ = rcache_get_tmp(); \
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cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
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rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW); \
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emith_sub_r_imm(rn, 1); /* sub rn, #1 */ \
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emith_bic_r_imm(cr, 1); /* bic cr, #1 */ \
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emith_sub_r_imm(cr, (cycles+1) << 12); /* sub cr, #(cycles+1)<<12 */ \
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cycles = 0; \
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emith_asrf(tmp, cr, 2+12); /* movs tmp, cr, asr #2+12 */ \
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EOP_MOV_IMM_C(A_COND_MI,tmp,0,0); /* movmi tmp, #0 */ \
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emith_asrf(tmp_, cr, 2+12); /* movs tmp_, cr, asr #2+12 */\
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EOP_MOV_IMM_C(A_COND_MI,tmp_,0,0); /* movmi tmp_, #0 */ \
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emith_lsl(cr, cr, 20); /* mov cr, cr, lsl #20 */ \
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emith_lsr(cr, cr, 20); /* mov cr, cr, lsr #20 */ \
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emith_subf_r_r(rn, tmp); /* subs rn, tmp */ \
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EOP_RSB_IMM_C(A_COND_LS,tmp,rn,0,0); /* rsbls tmp, rn, #0 */ \
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EOP_ORR_REG(A_COND_LS,0,cr,cr,tmp,A_AM1_LSL,12+2); /* orrls cr,tmp,lsl #12+2 */\
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emith_subf_r_r(rn, tmp_); /* subs rn, tmp_ */ \
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EOP_RSB_IMM_C(A_COND_LS,tmp_,rn,0,0); /* rsbls tmp_, rn, #0 */ \
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EOP_ORR_REG(A_COND_LS,0,cr,cr,tmp_,A_AM1_LSL,12+2); /* orrls cr,tmp_,lsl #12+2 */\
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EOP_ORR_IMM_C(A_COND_LS,cr,cr,0,1); /* orrls cr, #1 */ \
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EOP_MOV_IMM_C(A_COND_LS,rn,0,0); /* movls rn, #0 */ \
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rcache_free_tmp(tmp); \
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rcache_free_tmp(tmp_); \
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}
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#define emith_write_sr(srcr) { \
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@ -1,5 +1,5 @@
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/*
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* note about silly things like emith_eor_r_r_r_lsl:
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* note about silly things like emith_or_r_r_r_lsl:
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* these are here because the compiler was designed
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* for ARM as it's primary target.
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*/
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@ -107,25 +107,44 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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emith_pop(d); \
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}
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#define emith_mvn_r_r(d, s) { \
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if (d != s) \
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emith_move_r_r(d, s); \
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EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
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}
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#define emith_negc_r_r(d, s) { \
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int tmp_ = rcache_get_tmp(); \
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emith_move_r_imm(tmp_, 0); \
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emith_sbc_r_r(tmp_, s); \
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emith_move_r_r(d, tmp_); \
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rcache_free_tmp(tmp_); \
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}
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#define emith_neg_r_r(d, s) { \
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if (d != s) \
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emith_move_r_r(d, s); \
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EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
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}
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// _r_r_r
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#define emith_eor_r_r_r(d, s1, s2) { \
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if (d != s1) \
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if (d == s1) { \
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emith_eor_r_r(d, s2); \
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} else if (d == s2) { \
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emith_eor_r_r(d, s1); \
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} else { \
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emith_move_r_r(d, s1); \
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emith_eor_r_r(d, s2); \
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emith_eor_r_r(d, s2); \
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} \
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}
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#define emith_or_r_r_r_lsl(d, s1, s2, lslimm) { \
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if (d != s2 && d != s1) { \
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emith_lsl(d, s2, lslimm); \
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emith_or_r_r(d, s1); \
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} else { \
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if (d != s1) \
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emith_move_r_r(d, s1); \
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emith_push(s2); \
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emith_lsl(s2, s2, lslimm); \
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emith_or_r_r(d, s2); \
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emith_pop(s2); \
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} \
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int tmp_ = rcache_get_tmp(); \
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emith_lsl(tmp_, s2, lslimm); \
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emith_or_r_r(tmp_, s1); \
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emith_move_r_r(d, tmp_); \
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rcache_free_tmp(tmp_); \
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}
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// _r_imm
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@ -134,12 +153,15 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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EMIT(imm, u32); \
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}
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#define emith_move_r_imm_s8(r, imm) \
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emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))
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#define emith_arith_r_imm(op, r, imm) { \
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EMIT_OP_MODRM(0x81, 3, op, r); \
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EMIT(imm, u32); \
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}
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// 2 - adc, 3 - sbb, 6 - xor
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// 2 - adc, 3 - sbb
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#define emith_add_r_imm(r, imm) \
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emith_arith_r_imm(0, r, imm)
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@ -152,6 +174,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_sub_r_imm(r, imm) \
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emith_arith_r_imm(5, r, imm)
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#define emith_eor_r_imm(r, imm) \
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emith_arith_r_imm(6, r, imm)
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#define emith_cmp_r_imm(r, imm) \
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emith_arith_r_imm(7, r, imm)
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@ -185,6 +210,13 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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emith_bic_r_imm(r, imm); \
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}
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// _r_r_imm
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#define emith_and_r_r_imm(d, s, imm) { \
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if (d != s) \
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emith_move_r_r(d, s); \
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emith_and_r_imm(d, imm) \
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}
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// shift
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#define emith_shift(op, d, s, cnt) { \
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if (d != s) \
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@ -292,6 +324,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_subf_r_r emith_sub_r_r
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#define emith_adcf_r_r emith_adc_r_r
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#define emith_sbcf_r_r emith_sbc_r_r
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#define emith_negcf_r_r emith_negc_r_r
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#define emith_lslf emith_lsl
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#define emith_lsrf emith_lsr
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@ -363,18 +396,18 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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u8 *jmp0; /* negative cycles check */ \
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u8 *jmp1; /* unsinged overflow check */ \
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int cr, rn; \
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tmp = rcache_get_tmp(); \
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int tmp_ = rcache_get_tmp(); \
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cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
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rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
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emith_sub_r_imm(rn, 1); \
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emith_sub_r_imm(cr, (cycles+1) << 12); \
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cycles = 0; \
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emith_asr(tmp, cr, 2+12); \
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emith_asr(tmp_, cr, 2+12); \
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JMP8_POS(jmp0); /* no negative cycles */ \
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emith_move_r_imm(tmp, 0); \
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emith_move_r_imm(tmp_, 0); \
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JMP8_EMIT(IOP_JNS, jmp0); \
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emith_and_r_imm(cr, 0xffe); \
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emith_subf_r_r(rn, tmp); \
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emith_subf_r_r(rn, tmp_); \
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JMP8_POS(jmp1); /* no overflow */ \
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emith_neg_r(rn); /* count left */ \
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emith_lsl(rn, rn, 2+12); \
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@ -382,25 +415,25 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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emith_or_r_imm(cr, 1); \
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emith_move_r_imm(rn, 0); \
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JMP8_EMIT(IOP_JA, jmp1); \
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rcache_free_tmp(tmp); \
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rcache_free_tmp(tmp_); \
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}
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#define emith_write_sr(srcr) { \
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int tmp = rcache_get_tmp(); \
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int tmp_ = rcache_get_tmp(); \
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int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
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emith_clear_msb(tmp, srcr, 20); \
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emith_clear_msb(tmp_, srcr, 20); \
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emith_bic_r_imm(srr, 0xfff); \
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emith_or_r_r(srr, tmp); \
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rcache_free_tmp(tmp); \
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emith_or_r_r(srr, tmp_); \
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rcache_free_tmp(tmp_); \
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}
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#define emith_carry_to_t(srr, is_sub) { \
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int tmp = rcache_get_tmp(); \
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int tmp_ = rcache_get_tmp(); \
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EMIT_OP(0x0f); \
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EMIT(0x92, u8); \
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EMIT_MODRM(3, 0, tmp); /* SETC */ \
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EMIT_MODRM(3, 0, tmp_); /* SETC */ \
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emith_bic_r_imm(srr, 1); \
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EMIT_OP_MODRM(0x08, 3, tmp, srr); /* OR srrl, tmpl */ \
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rcache_free_tmp(tmp); \
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EMIT_OP_MODRM(0x08, 3, tmp_, srr); /* OR srrl, tmpl */ \
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rcache_free_tmp(tmp_); \
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}
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