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https://github.com/RaySollium99/picodrive.git
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add big endian platform support
This commit is contained in:
kub
parent
b053cb2044
commit
57c5a5e505
21 changed files with 224 additions and 178 deletions
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@ -21,36 +21,38 @@
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extern "C" {
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#endif
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#include <pico/pico_port.h>
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/******************************/
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/* Compiler dependant defines */
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/******************************/
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#ifndef UINT8
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#define UINT8 unsigned char
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#define UINT8 u8
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#endif
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#ifndef INT8
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#define INT8 signed char
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#define INT8 s8
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#endif
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#ifndef UINT16
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#define UINT16 unsigned short
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#define UINT16 u16
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#endif
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#ifndef INT16
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#define INT16 signed short
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#define INT16 s16
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#endif
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#ifndef UINT32
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#define UINT32 unsigned int
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#define UINT32 u32
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#endif
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#ifndef INT32
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#define INT32 signed int
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#define INT32 s32
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#endif
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#ifndef FPTR
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#define FPTR uintptr_t
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#define FPTR uptr
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#endif
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/*************************************/
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@ -62,16 +64,16 @@ extern "C" {
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#define CZ80_FETCH_SFT (16 - CZ80_FETCH_BITS)
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#define CZ80_FETCH_BANK (1 << CZ80_FETCH_BITS)
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#define PICODRIVE_HACKS 1
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#define CZ80_LITTLE_ENDIAN 1
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#define PICODRIVE_HACKS 1
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#define CZ80_LITTLE_ENDIAN CPU_IS_LE
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#define CZ80_USE_JUMPTABLE 1
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#define CZ80_BIG_FLAGS_ARRAY 1
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#define CZ80_BIG_FLAGS_ARRAY 1
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//#ifdef BUILD_CPS1PSP
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//#define CZ80_ENCRYPTED_ROM 1
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//#else
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#define CZ80_ENCRYPTED_ROM 0
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//#endif
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#define CZ80_EMULATE_R_EXACTLY 1
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#define CZ80_EMULATE_R_EXACTLY 1
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#define zR8(A) (*CPU->pzR8[A])
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#define zR16(A) (CPU->pzR16[A]->W)
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@ -48,11 +48,7 @@
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#define READ_OP() GET_OP(); PC++
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#define READ_ARG() (*(UINT8 *)PC++)
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#if CZ80_LITTLE_ENDIAN
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#define READ_ARG16() (*(UINT8 *)PC | (*(UINT8 *)(PC + 1) << 8)); PC += 2
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#else
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#define READ_ARG16() (*(UINT8 *)(PC + 1) | (*(UINT8 *)PC << 8)); PC += 2
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#endif
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//#ifndef BUILD_CPS1PSP
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//#define READ_MEM8(A) memory_region_cpu2[(A)]
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@ -63,11 +59,7 @@
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#define READ_MEM8(A) CPU->Read_Byte(A)
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#endif
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//#endif
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#if CZ80_LITTLE_ENDIAN
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#define READ_MEM16(A) (READ_MEM8(A) | (READ_MEM8((A) + 1) << 8))
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#else
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#define READ_MEM16(A) ((READ_MEM8(A) << 8) | READ_MEM8((A) + 1))
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#endif
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#if PICODRIVE_HACKS
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#define WRITE_MEM8(A, D) { \
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@ -82,11 +74,7 @@
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#else
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#define WRITE_MEM8(A, D) CPU->Write_Byte(A, D);
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#endif
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#if CZ80_LITTLE_ENDIAN
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#define WRITE_MEM16(A, D) { WRITE_MEM8(A, D); WRITE_MEM8((A) + 1, (D) >> 8); }
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#else
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#define WRITE_MEM16(A, D) { WRITE_MEM8((A) + 1, D); WRITE_MEM8(A, (D) >> 8); }
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#endif
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#define PUSH_16(A) { UINT32 sp; zSP -= 2; sp = zSP; WRITE_MEM16(sp, A); }
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#define POP_16(A) { UINT32 sp; sp = zSP; A = READ_MEM16(sp); zSP = sp + 2; }
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@ -98,44 +98,7 @@ extern "C" {
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/* Data definition */
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/*******************/
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#include <pico/pico_types.h>
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/*
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#ifdef u8
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#undef u8
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#endif
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#ifdef s8
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#undef s8
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#endif
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#ifdef u16
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#undef u16
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#endif
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#ifdef s16
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#undef s16
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#endif
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#ifdef u32
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#undef u32
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#endif
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#ifdef s32
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#undef s32
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#endif
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#ifdef uptr
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#undef uptr
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#endif
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#define u8 unsigned char
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#define s8 signed char
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#define u16 unsigned short
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#define s16 signed short
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#define u32 unsigned int
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#define s32 signed int
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#define uptr uintptr_t
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*/
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#include <pico/pico_port.h>
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/*
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typedef unsigned char u8;
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@ -148,10 +111,10 @@ typedef signed int s32;
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typedef union
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{
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u8 B;
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s8 SB;
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u16 W;
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s16 SW;
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u8 B[4];
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s8 SB[4];
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u16 W[2];
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s16 SW[2];
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u32 D;
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s32 SD;
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} famec_union32;
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@ -183,19 +183,22 @@
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// internals core macros
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/////////////////////////
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#define XB MEM_LE4(0)
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#define XW MEM_LE2(0)
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#define DREG(X) (ctx->dreg[(X)].D)
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#define DREGu32(X) (ctx->dreg[(X)].D)
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#define DREGs32(X) (ctx->dreg[(X)].SD)
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#define DREGu16(X) (ctx->dreg[(X)].W)
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#define DREGs16(X) (ctx->dreg[(X)].SW)
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#define DREGu8(X) (ctx->dreg[(X)].B)
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#define DREGs8(X) (ctx->dreg[(X)].SB)
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#define DREGu16(X) (ctx->dreg[(X)].W[XW])
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#define DREGs16(X) (ctx->dreg[(X)].SW[XW])
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#define DREGu8(X) (ctx->dreg[(X)].B[XB])
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#define DREGs8(X) (ctx->dreg[(X)].SB[XB])
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#define AREG(X) (ctx->areg[(X)].D)
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#define AREGu32(X) (ctx->areg[(X)].D)
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#define AREGs32(X) (ctx->areg[(X)].SD)
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#define AREGu16(X) (ctx->areg[(X)].W)
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#define AREGs16(X) (ctx->areg[(X)].SW)
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#define AREGu16(X) (ctx->areg[(X)].W[XW])
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#define AREGs16(X) (ctx->areg[(X)].SW[XW])
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#define ASP (ctx->asp)
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@ -2568,6 +2568,28 @@ static void rcache_init(void)
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// ---------------------------------------------------------------
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// swap 32 bit value read from mem in generated code (same as CPU_BE2)
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static void emit_le_swap(int cond, int r)
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{
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#if CPU_IS_LE
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if (cond == -1)
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emith_ror(r, r, 16);
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else
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emith_ror_c(cond, r, r, 16);
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#endif
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}
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// fix memory byte ptr in generated code (same as MEM_BE2)
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static void emit_le_ptr8(int cond, int r)
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{
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#if CPU_IS_LE
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if (cond == -1)
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emith_eor_r_imm_ptr(r, 1);
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else
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emith_eor_r_imm_ptr_c(cond, r, 1);
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#endif
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}
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// NB may return either REG or TEMP
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static int emit_get_rbase_and_offs(SH2 *sh2, sh2_reg_e r, int rmode, u32 *offs)
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{
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@ -2608,14 +2630,16 @@ static int emit_get_rbase_and_offs(SH2 *sh2, sh2_reg_e r, int rmode, u32 *offs)
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// if r is in rcache or needed soon anyway, and offs is relative to region,
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// and address translation fits in add_ptr_imm (s32), then use rcached const
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if (la == (s32)la && !(*offs & ~mask) && rcache_is_cached(r)) {
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u32 odd = a & 1; // need to fix odd address for correct byte addressing
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la -= (s32)((a & ~mask) - *offs - odd); // diff between reg and memory
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if (la == (s32)la && !(((a & mask) + *offs) & ~mask) && rcache_is_cached(r)) {
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#if CPU_IS_LE // need to fix odd address for correct byte addressing
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if (a & 1) *offs += (*offs&1) ? 2 : -2;
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#endif
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la -= (s32)((a & ~mask) - *offs); // diff between reg and memory
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hr = hr2 = rcache_get_reg(r, rmode, NULL);
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if ((s32)a < 0) emith_uext_ptr(hr2);
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if ((la & ~omask) - odd) {
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if (la & ~omask) {
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hr = rcache_get_tmp();
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emith_add_r_r_ptr_imm(hr, hr2, (la & ~omask) - odd);
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emith_add_r_r_ptr_imm(hr, hr2, la & ~omask);
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rcache_free(hr2);
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}
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*offs = (la & omask);
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@ -2792,9 +2816,9 @@ static int emit_memhandler_read_rr(SH2 *sh2, sh2_reg_e rd, sh2_reg_e rs, u32 off
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else
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hr2 = rcache_get_reg(rd, RC_GR_WRITE, NULL);
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switch (size & MF_SIZEMASK) {
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case 0: emith_read8s_r_r_offs(hr2, hr, offs ^ 1); break; // 8
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case 1: emith_read16s_r_r_offs(hr2, hr, offs); break; // 16
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case 2: emith_read_r_r_offs(hr2, hr, offs); emith_ror(hr2, hr2, 16); break;
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case 0: emith_read8s_r_r_offs(hr2, hr, MEM_BE2(offs)); break; // 8
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case 1: emith_read16s_r_r_offs(hr2, hr, offs); break; // 16
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case 2: emith_read_r_r_offs(hr2, hr, offs); emit_le_swap(-1, hr2); break;
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}
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rcache_free(hr);
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if (size & MF_POSTINCR)
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@ -5174,7 +5198,7 @@ static void sh2_generate_utils(void)
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emith_sh2_rcall(arg0, arg1, arg2, arg3);
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EMITH_SJMP_START(DCOND_CS);
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emith_and_r_r_c(DCOND_CC, arg0, arg3);
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emith_eor_r_imm_ptr_c(DCOND_CC, arg0, 1);
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emit_le_ptr8(DCOND_CC, arg0);
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emith_read8s_r_r_r_c(DCOND_CC, RET_REG, arg2, arg0);
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emith_ret_c(DCOND_CC);
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EMITH_SJMP_END(DCOND_CS);
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@ -5204,7 +5228,7 @@ static void sh2_generate_utils(void)
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EMITH_SJMP_START(DCOND_CS);
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emith_and_r_r_c(DCOND_CC, arg0, arg3);
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emith_read_r_r_r_c(DCOND_CC, RET_REG, arg2, arg0);
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emith_ror_c(DCOND_CC, RET_REG, RET_REG, 16);
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emit_le_swap(DCOND_CC, RET_REG);
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emith_ret_c(DCOND_CC);
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EMITH_SJMP_END(DCOND_CS);
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emith_move_r_r_ptr(arg1, CONTEXT_REG);
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@ -5221,7 +5245,7 @@ static void sh2_generate_utils(void)
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emith_abijump_reg_c(DCOND_CS, arg2);
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EMITH_SJMP_END(DCOND_CC);
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emith_and_r_r_r(arg1, arg0, arg3);
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emith_eor_r_imm_ptr(arg1, 1);
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emit_le_ptr8(-1, arg1);
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emith_read8s_r_r_r(arg1, arg2, arg1);
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emith_push_ret(arg1);
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emith_move_r_r_ptr(arg2, CONTEXT_REG);
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@ -5257,7 +5281,7 @@ static void sh2_generate_utils(void)
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EMITH_SJMP_END(DCOND_CC);
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emith_and_r_r_r(arg1, arg0, arg3);
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emith_read_r_r_r(arg1, arg2, arg1);
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emith_ror(arg1, arg1, 16);
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emit_le_swap(-1, arg1);
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emith_push_ret(arg1);
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emith_move_r_r_ptr(arg2, CONTEXT_REG);
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emith_abicall(p32x_sh2_poll_memory32);
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