mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
add big endian platform support
This commit is contained in:
kub
parent
b053cb2044
commit
57c5a5e505
21 changed files with 224 additions and 178 deletions
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@ -123,7 +123,6 @@ void Pico32xStartup(void)
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emu_32x_startup();
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}
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#define HWSWAP(x) (((x) << 16) | ((x) >> 16))
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void p32x_reset_sh2s(void)
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{
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elprintf(EL_32X, "sh2 reset");
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@ -143,9 +142,9 @@ void p32x_reset_sh2s(void)
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unsigned int vbr;
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// initial data
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idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000;
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idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000;
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idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc));
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idl_src = CPU_BE2(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000;
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idl_dst = CPU_BE2(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000;
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idl_size= CPU_BE2(*(unsigned int *)(Pico.rom + 0x3dc));
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if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize ||
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idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) {
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elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x",
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@ -155,7 +154,7 @@ void p32x_reset_sh2s(void)
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memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size);
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// VBR
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vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8));
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vbr = CPU_BE2(*(unsigned int *)(Pico.rom + 0x3e8));
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sh2_set_vbr(0, vbr);
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// checksum and M_OK
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@ -169,7 +168,7 @@ void p32x_reset_sh2s(void)
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unsigned int vbr;
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// GBR/VBR
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vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec));
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vbr = CPU_BE2(*(unsigned int *)(Pico.rom + 0x3ec));
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sh2_set_gbr(1, 0x20004000);
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sh2_set_vbr(1, vbr);
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// program will set S_OK
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@ -81,11 +81,11 @@ static void convert_pal555(int invert_prio)
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int i = 320; \
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while (i > 0) { \
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for (; i > 0 && (*pmd & 0x3f) == mdbg; pd++, pmd++, i--) { \
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t = pal[*(unsigned char *)((uintptr_t)(p32x++) ^ 1)]; \
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t = pal[*(unsigned char *)(MEM_BE2((uintptr_t)(p32x++)))]; \
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*pd = t; \
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} \
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for (; i > 0 && (*pmd & 0x3f) != mdbg; pd++, pmd++, i--) { \
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t = pal[*(unsigned char *)((uintptr_t)(p32x++) ^ 1)]; \
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t = pal[*(unsigned char *)(MEM_BE2((uintptr_t)(p32x++)))]; \
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if (t & PXPRIO) \
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*pd = t; \
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else \
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@ -56,7 +56,7 @@ static void (*m68k_write8_io)(u32 a, u32 d);
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static void (*m68k_write16_io)(u32 a, u32 d);
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// addressing byte in 16bit reg
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#define REG8IN16(ptr, offs) ((u8 *)ptr)[(offs) ^ 1]
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#define REG8IN16(ptr, offs) ((u8 *)ptr)[MEM_BE2(offs)]
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// poll detection
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#define POLL_THRESHOLD 5
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@ -1081,7 +1081,7 @@ static void PicoWrite8_32x_on(u32 a, u32 d)
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// TODO: verify
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if ((a & 0xfe00) == 0x5200) { // a15200
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elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
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((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
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((u8 *)Pico32xMem->pal)[MEM_BE2(a & 0x1ff)] = d;
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Pico32x.dirty_pal = 1;
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return;
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}
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@ -1173,7 +1173,7 @@ u32 PicoRead8_32x(u32 a)
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if (PicoIn.opt & POPT_EN_32X) {
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if ((a & 0xffc0) == 0x5100) { // a15100
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// regs are always readable
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d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
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d = ((u8 *)Pico32x.regs)[MEM_BE2(a & 0x3f)];
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goto out;
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}
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@ -1236,7 +1236,7 @@ void PicoWrite8_32x(u32 a, u32 d)
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// allow only COMM for now
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if ((a & 0x30) == 0x20) {
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u8 *r8 = (u8 *)r;
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r8[a ^ 1] = d;
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r8[MEM_BE2(a)] = d;
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}
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return;
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}
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@ -1275,7 +1275,7 @@ void PicoWrite16_32x(u32 a, u32 d)
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#define sh2_write8_dramN(p, a, d) \
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if ((d & 0xff) != 0) { \
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u8 *dram = (u8 *)p; \
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dram[(a & 0x1ffff) ^ 1] = d; \
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dram[MEM_BE2(a & 0x1ffff)] = d; \
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}
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static void m68k_write8_dram0_ow(u32 a, u32 d)
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@ -1315,7 +1315,7 @@ static void m68k_write16_dram1_ow(u32 a, u32 d)
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static void PicoWrite8_hint(u32 a, u32 d)
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{
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if ((a & 0xfffc) == 0x0070) {
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Pico32xMem->m68k_rom[a ^ 1] = d;
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Pico32xMem->m68k_rom[MEM_BE2(a)] = d;
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return;
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}
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@ -1468,9 +1468,9 @@ static u32 REGPARM(2) sh2_read8_cs0(u32 a, SH2 *sh2)
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// TODO: mirroring?
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if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
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d = Pico32xMem->sh2_rom_m.b[a ^ 1];
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d = Pico32xMem->sh2_rom_m.b[MEM_BE2(a)];
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else if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
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d = Pico32xMem->sh2_rom_s.b[a ^ 1];
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d = Pico32xMem->sh2_rom_s.b[MEM_BE2(a)];
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else
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d = sh2_read8_unmapped(a, sh2);
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goto out;
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@ -1493,7 +1493,7 @@ static u32 REGPARM(2) sh2_read8_rom(u32 a, SH2 *sh2)
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{
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u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19;
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s8 *p = sh2->p_rom;
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return p[(bank + (a & 0x7ffff)) ^ 1];
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return p[MEM_BE2(bank + (a & 0x7ffff))];
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}
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// read16
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@ -1569,7 +1569,7 @@ static u32 REGPARM(2) sh2_read32_rom(u32 a, SH2 *sh2)
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u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19;
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u32 *p = sh2->p_rom;
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u32 d = p[(bank + (a & 0x7fffc)) / 4];
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return (d << 16) | (d >> 16);
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return CPU_BE2(d);
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}
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// writes
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@ -1644,7 +1644,7 @@ static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
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if ((a & 0x3fe00) == 0x4200) {
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sh2->poll_cnt = 0;
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((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
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((u8 *)Pico32xMem->pal)[MEM_BE2(a & 0x1ff)] = d;
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Pico32x.dirty_pal = 1;
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goto out;
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}
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@ -1667,7 +1667,7 @@ static void REGPARM(3) sh2_write8_dram(u32 a, u32 d, SH2 *sh2)
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static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = (a & 0x3ffff) ^ 1;
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u32 a1 = MEM_BE2(a & 0x3ffff);
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((u8 *)sh2->p_sdram)[a1] = d;
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#ifdef DRC_SH2
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u8 *p = sh2->p_drcblk_ram;
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@ -1679,7 +1679,7 @@ static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2)
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static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = (a & 0xfff) ^ 1;
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u32 a1 = MEM_BE2(a & 0xfff);
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sh2->data_array[a1] = d;
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#ifdef DRC_SH2
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u8 *p = sh2->p_drcblk_da;
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@ -1805,10 +1805,10 @@ static void REGPARM(3) sh2_write32_cs0(u32 a, u32 d, SH2 *sh2)
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#define sh2_write32_dramN(p, a, d) \
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u32 *pd = &((u32 *)p)[(a & 0x1ffff) / 4]; \
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if (!(a & 0x20000)) { \
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*pd = (d << 16) | (d >> 16); \
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*pd = CPU_BE2(d); \
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} else { \
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/* overwrite */ \
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u32 v = *pd, m = 0; d = (d << 16) | (d >> 16) ; \
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u32 v = *pd, m = 0; d = CPU_BE2(d); \
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if (!(d & 0x000000ff)) m |= 0x000000ff; \
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if (!(d & 0x0000ff00)) m |= 0x0000ff00; \
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if (!(d & 0x00ff0000)) m |= 0x00ff0000; \
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@ -1829,7 +1829,7 @@ static void REGPARM(3) sh2_write32_dram(u32 a, u32 d, SH2 *sh2)
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static void REGPARM(3) sh2_write32_sdram(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0x3fffc;
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*(u32 *)((char*)sh2->p_sdram + a1) = (d << 16) | (d >> 16);
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*(u32 *)((char*)sh2->p_sdram + a1) = CPU_BE2(d);
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#ifdef DRC_SH2
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u8 *p = sh2->p_drcblk_ram;
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u32 t = p[a1 >> SH2_DRCBLK_RAM_SHIFT];
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@ -1842,7 +1842,7 @@ static void REGPARM(3) sh2_write32_sdram(u32 a, u32 d, SH2 *sh2)
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static void REGPARM(3) sh2_write32_da(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0xffc;
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*((u32 *)sh2->data_array + a1/4) = (d << 16) | (d >> 16);
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*((u32 *)sh2->data_array + a1/4) = CPU_BE2(d);
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#ifdef DRC_SH2
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u8 *p = sh2->p_drcblk_da;
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u32 t = p[a1 >> SH2_DRCBLK_DA_SHIFT];
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@ -1876,7 +1876,7 @@ u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
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sh2_map += SH2MAP_ADDR2OFFS_R(a);
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p = sh2_map->addr;
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if (!map_flag_set(p))
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return *(s8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
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return *(s8 *)((p << 1) + MEM_BE2(a & sh2_map->mask));
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else
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return ((sh2_read_handler *)(p << 1))(a, sh2);
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}
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@ -1903,7 +1903,7 @@ u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
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p = sh2_map->addr;
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if (!map_flag_set(p)) {
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u32 *pd = (u32 *)((p << 1) + (a & sh2_map->mask));
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return (*pd << 16) | (*pd >> 16);
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return CPU_BE2(*pd);
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} else
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return ((sh2_read_handler *)(p << 1))(a, sh2);
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}
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@ -1979,7 +1979,7 @@ int p32x_sh2_memcpy(u32 dst, u32 src, int count, int size, SH2 *sh2)
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// align dst to halfword
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if (dst & 1) {
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p32x_sh2_write8(dst, *(u8 *)((uptr)ps ^ 1), sh2);
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p32x_sh2_write8(dst, *(u8 *)MEM_BE2((uptr)ps), sh2);
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ps++, dst++, len --;
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}
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@ -1990,7 +1990,11 @@ int p32x_sh2_memcpy(u32 dst, u32 src, int count, int size, SH2 *sh2)
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u16 dl, dh = *sp++;
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for (i = 0; i < (len & ~1); i += 2, dst += 2, sp++) {
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dl = dh, dh = *sp;
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#if CPU_IS_LE
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p32x_sh2_write16(dst, (dh >> 8) | (dl << 8), sh2);
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#else
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p32x_sh2_write16(dst, (dl >> 8) | (dh << 8), sh2);
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#endif
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}
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if (len & 1)
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p32x_sh2_write8(dst, dh, sh2);
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@ -2014,7 +2018,7 @@ int p32x_sh2_memcpy(u32 dst, u32 src, int count, int size, SH2 *sh2)
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u32 d;
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for (i = 0; i < (len & ~3); i += 4, dst += 4, sp += 2) {
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d = *(u32 *)sp;
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p32x_sh2_write32(dst, (d << 16) | (d >> 16), sh2);
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p32x_sh2_write32(dst, CPU_BE2(d), sh2);
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}
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}
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if (len & 2) {
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@ -2022,7 +2026,7 @@ int p32x_sh2_memcpy(u32 dst, u32 src, int count, int size, SH2 *sh2)
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dst += 2;
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}
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if (len & 1)
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p32x_sh2_write8(dst, *sp >> 8, sh2);
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p32x_sh2_write8(dst, ((u8 *)sp)[MEM_BE2(0)], sh2);
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}
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return count;
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@ -2137,7 +2141,6 @@ static const u16 ssh2_code[] = {
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0x2400, 0x0018, // 23c _start_cd
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};
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#define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16))
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static void get_bios(void)
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{
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u16 *ps;
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@ -2167,7 +2170,7 @@ static void get_bios(void)
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ps = (u16 *)Pico32xMem->m68k_rom;
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pl = (u32 *)ps;
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for (i = 1; i < 0xc0/4; i++)
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pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
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pl[i] = CPU_BE2(0x880200 + (i - 1) * 6);
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pl[0x70/4] = 0;
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// fill with nops
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@ -2197,12 +2200,12 @@ static void get_bios(void)
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// fill exception vector table to our trap address
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for (i = 0; i < 128; i++)
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pl[i] = HWSWAP(0x200);
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pl[i] = CPU_BE2(0x200);
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// start
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pl[0] = pl[2] = HWSWAP(0x204);
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pl[0] = pl[2] = CPU_BE2(0x204);
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// reset SP
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pl[1] = pl[3] = HWSWAP(0x6040000);
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pl[1] = pl[3] = CPU_BE2(0x6040000);
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// startup code
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memcpy(&Pico32xMem->sh2_rom_m.b[0x200], msh2_code, sizeof(msh2_code));
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@ -2218,12 +2221,12 @@ static void get_bios(void)
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// fill exception vector table to our trap address
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for (i = 0; i < 128; i++)
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pl[i] = HWSWAP(0x200);
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pl[i] = CPU_BE2(0x200);
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// start
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pl[0] = pl[2] = HWSWAP(0x204);
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pl[0] = pl[2] = CPU_BE2(0x204);
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// reset SP
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pl[1] = pl[3] = HWSWAP(0x603f800);
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pl[1] = pl[3] = CPU_BE2(0x603f800);
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// startup code
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memcpy(&Pico32xMem->sh2_rom_s.b[0x200], ssh2_code, sizeof(ssh2_code));
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@ -290,7 +290,7 @@ u32 REGPARM(2) sh2_peripheral_read16(u32 a, SH2 *sh2)
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u32 d;
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a &= 0x1fe;
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d = r[(a / 2) ^ 1];
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d = r[MEM_BE2(a / 2)];
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elprintf_sh2(sh2, EL_32XP, "peri r16 [%08x] %04x @%06x",
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a | ~0x1ff, d, sh2_pc(sh2));
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@ -420,7 +420,7 @@ void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
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return;
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}
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r[(a / 2) ^ 1] = d;
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r[MEM_BE2(a / 2)] = d;
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if ((a & 0x1c0) == 0x140)
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p32x_sh2_poll_event(sh2, SH2_STATE_CPOLL, SekCyclesDone());
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}
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