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sh2 drc: rework of register cache to implement basic loop optmization

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kub 2019-09-17 23:02:05 +02:00
parent f53e166cf4
commit 58a444a295
2 changed files with 370 additions and 241 deletions
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608
cpu/sh2/compiler.c
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3
cpu/sh2/compiler.h
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@ -22,6 +22,7 @@ void sh2_drc_frame(void);
#define OF_B_IN_DS (1 << 4)
#define OF_DELAY_INSN (1 << 5) // DT, (TODO ADD+CMP?)
#define OF_POLL_INSN (1 << 6) // MOV @(...),Rn (no post increment), TST @(...)
#define OF_BASIC_LOOP (1 << 7) // pinnable loop without any branches in it
#define OF_IDLE_LOOP (1 << 2)
#define OF_DELAY_LOOP (2 << 2)
@ -39,7 +40,7 @@ unsigned short scan_block(unsigned int base_pc, int is_slave,
#elif defined(__aarch64__)
#define DRC_SR_REG "r22"
#elif defined(__mips__)
#define DRC_SR_REG "s6"
#define DRC_SR_REG "s2"
#elif defined(__i386__)
#define DRC_SR_REG "edi"
#elif defined(__x86_64__)