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https://github.com/RaySollium99/picodrive.git
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svp compiler: some pointer reg handling
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@362 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
f48f5e3b46
commit
5d817c9138
3 changed files with 260 additions and 32 deletions
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@ -12,6 +12,13 @@ static int had_jump = 0;
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static int nblocks = 0;
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static int iram_context = 0;
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#ifndef ARM
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#define DUMP_BLOCK 0x40b0
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unsigned int tcache[512*1024];
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void regfile_load(void){}
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void regfile_store(void){}
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#endif
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#define EMBED_INTERPRETER
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#define ssp1601_reset ssp1601_reset_local
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#define ssp1601_run ssp1601_run_local
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@ -513,36 +520,235 @@ static int get_iram_context(void)
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return val1;
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}
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// -----------------------------------------------------
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/*
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enum {
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SSP_GR0, SSP_X, SSP_Y, SSP_A,
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SSP_ST, SSP_STACK, SSP_PC, SSP_P,
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SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
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SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
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};
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*/
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/* regs with known values */
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static struct
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{
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ssp_reg_t gr[8];
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unsigned char r[8];
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} const_regs;
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#define CRREG_X (1 << SSP_X)
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#define CRREG_Y (1 << SSP_Y)
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#define CRREG_A (1 << SSP_A) /* AH only */
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#define CRREG_ST (1 << SSP_ST)
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#define CRREG_STACK (1 << SSP_STACK)
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#define CRREG_PC (1 << SSP_PC)
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#define CRREG_P (1 << SSP_P)
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#define CRREG_PR0 (1 << 8)
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#define CRREG_PR4 (1 << 12)
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#define CRREG_AL (1 << 16)
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static u32 const_regb = 0; /* bitfield of known register values */
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static u32 dirty_regb = 0; /* known vals, which need to be flushed (only r0-r7) */
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/* known values of host regs.
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* -1 - unknown
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* 00000-0ffff - 16bit value
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* 10000-1ffff - base reg (r7) + 16bit val
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* 20000 - means reg (low) eq AH
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*/
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static int hostreg_r[4];
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static void hostreg_clear(void)
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{
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int i;
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for (i = 0; i < 4; i++)
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hostreg_r[i] = -1;
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}
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/*static*/ void hostreg_ah_changed(void)
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{
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int i;
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for (i = 0; i < 4; i++)
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if (hostreg_r[i] == 0x20000) hostreg_r[i] = -1;
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}
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#define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x]
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static int translate_op(unsigned int op, int *pc)
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/* load 16bit val into host reg r0-r3. Nothing is trashed */
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static void tr_mov16(int r, int val)
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{
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if (hostreg_r[r] != val) {
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emit_mov_const(r, val);
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hostreg_r[r] = val;
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}
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}
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/* write dirty r0-r7 to host regs. Nothing is trashed */
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static void tr_flush_dirty(void)
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{
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int i, ror = 0, reg;
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dirty_regb >>= 8;
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/* r0-r7 */
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for (i = 0; dirty_regb && i < 8; i++, dirty_regb >>= 1)
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{
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if (!(dirty_regb&1)) continue;
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switch (i&3) {
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case 0: ror = 0; break;
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case 1: ror = 24/2; break;
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case 2: ror = 16/2; break;
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}
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reg = (i < 4) ? 8 : 9;
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EOP_BIC_IMM(reg,reg,ror,0xff);
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if (const_regs.r[i] != 0)
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EOP_ORR_IMM(reg,reg,ror,const_regs.r[i]);
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}
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}
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/* read bank word to r0 (MSW may contain trash). Thrashes r1. */
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static void tr_bank_read(int addr) /* word addr 0-0x1ff */
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{
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if (addr&1) {
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int breg = 7;
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if (addr > 0x7f) {
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if (hostreg_r[1] != (0x10000|((addr&0x180)<<1))) {
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EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
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hostreg_r[1] = 0x10000|((addr&0x180)<<1);
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}
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breg = 1;
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}
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EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1); // ldrh r0, [r1, (op&0x7f)<<1]
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} else {
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EOP_LDR_IMM(0,7,(addr&0x1ff)<<1); // ldr r0, [r1, (op&0x1ff)<<1]
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}
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hostreg_r[0] = -1;
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}
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/* write r0 to bank. Trashes r1. */
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static void tr_bank_write(int addr)
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{
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int breg = 7;
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if (addr > 0x7f) {
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if (hostreg_r[1] != (0x10000|((addr&0x180)<<1))) {
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EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
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hostreg_r[1] = 0x10000|((addr&0x180)<<1);
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}
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breg = 1;
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}
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EOP_STRH_IMM(0,breg,(addr&0x7f)<<1); // str r0, [r1, (op&0x7f)<<1]
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}
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/* handle RAM bank pointer modifiers. Nothing is trashed. */
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static void tr_ptrr_mod(int r, int mod, int need_modulo)
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{
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int modulo = -1, modulo_shift = -1; /* unknown */
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if (mod == 0) return;
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if (!need_modulo || mod == 1) // +!
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modulo_shift = 8;
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else if (need_modulo && (const_regb & CRREG_ST)) {
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modulo_shift = const_regs.gr[SSP_ST].h & 7;
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if (modulo_shift == 0) modulo_shift = 8;
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}
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if (mod > 1 && modulo_shift == -1) { printf("need var modulo\n"); exit(1); }
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modulo = (1 << modulo_shift) - 1;
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if (const_regb & (1 << (r + 8))) {
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if (mod == 2)
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const_regs.r[r] = (const_regs.r[r] & ~modulo) | ((const_regs.r[r] - 1) & modulo);
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else const_regs.r[r] = (const_regs.r[r] & ~modulo) | ((const_regs.r[r] + 1) & modulo);
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} else {
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int reg = (r < 4) ? 8 : 9;
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int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
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EOP_MOV_REG_ROR(reg,reg,ror);
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// {add|sub} reg, reg, #1<<shift
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EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, 1<<(8 - modulo_shift));
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EOP_MOV_REG_ROR(reg,reg,32-ror);
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}
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}
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static int translate_op(unsigned int op, int *pc, int imm)
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{
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u32 tmpv;
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int ret = 0;
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switch (op >> 9)
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{
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// ld d, s
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case 0x00:
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if (op == 0) return 1; // nop
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if (op == 0) { ret++; break; } // nop
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break;
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// ld a, adr
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case 0x03:
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EOP_ADD_IMM(0,7,1,30/2,(op&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
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EOP_LDRH_IMM(0,1,(op&0x7f)<<1); // ldr r0, [r1, (op&0x7f)<<1]
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EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16 @ A
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EOP_ORR_REG_SIMPLE(5, 0); // orr r5, r5, r0
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EOP_MOV_REG_ROR(5,5,16); // mov r5, r5, ror #16
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return 1;
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tr_bank_read(op&0x1ff);
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EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
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EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsl #16 @ AL
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EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
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const_regb &= ~CRREG_A;
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hostreg_r[0] = 0x20000;
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ret++; break;
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// ldi (ri), imm
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case 0x06:
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//tmpv = *PC++; ptr1_write(op, tmpv); break;
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// int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
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tr_mov16(0, imm);
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if ((op&3) == 3)
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{
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tmpv = (op>>2) & 3; // direct addressing
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if (op & 0x100) {
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if (hostreg_r[1] != 0x10200) {
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EOP_ADD_IMM(1,7,30/2,0x200>>2); // add r1, r7, 0x200
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hostreg_r[1] = 0x10200;
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}
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EOP_STRH_IMM(0,1,tmpv<<1); // str r0, [r1, {0,2,4,6}]
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} else {
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EOP_STRH_IMM(0,7,tmpv<<1); // str r0, [r7, {0,2,4,6}]
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}
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}
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else
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{
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int r = (op&3) | ((op>>6)&4);
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if (const_regb & (1 << (r + 8))) {
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tr_bank_write(const_regs.r[r] | ((r < 4) ? 0 : 0x100));
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} else {
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int reg = (r < 4) ? 8 : 9;
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int ror = ((4 - (r&3))*8) & 0x1f;
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EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
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if (r >= 4)
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EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
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if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
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else EOP_ADD_REG_LSL(1,7,1,1);
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EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
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hostreg_r[1] = -1;
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}
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tr_ptrr_mod(r, (op>>2) & 3, 0);
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}
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ret++; break;
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// ld adr, a
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case 0x07:
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EOP_ADD_IMM(0,7,1,30/2,(op&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
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if (hostreg_r[0] != 0x20000) {
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EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ A
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EOP_STRH_IMM(0,1,(op&0x7f)<<1); // str r0, [r1, (op&0x7f)<<1]
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return 1;
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hostreg_r[0] = 0x20000;
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}
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tr_bank_write(op&0x1ff);
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ret++; break;
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// ldi ri, simm
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case 0x0c ... 0x0f:
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tmpv = (op>>8)&7;
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const_regs.r[tmpv] = op;
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const_regb |= 1 << (tmpv + 8);
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dirty_regb |= 1 << (tmpv + 8);
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ret++; break;
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}
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return -1;
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return ret;
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}
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static void *translate_block(int pc)
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@ -556,6 +762,8 @@ static void *translate_block(int pc)
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printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
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block_start = tcache_ptr;
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const_regb = dirty_regb = 0;
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hostreg_clear();
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emit_block_prologue();
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@ -569,9 +777,11 @@ static void *translate_block(int pc)
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if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
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imm = PROGRAM(pc++); // immediate
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ret = translate_op(op, &pc);
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ret = translate_op(op, &pc, imm);
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if (ret <= 0)
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{
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tr_flush_dirty();
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emit_mov_const(0, op);
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// need immediate?
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@ -588,6 +798,7 @@ static void *translate_block(int pc)
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exit(1);
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}
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ccount++;
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hostreg_clear();
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}
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else
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ccount += ret;
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@ -599,6 +810,7 @@ static void *translate_block(int pc)
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}
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}
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tr_flush_dirty();
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emit_block_epilogue(ccount + 1);
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*tcache_ptr++ = 0xffffffff; // end of block
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//printf(" %i inst\n", icount);
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@ -615,7 +827,7 @@ static void *translate_block(int pc)
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printf("%i blocks, %i bytes\n", nblocks, (tcache_ptr - tcache)*4);
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//printf("%p %p\n", tcache_ptr, emit_block_epilogue);
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#if 0
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#ifdef DUMP_BLOCK
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{
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FILE *f = fopen("tcache.bin", "wb");
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fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
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@ -652,7 +864,9 @@ void ssp1601_dyn_reset(ssp1601_t *ssp)
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void ssp1601_dyn_run(int cycles)
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{
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//rPC = 0x1272 >> 1;
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#ifdef DUMP_BLOCK
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rPC = DUMP_BLOCK >> 1;
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#endif
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while (cycles > 0)
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{
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int (*trans_entry)(void);
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@ -22,9 +22,12 @@
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#define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
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/* data processing op */
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#define A_OP_AND 0x0
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#define A_OP_SUB 0x2
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#define A_OP_ADD 0x4
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#define A_OP_ORR 0xc
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#define A_OP_MOV 0xd
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#define A_OP_BIC 0xe
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#define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
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EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
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@ -32,12 +35,15 @@
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#define EOP_C_DOP_IMM(cond,op,s,rn,rd,ror2,imm8) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
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#define EOP_C_DOP_REG(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
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#define EOP_MOV_IMM(s, rd,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,s, 0,rd,ror2,imm8)
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#define EOP_ORR_IMM(s,rn,rd,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,s,rn,rd,ror2,imm8)
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#define EOP_ADD_IMM(s,rn,rd,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,s,rn,rd,ror2,imm8)
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#define EOP_MOV_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
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#define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
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#define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
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#define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
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#define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
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#define EOP_MOV_REG(s, rd,shift_imm,shift_op,rm) EOP_C_DOP_REG(A_COND_AL,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
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#define EOP_ORR_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG(A_COND_AL,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_ADD_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG(A_COND_AL,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
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#define EOP_MOV_REG_SIMPLE(rd,rm) EOP_MOV_REG(0,rd,0,A_AM1_LSL,rm)
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#define EOP_MOV_REG_LSL(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSL,rm)
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@ -46,6 +52,14 @@
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#define EOP_MOV_REG_ROR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ROR,rm)
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#define EOP_ORR_REG_SIMPLE(rd,rm) EOP_ORR_REG(0,rd,rd,0,A_AM1_LSL,rm)
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#define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
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#define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
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#define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ASR,rm)
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#define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ROR,rm)
|
||||
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||||
#define EOP_ADD_REG_SIMPLE(rd,rm) EOP_ADD_REG(0,rd,rd,0,A_AM1_LSL,rm)
|
||||
#define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
|
||||
#define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
|
||||
|
||||
/* addressing mode 2 */
|
||||
#define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
|
||||
|
|
@ -64,7 +78,9 @@
|
|||
#define EOP_STR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
|
||||
|
||||
#define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
|
||||
#define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
|
||||
#define EOP_STRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
|
||||
#define EOP_STRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
|
||||
|
||||
/* ldm and stm */
|
||||
#define EOP_XXM(cond,p,u,s,w,l,rn,list) \
|
||||
|
|
@ -90,7 +106,7 @@ static void emit_mov_const(int d, unsigned int val)
|
|||
{
|
||||
int need_or = 0;
|
||||
if (val & 0xff000000) {
|
||||
EOP_MOV_IMM(0, d, 8/2, (val>>24)&0xff);
|
||||
EOP_MOV_IMM(d, 8/2, (val>>24)&0xff);
|
||||
need_or = 1;
|
||||
}
|
||||
if (val & 0x00ff0000) {
|
||||
|
|
@ -162,8 +178,6 @@ static void handle_caches()
|
|||
#ifdef ARM
|
||||
extern void flush_inval_caches(const void *start_addr, const void *end_addr);
|
||||
flush_inval_caches(tcache, tcache_ptr);
|
||||
#else
|
||||
#error wth
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -38,8 +38,8 @@ flush_inval_caches:
|
|||
@ r5: A
|
||||
@ r6: STACK and emu flags
|
||||
@ r7: SSP context
|
||||
@ r8: r0-r2
|
||||
@ r9: r4-r6
|
||||
@ r8: r0-r2 (.210)
|
||||
@ r9: r4-r6 (.654)
|
||||
@ r10: P
|
||||
@ r11: cycles
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue